JPH0370262A - Image scanner control circuit - Google Patents

Image scanner control circuit

Info

Publication number
JPH0370262A
JPH0370262A JP1204857A JP20485789A JPH0370262A JP H0370262 A JPH0370262 A JP H0370262A JP 1204857 A JP1204857 A JP 1204857A JP 20485789 A JP20485789 A JP 20485789A JP H0370262 A JPH0370262 A JP H0370262A
Authority
JP
Japan
Prior art keywords
scanner
register
counter
scanning
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1204857A
Other languages
Japanese (ja)
Inventor
Hiroshi Sakamoto
裕志 坂本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1204857A priority Critical patent/JPH0370262A/en
Publication of JPH0370262A publication Critical patent/JPH0370262A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the processing performance by setting a register value according to an original size to be read and applying a coincidence signal output resulting the comparison of a comparator to a CPU. CONSTITUTION:At first a CPU 1 sets the number of subscanning signals to a register 2 when the length (y) of an original G is scanned by a scanner S and a counter 3 counts the subscanning signal outputted from the scanner S when being moved in the subscanning direction (in the direction of arrow). Thus, as soon as a carriage mounting a sensor of the scanner S finishes the scanning of the original G, the content of the register 2 and the counted value of the counter 3 are coincident. That is, the coincidence signal is interrupted from a comparator 4 to the CPU 1 to make the input of a picture data to a personal computer complete. In this case, the scanner S applies the remaining scanning of the readable range although no picture data is outputted. The succeeding data processing is attained without waiting for the end of the scanning of the scanner S.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、パソコンやDTP(デスクトップパブリッシ
ング装置)における、図形や写真等の画像データを入力
するイメージスキャナ制御回路に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an image scanner control circuit for inputting image data such as graphics and photographs in a personal computer or a DTP (desktop publishing device).

(従来の技術) 近年、図形や写真等の画像データをパソコンやDTP等
に入力するために、イメージスキャナ(以下、単にスキ
ャナという)が用いられるようになった。
(Prior Art) In recent years, image scanners (hereinafter simply referred to as scanners) have come to be used to input image data such as figures and photographs into personal computers, DTPs, and the like.

第3図は、そのスキャナの出力信号波形を例示したもの
で、aは図形等の画像読取りの開始、および終了を制御
するスタートエンド信号、bは1行(1分解能)の主走
査方向のデータが有効であることを示す主走査信号、C
は主走査信号す中に出力される画像データ、dは副走査
信号であり、センサを搭載したキャリッジが1列移動す
る度にパルス1個を送出する。eは画像データCの同期
をとるためのクロック信号である。
Figure 3 shows an example of the output signal waveform of the scanner, where a is a start/end signal that controls the start and end of reading images such as figures, and b is data in the main scanning direction of one line (one resolution). A main scanning signal indicating that C is valid.
d is the image data output in the main scanning signal, and d is the sub-scanning signal, which sends out one pulse each time the carriage carrying the sensor moves one row. e is a clock signal for synchronizing the image data C.

上記のような画像データ信号の出力中、スキャナの原稿
読取りの終了は、スタートエンド信号aがLレベル(低
レベル)からHレベル(高レベル)になるレベル変化を
、第4図のようにスキャナ31からパソコン等32に有
するCPU(中央処理装置)33に割込み入力して行っ
ている。
While outputting the image data signal as described above, the end of the scanner's document reading is determined by the level change of the start/end signal a from L level (low level) to H level (high level) as shown in Figure 4. This is done by inputting an interrupt from 31 to a CPU (central processing unit) 33 in a personal computer or the like 32.

(発明が解決しようとする課題) 上記のように従来の構成ではJスキャナ出力のスタート
エンド信号aをCPUに印加する手段によって、原稿読
取りの終了を検知しているから。
(Problems to be Solved by the Invention) As described above, in the conventional configuration, the end of document reading is detected by means of applying the start/end signal a of the J scanner output to the CPU.

スキャナの読取り可能な原稿サイズに比べて小さな原稿
であっても、スキャナは常に所定の原稿サイズ最後の走
査後に発生される、スタートエンド信号aのレベル変化
を待って読取りが終了することになる。すなわち、読取
り原稿の大きさと無関係に、スキャナの原稿を読む時間
が一定であるため時間的な無駄があり1画像データ入力
システムの機能を低下する問題点がある。
Even if the original is smaller than the original size that can be read by the scanner, the scanner always waits for a change in the level of the start/end signal a, which is generated after the last scan of a predetermined original size, to complete reading. That is, since the time required for reading the document by the scanner is constant regardless of the size of the document to be read, there is a problem in that time is wasted and the function of the single-image data input system is degraded.

本発明は上述の問題点を解決するスキャナ制御回路の提
供を目的とする。
The present invention aims to provide a scanner control circuit that solves the above-mentioned problems.

(課題を解決するための手段) 本発明は上記の目的を、スキャナが発生する副走査信号
のパルス数を計数するカウンタと、任意にレジスト値が
設定可能なレジスタと、それらのカウンタ出力とレジス
ト設定値とを比較するコンパレータとを備え、読取る原
稿サイズに従ってレジスタ値を設定し、上記コンパレー
タが比較した一致信号出力をCPUに印加する構成によ
って達成する。
(Means for Solving the Problems) The present invention has achieved the above object by providing a counter that counts the number of pulses of a sub-scanning signal generated by a scanner, a register that can arbitrarily set a register value, and a counter output and a register. This is achieved by a configuration in which a register value is set according to the document size to be read, and a match signal output compared by the comparator is applied to the CPU.

(作 用) 本発明によれば、原稿の長さに従ってレジスト値を設定
することにより、その設定値に副走査信号のカウンタ値
が一致すると、一致信号が画像データを入力するパソコ
ンまたはDTPに有するCPUに印加され画像データの
入力が終了する。すなわち、スキャナが所定の原稿サイ
ズ−杯まで、残る走査をする時間をCPUは他の処理を
することが可能になり、パソコン等の画像処理時間が短
縮される。
(Function) According to the present invention, by setting the registration value according to the length of the original, when the counter value of the sub-scanning signal matches the set value, a matching signal is sent to the personal computer or DTP into which image data is input. The signal is applied to the CPU, and input of image data is completed. That is, the CPU can perform other processing while the scanner scans the remaining document size up to a predetermined original size, and the image processing time of a personal computer or the like is shortened.

(実施例) 以下、本発明の実施例を図面を用いて説明する。(Example) Embodiments of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例の構成を示すブロック図で、
Sはスキャナ、Pは画像データを入力するパソコンまた
はDTP(以下、これらをパソコン等という)に有する
CPU(1)、2はパソコン等のキーボード操作により
CPUIから直接レジスト値の設定が可能なレジスタ、
3はスキャナが発生する副走査信号を計数するカウンタ
、4は上記レジスタ2の設定されたレジスト値と、上記
カウンタ3の副走査信号のカウント出力を比較するコン
パレータで、比較結果が一致すると一致信号がCPUI
に印加される。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
S is a scanner, P is a CPU (1) included in a personal computer or DTP (hereinafter referred to as a personal computer, etc.) that inputs image data, and 2 is a register that allows register values to be set directly from the CPUI by keyboard operation of a personal computer, etc.
3 is a counter that counts the sub-scanning signals generated by the scanner, and 4 is a comparator that compares the register value set in register 2 and the sub-scanning signal count output of counter 3. If the comparison results match, a match signal is issued. is the CPUI
is applied to

第2図は読取りの例を示す図で、Gは副走査方向の原稿
の長さがyである読取るべき原稿、RはスキャナSの読
取り可能範囲で、副走査方向の長さをY(ただしY >
 y )とする。初めに第1図のCPUIによってレジ
スタ2に、原稿Gの長さyをスキャナSが走査したとす
るときの副走査信号数を設定する。つぎにスキャナSが
副走査方向(矢印)に移動する度に出力する上記副走査
信号を上記カウンタ3によりカウントさせる。それによ
り。
Figure 2 is a diagram showing an example of reading, where G is the document to be read whose length in the sub-scanning direction is y, R is the readable range of the scanner S, and the length in the sub-scanning direction is Y (where Y>
y). First, the number of sub-scanning signals when the scanner S scans the length y of the document G is set in the register 2 using the CPUI shown in FIG. Next, the counter 3 counts the sub-scanning signal outputted every time the scanner S moves in the sub-scanning direction (arrow). Thereby.

スキャナSのセンサを搭載したキャリッジが原稿G上の
走査を終了すると同時に、上記レジスタ2のレジスト値
と上記カウンタ3のカウント値とが一致する。すなわち
、その一致信号を上記コンパレータ4からCPUIに割
込ませることにより、パソコン等への画像データの入力
が終了する。このときスキャナSは読取り可能範囲の残
る走査を。
At the same time as the carriage carrying the sensor of the scanner S finishes scanning the document G, the registration value of the register 2 and the count value of the counter 3 match. In other words, inputting the image data to the personal computer or the like is completed by causing the comparator 4 to interrupt the CPUI with the coincidence signal. At this time, the scanner S scans the remaining readable range.

画像データを出力しないが行うことになる。言換えると
パソコン等はスキャナSの走査完了を待たずに、次のデ
ータ処理を行うことが可能になる。
It does not output image data, but it does. In other words, the personal computer or the like can perform the next data processing without waiting for the scanner S to complete scanning.

(発明の効果) 以上説明して明らかなように本発明は、パソコンやDT
P本体がスキャナに対して処理を要求する時間が、原稿
の大きさによって短く変化し、したがって、システム全
体としての性能が向上することになり生産の向上につな
がる効果がある。
(Effects of the Invention) As is clear from the above explanation, the present invention can be applied to personal computers and DTs.
The time required by the P main body to request processing from the scanner is shortened depending on the size of the document, and therefore the performance of the entire system is improved, which has the effect of leading to improved production.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の構成を示すブロック図、第
2図は第1図の説明補助図で小さな原稿の読取りを示す
図、第3図はスキャナの出力信号を示す波形図、第4図
は従来のデータ読取り終了のCPU割込みを示す図であ
る。 1・・・CPU、  2・・・レジスタ、  3・・・
カウンタ、  4・・・コンパレータ、  S・・・イ
メージスキャナ(スキャナと略す)、  P・・・パソ
コン等、 G・・・原稿、 R・・・スキャナの読取り
可能範囲。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is an auxiliary diagram for explaining FIG. FIG. 4 is a diagram showing a conventional CPU interrupt at the end of data reading. 1...CPU, 2...Register, 3...
Counter, 4...Comparator, S...Image scanner (abbreviated as scanner), P...PC, etc., G...Original, R...Readable range of the scanner.

Claims (1)

【特許請求の範囲】[Claims] イメージスキャナのキャリッジが副走査方向に1分解能
移動する度に、1個のパルスとして出力する副走査信号
と、そのパルス数を計数するカウンタと、任意のカウン
ト値の設定が可能なレジスタと、それらのカウンタ出力
とレジスタ設定値とを比較するコンパレータとを備え、
読取る原稿サイズに従って上記レジスタにレジスト値を
設定し、上記カウンタの副走査信号パルスの計数値とを
、上記コンパレータにより比較し、その一致信号を画像
信号データを処理するパソコン等に有するCPUに印加
して、画像データの入力を終了とすることを特徴とする
イメージスキャナ制御回路。
A sub-scanning signal that is output as one pulse each time the carriage of the image scanner moves by one resolution in the sub-scanning direction, a counter that counts the number of pulses, a register that can set an arbitrary count value, and these. Equipped with a comparator that compares the counter output with the register setting value,
A registration value is set in the register according to the size of the original to be read, the count value of the sub-scanning signal pulse of the counter is compared with the count value of the sub-scanning signal pulse by the comparator, and the matching signal is applied to a CPU included in a personal computer etc. that processes image signal data. An image scanner control circuit characterized in that the input of image data is terminated.
JP1204857A 1989-08-09 1989-08-09 Image scanner control circuit Pending JPH0370262A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1204857A JPH0370262A (en) 1989-08-09 1989-08-09 Image scanner control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1204857A JPH0370262A (en) 1989-08-09 1989-08-09 Image scanner control circuit

Publications (1)

Publication Number Publication Date
JPH0370262A true JPH0370262A (en) 1991-03-26

Family

ID=16497549

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1204857A Pending JPH0370262A (en) 1989-08-09 1989-08-09 Image scanner control circuit

Country Status (1)

Country Link
JP (1) JPH0370262A (en)

Similar Documents

Publication Publication Date Title
EP0767575A3 (en) Scanner server apparatus and scanner server system
JPS62501952A (en) Document resolution adaptation method and apparatus
JPH0370262A (en) Image scanner control circuit
US5812706A (en) Scanner of any type of document and implementatioin process for said scanner
JPS621370A (en) Image processing method for digital copying machine or the like
JPS62239662A (en) Original document processor
US5408635A (en) Method of controlling data output by direct memory access
JP2669642B2 (en) Image reading device
JPH01191981A (en) Picture processing display system
JPH02107059A (en) Line density converting circuit for facsimile equipment
JP2547147Y2 (en) Data movement editing device
JP2855630B2 (en) Image input device
JPS61198872A (en) Picture input device
JPH07212581A (en) Composite equipment
JPH11341232A (en) Image reader
JPS6132653A (en) Picture inputting device
JPS62144464A (en) Image signal processor
JPH01305479A (en) Method for transferring data to be set on image input device
KR20000051665A (en) Method of printing warning message on paper to protect illegal copy in digital color copier
JPH01312673A (en) Interface circuit for image scanner device
JPS639274A (en) Partial variable power device
JPS62103776A (en) Optical picture reading device
JPS60250485A (en) Optical character reading device
JPS63121359A (en) Picture processor
JPS6331829B2 (en)