JPH0369285A - Charge transfer device driving device - Google Patents

Abstract

PURPOSE:To prevent the generation of shading by correcting the driving voltage of a charge transfer device to a value differently from a value obtained immediately after starting a slow drive when a 1st timing signal is generated immediately after starting a fast driving. CONSTITUTION:When a MPU 1 outputs a signal PHV to a timing generator 2 synchronously with a vertically synchronizing signal inputted from the generator 2 to command fast driving, signals V1 to V4 and V1 to V4 are respectively rapidly outputted to a driver 3 and a CCD 4. At the timing of generating a signal TG immediately after the fast outputs, the MPU 1 inverts a signal PV to a low level. Thereby, a VH power supply circuit 32 turns off a switch 48 and releases the shortcircuit of a resistor 47. Consequently, an output voltage VH is increased. The increment of voltage is set up correspondingly to voltage drop due to an impedance change equivalent to the capacity of a resistor at the time of fast driving. Thereby, the output voltage VH is made approximately equal to the value of slow drive.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a charge transfer element driving device for driving a charge transfer element typified by a COD.

[Conventional technology]

FIG. 2 is a block diagram showing the configuration of an example of a conventional charge transfer element driving device used in a television camera.

In the figure, 1 is a microprocessor unit (MP
U) and controls the operation of each circuit, means, etc. 2 is a timing generator that generates signals V1 to V4 and a signal TO as timing signals. 3 is a driver, which operates a CCD 4 as a charge transfer element in response to a timing signal inputted from the timing generator 2.
to drive. A power supply circuit 5 supplies a predetermined voltage necessary for the driver 3.

FIG. 3 is a plan view showing a more detailed configuration of the interline type COD as COD'4.

In the figure, 11 is a photodiode, which generates a charge corresponding to incident light. 12 is vertical transfer CO
D, and the charge generated by the photodiode 11 is transferred to the horizontal transfer CCD 13 or the drain drain 14. 15 is a floating diffusion amplifier (
FDA) converts the charge transferred from the horizontal transfer CCD 13 into a voltage and outputs it. Reference numeral 16 denotes an overflow drain for discharging charges overflowed by strong light irradiation.

Next, the operation of the apparatus shown in FIG. 2 will be explained with reference to the timing chart shown in FIG.

When the signal TG is input from the timing generator 2, the driver 3 selects the highest voltage Vw among the voltages supplied from the power supply circuit 5.

Then, corresponding to the signal vl or V generated from the timing generator 2, the signal φV□ or φ of the voltage Vm
Generate V3 and supply it to CCD4. Thereby, the charges accumulated in the photodiode 11 are transferred to the adjacent vertical transfer CCD 12.

Further, the driver 3 outputs signals φV to φ in response to signals V to φ inputted from the timing generator 2.
V4 is generated and output to CCD4.

The charge transferred to the vertical transfer CCD 12 is transferred to this signal φV.
The signals are sequentially transferred to the horizontal transfer CCD 13 through φV4. When the signal TG is not input, the signals φV1 to φV
4 is a signal represented by two values: the lowest voltage V and a voltage vH intermediate between the voltages vL and VM.

Signals φH1 and φH3 are supplied to the horizontal transfer CCD 13 from a horizontal drive driver (not shown). As a result, the charges transferred to the horizontal transfer CCD 13 are transferred to the FDA 15.
The voltage is inputted to the circuit, converted to voltage, and read out.

In this way, the photodiode 1 constituting each pixel
Charges accumulated corresponding to the subject at 1 are outputted from the CCD 4 as a video signal.

On the other hand, when operating a so-called electronic shutter, it is necessary to read out only the charges accumulated in a predetermined period as described above. Therefore, charges accumulated during unnecessary periods other than that period are discarded.

A normal read operation is performed in units of fields in synchronization with horizontal and vertical synchronizing signals of a video signal. If the operation of discarding unnecessary charges is performed at the same speed as the normal read operation, the normal read operation will be interrupted during that time.

This operation of discarding unnecessary charges must be performed at high speed so that the normal read operation is not interrupted.

When performing an operation to discard this unnecessary charge.

The MPUI outputs a signal Pllv to the timing generator 2 in synchronization with the vertical synchronization signal (VD) (FIG. 4(a)) input from the timing generator 2. When the signal P Hv is input, the timing generator 2
outputs the signals vl to v4 at high speed and in the opposite phase to that in the case of low speed (normal read operation) (FIG. 4(b)). As a result, the signals φV to φV input to the CCD 4,
(FIG. 4(b)) is also high speed and reverse phase. As a result, the charge of the vertical transfer CC: D12 is transferred to the drain drain 14 and discarded.

[Problem to be solved by the invention]

An equivalent circuit when driving the CCD 4 (vertical transfer CCD 12) by the driver 3 can be expressed as shown in FIG.

In the figure, 21 is a resistance of a power supply line to which voltage vll is supplied from the power supply circuit 5, and 22 is an equivalent capacitance of the vertical transfer CCD 12.

For example, when the signal φV1 changes from the voltage Vs (ground potential) to V(), a current flows from the equivalent capacitance 22 to the power supply circuit 5 via the driver 3, as shown by the broken line in the figure. When □ changes from the voltage VL to V-, current flows not from the voltage VM supply source but from the voltage V and the supply source via the resistor 2 and driver 3 to the equivalent capacitance 22. .

Since these currents and the values of the equivalent capacitance 22 are relatively large,
The voltage drop during high-speed driving is greater than during low-speed driving. As a result, as shown in FIG. 4 (Q), the voltage Vm
is lower than when driving at low speed.

When the high-speed drive is stopped, the voltage Vll returns to its original level, but due to the equivalent capacitance 22 of the vertical transfer CCD 12,
Its recovery will take some time, as in the case of a decrease.

However, an operation for transferring the charges accumulated in the photodiode 11 by the electronic shutter operation to the vertical transfer CCD 12 is performed immediately after the charges are swept out by this high-speed drive. Therefore, the voltage VW multiplied by TG, the voltage V, is generated before it is completely recovered, and T
The G-times signal level becomes a value slightly lower than the original value (4th
Figure (b)).

As a result, from the photodiode 11 to the vertical transfer CCD 1
The charge cannot be completely transferred to 2.

Some amount of charge will remain in the photodiode 11. This causes a so-called shading phenomenon in which, for example, the peripheral area of the screen becomes darker or brighter than the central area, resulting in deterioration of image quality.

This phenomenon occurs in FIT (frame interline transfer) type CCDs as shown in Fig. 6.
appear more prominently.

That is, the FIT type CCD temporarily stores the charges transferred from the vertical transfer CCD 12 in the memory area 25, and then stores the charges stored in the memory area 25 in the horizontal transfer CCD 1.
3 are output sequentially.

Transfer to this memory area 25 is also performed by the photodiode 11.
This is done at high speed to ensure sufficient exposure time. Therefore, in this case as well, the voltage (2) is lower than when driving at low speed.

Such a phenomenon can also be prevented by, for example, connecting a large capacity capacitor to the power supply circuit 5. However, if this is done, the circuit scale becomes large and the device becomes large.

This invention was made in view of this situation,
The purpose of this invention is to prevent a drop in the level of a timing signal generated immediately after high-speed driving without increasing the size of the device, thereby preventing image quality deterioration such as shading from occurring.

[Means for Solving Problem 11] In the charge transfer element driving device of the present invention, a first timing signal for transferring charges from the photodiode to the charge transfer element, and a second timing signal for sequentially transferring charges to the charge transfer element are provided. a driver for driving the charge transfer element in response to the first and second timing signals output from the generation means; a power supply circuit for supplying a predetermined voltage to the driver; When the first timing signal is generated immediately after driving the charge transfer element at a high speed with the second timing signal, the value is different from that when the first timing signal is generated immediately after driving the charge transfer element at a low speed. and control means for controlling the voltage supplied to the driver from the power supply circuit.

[Effect]

In the charge transfer element driving device having the above configuration, when high-speed driving is performed by the second timing signal, when the first timing signal is generated immediately after that, the driving voltage of the driver is changed to the same level as that immediately after low-speed driving. For example, it may be increased.

Therefore, it is possible to prevent the level of the first timing signal from decreasing, thereby preventing the occurrence of shading.

〔Example〕

FIG. 1 is a plan view showing the structure of an embodiment of a charge transfer element driving device of the present invention, and parts corresponding to those in FIG. 2 are given the same reference numerals.

In FIG. 1, the power supply circuit is connected to the power supply unit 31 and ■-
The power supply circuit 32 consists of two parts. The power supply unit 31 generates voltages V, , v, and vll,
The power is supplied to the driver 3 and the Vl power supply circuit 32, respectively. The Vl power supply circuit 32 generates a voltage V from the input voltage VW and outputs it to the driver 3.

(2) The power supply circuit 32 is controlled by the MPU 1 as a control means.

The other configurations are the same as in FIG. 2. Further, as for the CCD 4, an interline type or FIT type CCD having a configuration as shown in FIG. 3 or FIG. 6 is used.

FIG. 7 is a block diagram showing the configuration of one embodiment of the VU power supply circuit 32.

In the figure, 41 is a capacitor, and the voltage Vlli
is smoothed and supplied to the voltage regulator 49. The voltage regulator 49 converts the voltage VM into a voltage V□ and outputs it. The voltage vl is converted into a voltage Vm by a bias circuit including resistors 45 to 47 and capacitors 42 and 43, smoothed by a smoothing capacitor 44, and output. A switch 48 is connected in parallel to the resistor 47, and is turned on and off by a signal Pv output by the MPUI.

FIG. 8 shows the configuration of one embodiment of the driver 3.

In the same figure, 61 is a switch, and when the signal obtained by inverting the signal TG by the inverter 64 is at a high level, the voltage V
, respectively, are switched between terminals a and b to select the voltage VM when at a low level. 62 is also a switch, and the voltage from switch 61 supplied to terminal a,
By selecting one of the voltages VL supplied to the terminals, the signal φ
Output as V-engine. The switch 62 connects the terminal a when the signal obtained by inverting the signal V□ by the inverter 65 is at a high level.
When the level is low, it can be switched to the terminal side.

The voltages VM and V are applied to terminals a and b of the switch 63.

are supplied respectively, and the selected one is supplied with the signal φV2.
It is now output as . Sui.

The terminal 63 is switched to the terminal a side when the signal V, which is inverted by the inverter 66, is at a high level, and to the terminal a side when the signal is at a low level.

From the signals Vl and V4, the signal φV3. The circuit that generates φV4 is similarly configured. In this case, the signal V□ is
3, and the signal V2 corresponds to the signal V4, respectively.

Next, the operation will be explained with reference to the timing chart of FIG.

During normal low-speed operation, the signal PV (9th
TJACd)) is considered to be at a high level. Due to this.

The switch 48 of the V, power supply circuit 32 is turned on.

As a result, the resistor 47 is short-circuited, and one end of the resistor 46 is grounded via the switch 48. As a result, the resistance is 45.
Let the resistance values of 46 be R□ and R2, respectively.

V, the output voltage Vw of the power supply circuit 32 is VII=V1
(1+Rg/Rz) ” ” ”
(1) becomes.

The voltage VW generated in this way is supplied to the terminal a of the switch 61. Further, voltages V8 and VL output from the power supply unit 3 are supplied to the terminals of the switch 61 and the terminal a of the switch 63, or to the terminals of the switches 62 and 63, respectively.

Then, as in the case described above, in the driver 3,
The signals φV□ to φ correspond to the signal TO as the second timing signal outputted from the timing generator 2 and the signals V4 to V4 as the second timing signals.
V is generated, and the CCD 4 is driven at a normal low speed.

Since the driving speed at this time is low, the vertical transfer CC
The impedance at the equivalent capacitance 22 of D12 is relatively small, and the resulting voltage drop is also relatively small, so
The voltage v- is maintained at approximately a predetermined value (FIG. 9(e)).

Next, the MPU 1 inputs the vertical synchronizing signal (VD) input from the timing generator 2 (see FIG. 9).
When the signal PIv is output in synchronization with a)) to command high-speed driving, the signals VL to V4 are sent to the driver 3, and the signals φV1 to φV4 are sent to the CCD 4, as in the case described above.
and are output at high speed (FIG. 9(b)). As a result, the charges of the vertical transfer CGDI2 are swept out at high speed.

Also, immediately after that, at the timing when the signal TG is issued, the MPUI inverts the signal Pv to a low level (
FIG. 9(d)) As a result, the switch 48 in the v1 power supply circuit 32 is turned off, and the short circuit of the resistor 47 is released. As a result, when the resistance value of the resistor 47 is R1, the output voltage vl of the Vl power supply circuit 32 is Vm"VM(1"(Ry"
Ra)/Rx) ・” ・(2) Comparing equations (2) and (1), since the voltage is positive, the resistance value R1 in equation (2) is better. (the absolute value increases in the positive direction).

This increase is set to correspond to the voltage decrease due to impedance changes of the resistor 21 and equivalent capacitance 22 during high-speed driving.

As a result, if the voltage VII set by equation (1) is output as is, as shown in FIG. 9(c).

The voltage V, which decreases due to voltage drop, is corrected by that amount, so i! The pressure is.

As shown in FIGS. 7(b) and 7(e), it is approximately the same as in the case of low-speed driving.7 [Effects of the Invention] As described above, according to the charge transfer element driving device of the present invention, the charge transfer Since the driving voltage of the element is corrected to a different value when the first timing signal is generated immediately after high-speed driving than when it is generated immediately after low-speed driving, the engraver's timing signal can be adjusted without increasing the size of the device. It is possible to prevent the level from decreasing and therefore from causing shading.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a charge transfer device driving device of the present invention, FIG. 2 is a block diagram showing the configuration of an example of a conventional charge transfer device driving device, and FIG. 3 is an interline type A schematic plan view showing the configuration of the COD, Figure 4 is a timing chart explaining the operation of the device in Figure 2, Figure 5 is an equivalent circuit explaining the operation of the COD drive, and Figure 6 is the configuration of the FIT type COD. FIG. 7 is a block diagram showing the configuration of an embodiment of the VI power supply circuit of the present invention. FIG. 8 is a block diagram showing the configuration of an embodiment of the driver of the present invention, and FIG. 9 is a timing chart explaining the operation of the devices shown in FIGS. 1, 7, and 8. Engineering: Microprocessor unit 2 ・ ・ 3 ・ ・ 4 ・ ・ 5 ・ ・ 11 ・ 12 ・ 13 ・ 14°・ Engineering 5 ・ Pu16 ・ ・ 21 ・ ・ 22 ・ ・ 25 ・ ・ 31 ・ ・ 32 ・ ・9-- 61.6 ・Timing generator/driver/COD ・Power supply circuit ・・Photodiode ・・Vertical transfer COD ・・Horizontal transfer CCD ・・Sweep drain ・Floating diffusion an ・ O-half 0-drain ・Resistance ・Equivalent capacitance・Memory area ・Power supply unit ・V- power supply circuit ・Voltage regulator 2.63...switch

Claims (1)

[Scope of Claims] Generating means for generating a first timing signal for transferring charge from a photodiode to a charge transfer element and a second timing signal for sequentially transferring charge to the charge transfer element; a driver that drives the charge transfer element in response to the outputted first and second timing signals; a power supply circuit that supplies a predetermined voltage to the driver; and a power supply circuit that drives the charge transfer element according to the second timing signal. The power supply circuit controls the driver so that when the first timing signal is generated immediately after driving the charge transfer element at a high speed, it has a different value than when it is generated immediately after driving the charge transfer element at a low speed. A charge transfer element driving device comprising a control means for controlling a voltage supplied to the charge transfer element.