JPH0368295A - Bs tuner accommodating to high vision broadcast - Google Patents

Abstract

PURPOSE:To reduce the cost through the elimination of a downconverter by averaging the result of count to detect a deviation in a 2nd intermediate frequency thereby controlling a PLL circuit. CONSTITUTION:A keyed APC pulse P is inputted to a BS tuner 16 from a MUSE decoder 70 at the reception of a MUSE broadcast and inputted to a retriggerable monostable multivibrator 120 via a buffer circuit 124, which outputs a MUSE discrimination signal. Thus, a switch 122 is thrown to the position of an output inverting circuit 126, the keyed AFC is inputted to a microcomputer 32, a counter circuit 46 is operated at the input, a 2nd IF intermediate frequency is counted to average the count.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present application relates to satellite broadcast receiving technology, and relates to an indoor receiver called a BS tuner. In particular, the present invention relates to BS tuner technology that can support high-definition television broadcasting transmitted using the MUSE system.

(b) Conventional technology In normal satellite broadcasting, a video signal of the NTSC standard is FM modulated and transmitted as a FM video signal of 1.2 GHz (4t).

On the receiving side, this 12 GHz band FM video signal is
．． After converting to the first intermediate frequency signal of the G I (, band), and sequentially down-converting to the second intermediate frequency signal of the frequency band including 402.78 MHz, Ii'
M demodulates and outputs a video signal.

The oscillation frequency of the local oscillation circuit for down-converting is well controlled by an AFC circuit (automatic frequency control circuit).

AFC operation is performed by a plurality of circuits forming an AFC loop.

Normal AFC utilizes the fact that the DC signal level of the synchronizing signal portion of the video signal output from the FM demodulation circuit corresponds to the frequency of the second intermediate frequency signal, and detects the level of this DC signal. Based on the results, the oscillation frequency of the local oscillation circuit was feedback-controlled (Japanese Patent Laid-Open No. 57-135
582).

However, DC signals have the disadvantage of being susceptible to drift and the like.

For this reason, a technique has been considered in which the frequency of the second intermediate frequency signal (hereinafter referred to as 21F signal) is counted and the local oscillation frequency is feedback-controlled using this count data.

This example will be briefly explained with reference to FIGS. 5 and 6.

In Figure i5, (10) is the BS antenna.

(11) is an antenna section, for example, a parabolic antenna or a planar antenna. (]2) is the first converter. The first converter (12) receives the received 12GHz
The ifF satellite broadcasting signal (FM video signal) and the output of the internal oscillation circuit (13) are mixed in the mixing circuit (14) to generate approximately I
G) i Outputs the J# FM video signal (first intermediate frequency signal) (11th F signal). Its output fluctuation is ±1
．． Up to 5MHz is allowed. Furthermore, this variation is
Corrected by AFC operation.

(16) is a BS tuner. (18) is a second down converter, which is advantageous for converting the i i i;'' signal into multiple channels, for example, the 21st down converter of 402.78M II z.
Convert to F signal. (20) and (24) are automatic gain control amplifier circuits. (22) is a mixing circuit. (26)
is a variable oscillation circuit, (28) is a prescaler that performs frequency division by 172, and (30) is a PLL loop circuit.

This PLL loop circuit (30) is a circuit (26) (2g
) and "() to form a PLI loop. The channel selection microcomputer (32) selects the receiving channel by switching the division ratio of the program divider built in the P I-L loop circuit (30). At the same time, AFC for fine tuning is also performed.
Regarding L-rupu, please refer to Japanese Patent Application Laid-open No. 60-77533 (HO
4B1/16), etc., and is well known, so its explanation will be omitted.

(34) is an FM demodulation block. (36) is the second I
F filter, (38) is amplifier, (40) is PLT-
This is a type FM demodulation circuit. (42) is an AGC detection circuit that creates an AGC voltage. (44) is made by ECL 1/25
It is a divide-by-6 circuit.

(46) is a counter circuit that directly counts the output signal of the 1/256 frequency dividing circuit. This counter circuit (46)
The reset and counting operation periods are controlled by a microcomputer (32), and count data is output to this microcomputer (32).

(48) is an audio DPSK signal demodulation circuit. (50)
is a PCM decoder. This PCM decoder is, for example, TM4218N manufactured by Toshiba Corporation, and is provided with a terminal (50a) for outputting a signal (NSYNC) when receiving an audio PCM signal of NTSC broadcasting. (52) is an audio output circuit that performs digital-to-analog conversion and is also connected to a low-pass filter. (54) is an encoder for outputting digital equipment. (56) is a buffer amplifier. (58)
is a low-pass filter de-emphasis circuit, (60)
is a dispersal circuit that removes triangular waves, and (62) is an output amplifier.

(64) is an output processing block. (66> is an output terminal group. (66a) and (66b) are audio output terminals,
(66c) (66d) is an output terminal for DAT optical cable connector, (66e) is an output terminal for pit stream, (66f) is an output terminal for pay TV decoder, (66
g) is a video output terminal.

(68) is a synchronization separation circuit, and the vertical synchronization signal pulse (
VO) and outputs it to the microcomputer (32).

The above operation will be explained.

This BS tuner (16) operates a counter circuit (46) for a predetermined period and inputs this count data to the microcomputer (32). The microcomputer (32) learns the frequency deviation of the 21F signal by comparing this data with the reference data. And the microcomputer (32)
To correct this deviation, the frequency division ratio of the program divider of the PLL circuit (30) is varied.

This predetermined period of counting is determined by the microcomputer (32
) is determined from the vertical synchronization signal (Vo). This predetermined period (gate) is shown in FIG.

In Fig. 6, (a) is the output of the PLL type FM demodulation circuit (40), (b) is the output of the synchronous separation circuit (68), and (c) is the counter circuit (46) output from the microcomputer (32). The reset signal (C4, (d)) is a counter operation period designation signal (gate) of the counter circuit (46) output from the microcomputer (32).

The operation will be explained with reference to FIG.

Vertical synchronization signal pulse (Vo) from the synchronization separation circuit (68)
is input to the microcomputer (32), the microcomputer (32)
) outputs a reset signal (CJ). Then, during the vertical synchronization retrace period (1024 microseconds), a (A) gate signal is output to permit the counting operation of the counter circuit (46).

Then, after stopping the output of the gate signal (gate) for the period (B), the gate signal (C) is output again for 1024 μsec. And the microcomputer (32
) reads the count data of the counter circuit (46) in the subsequent period (D). In order to remove the influence of the triangular wave, which is an energy diffusion signal, a microcomputer (32)
Detects the "shift" in the frequency of the second IF signal by comparing the value obtained by adding up the four count results for two frame periods and dividing by 4 with the reference data value at the time of NTSC broadcast reception.
AFC operation is performed by varying the frequency division ratio of the PLL circuit (30).

The counter circuit (46) is operated during the video period because, in the case of NTSC broadcasting, average value AFC for transmission is adopted as the main carrier frequency control method. ) The value of period (B) is varied, for example, 6 msec, 4 msec, 6 msec, 8 msec for each field, and the frequency value of each part of the screen is detected to prevent fluctuations due to variations in brightness. are doing.

In this way, the microcomputer (32) controls the PLL circuit (30) to perform average value AFC every two frame periods. In addition, when controlling the PLL circuit (30) for each field, the AFC operation may be performed by averaging the past four count results and comparing this with reference data.

Also, in the above example, 4 fields (2 frames) period
The two count results were averaged, which is 4.6.8
It may be a frame period.

In addition, this BS tuner can also receive satellite broadcasting (generally called high-visit broadcasting) in which the MUSE signal (a high-definition TV signal developed by NHK is converted using 41-band technology) is FM modulated. In this case, the number of fields to average the count values in accordance with the period of the spread signal for the MUSE signal is switched from that of the NTSC system. Also, the period during which the counter circuit (46) is operated is naturally MUS.
In the case of E reception, switching is made to the clamp level period of the MUSE signal. Regarding the MUSE signal, please refer to the magazine "Nikkei Electronics 1987" published by Nikkei McGraw-Hill.
This is a well-known technology, as described in P2S5-P212 of the November 2 issue of NQ433J as ``Transmission system for high-definition broadcasting using satellite MUSE'' by Tasuku Ninomiya of the Japan Broadcasting Corporation.

However, as shown in FIG. 7, the clamp level period of the MUSE signal is different from the retrace period (1024
It is extremely short (23 μ seconds) compared to 15 to 17 μ seconds, and the period for operating the counter circuit is even shorter (15 to 17 μ seconds).
seconds), and it is impossible to accurately perform AFC operation by counting this period.

That is, when receiving MUSE broadcasting, the detection accuracy of the shift "shift" of the 21st F signal per count of the counter circuit is about 17 MH2, which is not enough to perform AFC operation.

Therefore, 1. 2nd I without using /256 frequency divider (44)
It is sufficient to directly count the F signal using the counter circuit (46). However, it is difficult to create a high-speed counter circuit that counts the second IF signal of 402.78 MHz using ECL. In other words, even with ECL, the frequency dividing circuit (44) L that simply divides the frequency as shown in FIG. 5 is difficult to put into practical use.

This is done by converting the second IF signal to 172 to 1 using the ECL frequency dividing circuit.
Even with a signal set to /4, it is difficult to count. Furthermore, if the frequency is divided more than this, the detection accuracy per count becomes too coarse, causing a practical problem.

This is because the frequency variation of the 21st F signal is also divided at the same time. In addition, if it is possible to count at 1/2, the detection accuracy per count at that time is about 130
At 1/4 KHz, it is approximately 260KH2.

Therefore, it is conceivable to perform normal key A and FC when receiving MUSE. An example of this is shown in FIG. (70)
is a MUSE decoder. This decoder (70) outputs a high-quality television signal, and also outputs a signal (keyed AF signal) indicating a clamp level signal period only when the MUSE signal is input.
C pulse signal) (P) is output.

(72) is a MUSE signal buffer, (72a) is an output terminal, (74) is a keyed A, FC pulse signal input terminal (high-definition broadcast compatible terminal), (76) is a sample hold circuit that samples the clamp level signal, (78) is an A/D converter that converts the value of the sample and hold circuit (76) into a digital value. Microcomputer (3
2) is this A/D conversion when receiving MUSE!
The value from (78) is compared with the reference data for MUSE reception to detect a "deviation", and the PLI circuit (30) is controlled to perform AFC operation.

However, as mentioned above, this kind of circuit samples and holds the analog signal, and is affected by temperature etc.
It was impossible to achieve the high precision and high response of the S tuner.

Therefore, by mixing the second IF signal and the oscillation signal from the highly stable oscillation circuit for down-conversion, converting the frequency, and counting this frequency-converted signal (temporarily referred to as 31F), the second IF signal It has been considered to detect the "shift" of

This conventional example will be explained with reference to FIGS. 9 and 10.

In FIG. 9, (80) is an AFC down converter circuit, which converts the 21st F signal of 402.78 MH, into 2
It is converted into a third IF signal of 4.78MH. (82) is an amplifier, (84) is a highly stable oscillation circuit that oscillates at 378M H, (86) is a mixing circuit, and (88) is 24.78M H.
H is a signal bandpass amplifier. (90) is 1
/16 frequency divider circuit. (SWI) is a changeover switch. This switch (SWI) is connected to the N side when receiving NTSC broadcasting.

(92) is a reception mode discrimination circuit, which determines whether it is receiving rNTSC broadcasting by using a synchronization signal and a keyed AFC pulse signal.
It determines whether it is rMUSE broadcast reception, or whether it is otherwise, and outputs it to the microcontroller (32).
) is switched to M fllU when receiving MUSE, and NTS
Switch to the receiving side when receiving C.

(94) has a counter control pulse generation time for NTSC reception, and a synchronization signal is input and the gate signal (g
ate), clear signal ((1), vertical synchronization signal (VD)
Output.

(96) creates counter control pulse creation times for MUSE reception, inputs key A, FC pulse (P), and generates second gate signal (gate2) and second clear (C12).
), and generates a counter data read control signal (V D2). The selection output circuit (98) selects these two pulse generation circuits (94) and (96) according to the reception mode.
The selected signals are output to the counter circuit (46) and the microcomputer (32).

(100) is an AFC prohibition circuit, which switches (SW) when receiving MUSE and when the AGC voltage is low (weak electric field).
2) to cut off the input of the read control signal (VD2) and prohibit AFC operation. This is because the reliability of the AFC operation decreases when receiving a weak electric field. Furthermore, N
When receiving TSC broadcasting, even if the second IF signal is slightly lost, the AFC will not malfunction significantly because the sampling time is long.

The above operation will be explained with reference to FIGS. 9, 10, and 6.

When the user selects a receiving channel, the microcontroller (32) sends standard frequency division ratio data for receiving that channel.
is output to the PLL circuit (30). Then, reception is performed for a while using this frequency division ratio data.

Thereafter, when the reception discrimination circuit (92) determines that the mode is NTSC reception mode based on the synchronization signal, the selection output circuit (98) sends a clear signal (C1) to the counter circuit (46).
) [C in Figure 6] and gate signal (gate) [D in Figure 6
] and sends a vertical synchronization signal (Vo) to the microcontroller (32).
Output. Also, the microcontroller (32) is also informed that the NTSC reception mode will be selected, and the microcontroller sets the AFC for NTSC.
Start operation. The switch (SWI) is connected to the N side.

In other words, the counter circuit (46) operates in the same manner as shown in FIG. Compare with current reference data. Then, the "deviation" of the 21st F signal is detected, and the frequency division ratio of the PLI circuit (30) is varied in the same manner as described above.
, performs FC operation.

Also, after tuning, the signal output from the terminal (72a) is input to the MUSE decoder (not shown), and this M'USE
If the decoder determines that it is a MUSE signal, this BS
A keyed AFC pulse signal (P) is input from the terminal (74) of the tuner (16). Then, the reception discrimination circuit (9
2), the MU is activated by this keyed AFC pulse signal (P).
It is determined that the mode is SE reception mode. Switch (SWl,
) is connected to the M side, and the microcontroller (32) is connected to the A side for MUSE.
Start FC operation.

The selection output circuit (98) receives the second gate signal (gat
e2) Second clear signal (Cj!2) control signal (V O2
) is output.

This signal is shown in FIG. Figure 10(a) shows MtJs
It shows a triangular wave that is valuable for E signals.

(b) is the keyed AFC output from the MUSE decoder
It shows a pulse signal. (C) is the second clear signal (C
P, 2) and (d) indicate the second gate signal (gate2). (e) shows the control signal (VD2).

As can be seen from FIG. 10, the keyed AFC pulse signal output period, which is the clamp level signal period, is exactly at the center potential of the triangular wave. Therefore, when receiving the MUSE signal, the count data value of the counter circuit (46) does not vary from field to field due to the influence of the triangular wave. Therefore, even with one count data, AFC operation can be performed theoretically without the influence of the triangular wave. However, in reality, there is a difference when superimposing this triangular wave and the MUSE signal, keys A and F
Due to the delay in detecting the C pulse signal, etc., it will still be at least 1
Two data samples sampled during a period (one frame) must be averaged.

In this conventional example, in order to improve reliability, the AFC operation is performed by comparing the average of four pieces of data for two frame periods with reference data for MUSE reception. Furthermore, among these four data, there are too many other data,
A safety measure is adopted in which the microcomputer (32) excludes count data that is far apart and averages it. Alternatively, count data that is too large and far from the reference data may be excluded, and the count data of the past four times may be averaged.

FIG. 11 shows another conventional example. This figure 11 shows a type in which a microcomputer (32) creates a clear signal (cF) and a gate signal (gate) at the time of NTSC reception, similar to the conventional example shown in figure 5.Also, the counter circuit at the time of NTSC reception ( 4
The count input to 6) is also a 1/256 frequency divided signal of the second IF signal.

When this microcomputer (32) receives a vertical synchronization signal (VO) from the synchronization separation circuit (68), it determines that it is receiving an NTSC broadcast, and performs an AFC operation for NTSC. or,
When keyed AFC pulse signal (P) is input, MUSE
It determines that it is broadcast reception time and performs AFC operation for MUSE. When neither signal is input, AFC
Stop operation.

That is, the frequency division ratio of the P L, I, circuit (30) is not changed, and the frequency division ratio is held at its previous value.

(93) is a circuit for determining when receiving MUSE broadcasting;
The switch (SW3) is opened during MUSE broadcasting to prevent vertical synchronization signal pulses (VD) from being input erroneously. Also, this discrimination circuit (93) always selects the switches (SW6) (SW7) (SWI) connected to the N side.
Switch to M side when broadcasting from MUSE.

(SW4) is a normally closed switch, (SWS) is a normally open switch, and (102) is a gate pulse generation circuit. This gate pulse generation circuit (102) outputs a delayed pulse signal (G) delayed by approximately 1760 seconds as shown in FIG. 12(c) every time the keyed AFC pulse signal (P) shown in FIG. 12(b) is input. do. Then, during the period (G) in FIG. 12(c),
The normally closed switch (SW4) is opened. Also, Figure 12 (
During period (G) of c), the normally open switch (SWS) is closed. In other words, this switch (SW 4 ) (
A regular keyed AFC pulse signal (P) input at an interval of 60 Hz passes through S W 5 ), and noisy pulses are removed.

(97) is the creation of a counter control signal for MUSE that creates a second clear signal (C 2) and a second gate signal (gate2). If the counter operation period of the counter circuit (46) is not set accurately, it may cause malfunction of the AFC operation, so in this embodiment, the IOMHz oscillation circuit (1
04) sets the second gate signal (ga, te2) period.

(104) is an IOMHz oscillation circuit, as shown in Fig. 13 (
b) Outputs the clock signal. (106) is a key pulse synchronization circuit. This key pulse synchronization circuit (106)
outputs the second clear signal (Cffi2) in FIG. 13(C) at the timing when the clock signal is input after the keyed AFC pulse signal (P) in FIG. 13(a) is input. , (108) is this second clear signal ((,12
) is a counter that is cleared by (110) is a gate signal generation circuit, which is set by the second Knorr signal (C12) to generate the second gate signal (
Open gate2).

The gate signal generation circuit (110) outputs the signal (k) shown in FIG. 13(e) that allows the operation of the counter (108).

Therefore, the counter (108) starts counting the clock signals. The counter (108) receives the clock signal by 16
When counting 0, the reset signal (R
) is output. This reset signal (R) causes the gate signal generation circuit (110) to generate the second gate signal (gate signal).
2) Bring down. In addition, a gate signal generation circuit (110
) is the counter (108) with the signal (k) at low level.
Prohibits the operation of

(85) is a highly stable oscillation circuit for controlling the third IF signal. (112) is a 378 MHz oscillation circuit, (114
) is a PLL circuit with a built-in ECL pnoscaler equipped with a 4MHz crystal (accuracy 10-''), and its frequency division ratio is fixed.In this way, in the past, a PLL loop was formed to generate an oscillation circuit. (112) to suppress its oscillation frequency fluctuation to within ±37.8 KHz.

Note that this BS tuner may also take measures against weak electric field reception of MUSE broadcasts. For example, as in the previous example, the AFC operation may be stopped by detecting the weak electric field reception using the AGC signal. Further, as the electric field becomes weaker, the averaging period may be set to be longer (for example, 8 frame periods). Alternatively, the lamp may be turned on during the input period of the keyed AFC pulse signal to notify that the MUSE broadcast reception mode is in effect. Also, the synchronization signal or the PC in Fig. 5
The terminal (50a) output of the M decoder (50) may be used to light a lamp to notify that NTSC broadcasting is being received.

Alternatively, a MUSE decoder may be incorporated.

Also, tJ FN F, VHF% TV for CATV reception.
A tuner may also be built in. At this time, the oscillation frequencies of the oscillation circuits (84) and (112) are set to a frequency between the channels so as not to overlap with the channel transmission band of the TV.

FIG. 14 shows another conventional example. Note that the same parts as in FIG. 11 are given the same reference numerals, and redundant explanation will be omitted. In FIG. 14, (130) is a gate array IC. In other words, in this conventional example, the circuit is integrated. This gate array (130) detects the presence or absence of the 31st F, and stops the AFC operation (holds the previous value) when the 31st F is absent.

In other words, if the received signal is lost for a short period of time or the down converter (80) fails, the AFC will malfunction, so this gate array IC (130) has adopted a safety measure to stop this AFC operation. There is.

In FIG. 14, (93') is a MUSE broadcast receiving/broadcast receiver discrimination circuit, which notifies the channel selection microcomputer (32') that it is the receiving side when receiving MUSE. Also, this discrimination circuit (93'
) switches the switch (SW3').

In other words, the switch (SW3') normally connected to the N side is switched to the receiving side when receiving MUSE, and the keyed AFC pulse (pseudo second gate signal) (gate2') shaped by the counter control signal generation circuit (97) is generated. Input to the channel selection microcomputer (32').

The channel selection microcomputer (32') determines whether the receiving side is receiving NTSC or MUSE based on a signal from the discriminating circuit (93'), and executes a program for that mode. Then, the timing is set by the fall of the vertical synchronizing signal from the switch (SW3') or the pseudo second gate signal (gaLe2'), and the data of the counter circuit (46) is taken in.

(1, 20) is a D flip-flop showing the characteristics of this conventional example. A third IF signal is supplied to the clock terminal (CK) of this D flip-flop (120). That is, this D flip-flop (120) outputs a pseudo second gate signal (gate2') obtained by delaying the second gate signal (gate2) in FIG. 11 by the period of the 31F signal. If the third IF signal disappears, this D flip-flop (120) holds the value (usually O) before the third IF signal disappears. For this reason, the channel selection microcomputer (32'
) is not given the pseudo second gate signal "+(gate2'), the channel selection microcomputer (32') does not take in data, and the AFC operation substantially stops.

That is, in FIG. 14, the second gate signal (gate2) created in the same manner as in FIG.
120) to the D terminal. The third IF signal is a normal output (pseudo second The gate signal (gate2') disappears. Since the falling edge of this pseudo second gate signal (gate2') is used as a pulse for data reading timing in the tuning microcomputer (32'), the tuning microcomputer (32') is used as a pulse for data reading timing. stop.

Therefore, the value of the PLL circuit (30) due to the AFC operation at the time when the 31st F signal disappears is held.

As mentioned above, in the conventional example shown in Fig. 14, when the third IF signal disappears, the supply of the pseudo second gate signal (ga Le2') to the tuning microcomputer (32°) is stopped, and the AFC operation is stopped. There is.

In the above conventional example, the D flip-flop (120) was provided between the gate signal generation circuit (110) and the switch (SW7), but this It may be provided in between.

Moreover, in this conventional example, the D flip-flop (120) 1
This prevents malfunction when the 31st F signal is missing, but this also includes a 3rd IF signal missing state detection circuit and the output of this detection circuit to stop the AFC operation when the channel selection microcomputer (32') receives MUSE. It is also possible to install a separate stop circuit for the NTSC reception.However, by doing so, the reliability will be improved.Also, it can be applied to the circuit shown in Fig. 1, and the NTSC Stop AFC operation (previous value hold)
You may do so.

In the above conventional example, the frequency of the 31st F signal output from the AFC down converter circuit (80) has an adverse effect on the normal VHF, UHF, and CATV tuners built into this BS tuner or placed nearby. For example, it is set as shown in FIG.

TV for receiving regular Japanese television broadcasting (terrestrial broadcasting)
, the frequency of the audio intermediate frequency signal SIF is 54
．． 25MHz H7, and the frequency of the video intermediate frequency signal VIF is set to 58.75MHz. The frequency of the 31st F signal (IF) output from the A, FC down converter circuit (80) of the BS tuner is 24.78M.
When set to H, the second harmonic of the third IF signal (
The frequency of IF2) is 49.56MH, roaring. In this way, the frequency of the third IF signal is set so that the frequency of the second harmonic of the 31st F signal does not overlap with the frequency of the audio intermediate frequency signal and the frequency of the video intermediate frequency signal. In addition, the frequency of the third harmonic (IF3) of the third IF signal is set so that the frequency of the third harmonic (IF3) of the third IF signal does not overlap with the frequency of the audio intermediate frequency signal (S
The frequency of the 1F signal is set.

Further, the oscillation frequency of the oscillation circuits (84) and (112) included in the AFC down converter circuit (8o) is the first
As shown in Figure 6, in Japanese television broadcasting, there is an empty area (SR) between the VHF band and the UHF band.
)do. Therefore, the frequency of the oscillation signal (OSC) output from the oscillation circuits (84) and (112) is 222M
Set between H2 and 470M H2.

In this case, the oscillation signal (OSC) should be Frequency is set. For example, if the frequency of the oscillation signal (OSC) is 37
When set to 8MH, the second harmonic command (O5C2)
The frequency is exactly between the frequency of the video carrier (fp) and the frequency of the audio carrier (fs) of the 60 channels.

If V HF 41 and U E
(When a channel is assigned to the free area between Fl and In Fig. 7, the frequency of the oscillation signal is set so as not to overlap with the frequency of the audio carrier (fs), which is 377.75 MHz, and the frequency of the video carrier (fp), which is 379.25 MHz. The frequency is set at 3781vfFLz, which is between two channels. Also, 378MH is the frequency at the boundary between channels.

As described above, according to the conventional example, the second IF signal is converted into the third IF signal by the frequency mixing method. Therefore, the variation of the second fF signal is not frequency divided. Therefore, the frequency fluctuation of the second IF signal can be detected with high accuracy, and highly accurate AFC operation is possible.

(c) Problems to be Solved by the Invention As described above, in order to receive high-definition broadcasting with a BS tuner, a down converter (80) for down converting the second intermediate frequency signal is required, which increases costs. Furthermore, it is difficult to select the oscillation frequency (OSC) and third intermediate frequency (IF3) of this down converter (80).

(d) Means for Solving the Problems The present invention includes a counter circuit (46) that frequency-divides the second intermediate frequency signal and counts the frequency-divided output for a predetermined period of time;
A control circuit (32) which controls the operation timing of this counter circuit (46) and performs AFC operation by inputting the count result, and a control circuit (32) which determines whether or not the receiving state is when receiving a MUSE signal and controls the MUSE determination signal as described above. A MUSE discrimination circuit outputs to the circuit (32), a keyed AFC pulse (P) is input to the control circuit (32) when the MUSE discrimination signal is input, and a vertical synchronization signal pulse (VO) is controlled by the control circuit when the MUSE discrimination signal is not input. and a switch circuit (122) that inputs to the circuit (32), and the control circuit (32) controls the counter circuit ( The counter circuit (40) is opened during the predetermined time of the vertical retrace period and the count result is input, and when the MUSE signal is not input, the counter circuit (40) is opened during the predetermined time of the video period. The PLL circuit (30
).

The present invention also provides a counter circuit (46) that frequency-divides the second intermediate frequency signal and counts the frequency-divided output, and controls the operation timing of this counter circuit (46) and inputs the count result to perform AFC. Control circuit (12
2) (32) and the reception status is MUSE signal reception signal reception -
is determined and the MUSE determination signal is sent to the control circuit (32) (
122) and a control circuit (3
2) and a manually operated switch circuit (122), the control circuit (32) (1, 22) is timing-controlled by the MUSE signal reception signal reception-do AFC pulse (P).
During the vertical blanking period during which the value audio signal is interpolated, the counter circuit (46) is operated to detect the frequency of the second intermediate frequency signal to perform an AFC operation, and
When receiving the TSC signal, the counter circuit (46) is operated at least during the vertical retrace period under timing control by the vertical synchronizing signal pulse (VD) to detect the frequency of the second intermediate frequency signal and perform the AFC operation. It is characterized by

(E) Function The present invention detects the frequency of the second intermediate frequency signal by counting the frequency division signal of the second intermediate frequency signal in the audio signal period with small movement in the case of high-definition broadcasting. and performs AFC operation.

This is because the level of the audio signal period becomes an intermediate level when averaged.

In other words, during the video period, the image at that time is a bright screen or a dark screen, and its level fluctuates greatly. Therefore, the frequency of the second intermediate frequency signal, which is a signal obtained by FM modulating this signal, also varies greatly depending on the brightness and darkness of the screen.

In contrast, the audio signal period is close to the mid-level (128/256) when averaged.

This means that the audio signal is at an intermediate level (as shown in Figure 3).
1, 28/256), and the values of its positive peak (2) and negative peak (0) are smaller than that of the video signal.

Also, quasi-instantaneous companding differential encoding is used to encode the audio signal for data compression, but the basic encoding is 2
The complement of 2°S is used. This 2
As shown in Fig. 4, for example, as shown in Figure 4, even if the fluctuation of the input signal is small, if the signal is symmetrical in positive and negative, the probability of occurrence of "o" and "1" will not be biased to one side. do not have.

If the frequencies of the audio signal period are detected and averaged in this way, the level becomes approximately an intermediate level, and an average second intermediate frequency can be detected regardless of the content of the audio.

(F) Embodiment FIG. 1 shows an embodiment of the present invention. In the drawings, the same parts as in the conventional example are given the same reference numerals.

In FIG. 1, (1, 20) is a determination circuit for MUSE reception. This discrimination circuit (120) consists of a retriggerable monomulti. This discrimination circuit (120) continues to output the MUSE discrimination signal as long as the keyed AFC pulse (P) continues to be input at a 60 Hz cycle.

(122) is a switch circuit, which switches when the MUSE discrimination signal is input and vertical synchronization signal pulse (VD
) instead of keyed AFC pulse (P) by microcomputer (3
2) Enter.

The buffer circuit (124) (126) is an output inversion circuit.

The above circuit operates in the same manner as the conventional example shown in FIG. 5 during normal reception.

Furthermore, when receiving a MUSE broadcast (high-definition broadcast), a keyed AFC pulse (P) is input from the MUSE decoder (70) to the ES tuner (16). This keyed AFC pulse (P) is input to a retriggerable monomulti (1, 20) via a buffer circuit (1, 24). This drives the monomulti (120) and outputs the MUSE discrimination signal. Thereby, the switch (122) is connected from the synchronous separation circuit (68) side to the edge reversing circuit (126) side. As a result, the keyed AFC pulse (P) is input to the microcomputer (32). From the time of keyed AFC pulse input, the microcontroller (32)
It operates for a period of 1024 μs, the same as when receiving normal broadcasting.
The counter circuit (46) is operated and the 21st intermediate frequency signal 1. /256 division frequency is counted. This count period corresponds to the shaded area in FIG. Further, in normal broadcasting, the video signal period (C) is also counted as shown in FIG. 6d, but this is not done when the MUSE signal is received.

In other words, when the MUSE discrimination signal is not input, the channel selection microcomputer (32) counts for 1024 microseconds when there is a pulse input from the switch circuit (122), and for a predetermined period from this count (see Fig. 6). The count of C) in d is 1
Perform for 024 microseconds. These are then averaged.

Also, when inputting the MUSE discrimination signal, the switch circuit (1,
22), it counts for 1024 microseconds. And these are averaged.

In this embodiment, the MUSE was determined based on the presence of the input of the keyed A l''C pulse (P);
You may also make a determination. Alternatively, both may be used.

(G) Effects of the Invention As described above, according to the present invention, a 3S tuner compatible with high-definition broadcasting can be realized without using a down converter. Therefore, cost reduction can be achieved by eliminating the down converter. Furthermore, by eliminating the down converter, it becomes unnecessary to select the oscillation frequency and the third intermediate frequency.

[Brief explanation of drawings]

1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a count period. 3 and 4 are diagrams for explaining the present invention in detail. FIG. 5 is a diagram showing a first conventional example, and FIG. 6 is a waveform diagram thereof. FIG. 7 is a diagram showing signal assignment of the MLJSE signal. Figure 8 shows the second conventional example, which is a high-definition compatible BS.
It is a diagram of a tuner. FIG. 9 is a diagram showing a third conventional example, and FIG. 10 is an operation waveform diagram thereof. FIG. 11 is a diagram showing a fourth conventional example, and FIGS. 12, 13 are operational waveform diagrams thereof. FIG. 14 is a diagram showing a fifth conventional example. FIG. 15, FIG. 16, and FIG. 17 are diagrams for explaining frequency selection by the down converter. (32)...Microcomputer (control circuit), (46)...
Counter circuit, (34>...FM demodulation block, (122)...Switch circuit (control circuit), (P)
... Keyed AFC pulse, (Vn) ... Vertical synchronization signal pulse, (68) ... Synchronization separation circuit, (]6) ... BS tuner.

Claims (2)

[Claims] (1) A counter circuit (46) that frequency-divides the second intermediate frequency signal and counts the frequency-divided output for a predetermined period of time; and a counter circuit (46) that controls the operation timing of this counter circuit (46) and inputs the count result. A control circuit (32) that performs AFC operation, and a control circuit (32) that determines whether the receiving state is when receiving a MUSE signal and transmits the MUSE signal.
MUSE that outputs the E discrimination signal to the control circuit (32)
a discrimination circuit; a keyed AFC pulse (P) is input to the control circuit (32) when the MUSE discrimination signal is input, and a vertical synchronization signal pulse (V_D) is input to the control circuit (32) when the MUSE discrimination signal is not input;
32), and the control circuit (32) vertically controls the counter circuit (40) by the pulse signal from the switch circuit (122) regardless of input/non-input of the MUSE signal. Operate during the predetermined time of the retrace period and input the count result, and
When the MUSE signal is not input, the counter circuit (40) is operated during the predetermined time period of the video period to input the count results, and these count results are averaged to detect the shift in the second intermediate frequency. A high-definition compatible BS tuner, characterized in that it controls a PLL circuit (30). (2) A counter circuit (46) that frequency-divides the second intermediate frequency signal and counts the frequency-divided output, and controls the operation timing of this counter circuit (46) and inputs the count result to perform AFC operation. Control circuit (32) (12
2), and determines whether the receiving state is when receiving a MUSE signal and sends the MUSE signal.
and a MUSE discrimination circuit that outputs an E discrimination signal to the control circuit (32) (122), and the control circuit (32) (122) is timing-controlled by the keyed AFC pulse (P) when receiving the MUSE signal. During the vertical retrace period during which the value audio signal is interpolated, the counter circuit (46) is operated to detect the frequency of the second intermediate frequency signal and perform an AFC operation;
Vertical synchronization signal pulse (V_D) when receiving NTSC signal
At least during the vertical retrace period, the timing is controlled to
A BS tuner compatible with high-definition broadcasting that operates the counter circuit (46) to detect the frequency of the second intermediate frequency signal and performs an AFC operation.