JPH0368033A - Program execution control system - Google Patents

Abstract

PURPOSE:To disuse privileged instruction simulation that had been practiced at a virtual computer system by removing the interference mutually between OSs (operating systems) to be parallelly executed, or mutually between APs to be run on the OS. CONSTITUTION:This system, basically, is equipped with a CPU 1, and a memory 4 housed through an address bus 3 and a data bus 2, to this CPU 1, and also consists of an OS selection changeover circuit 8, a peripheral processing requirement notification circuit 7, an interruption control circuit 6, and peripheral equipments 14, 15. The interruption control circuit 6 converts an OS selection changeover interruption signal 9 from the OS selection changeover circuit 8 and processing requirement signals 12, 13 from the peripheral equipment into vector numbers, and notifies them to the CPU 1 as interruption signals 5. Also, based on an OS selection classification signal 16 from the OS selection changeover circuit 8, the peripheral processing requirement notification circuit 7 outputs only the requirement corresponding to the actually selected peripheral equipment.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a program execution control method for executing multiple operating systems in parallel on an information processing system, and in particular, it is easy to increase the number of operating systems. The present invention relates to a program execution control method that can cope with the above problems and greatly improve the degree of reuse of application programs.

[Conventional technology] In general, a program has a large operating system (
These programs are broadly divided into O8 (hereinafter simply referred to as O8) and application programs (hereinafter simply referred to as AP), but in recent years, with the progress of computerization in various fields and the development of microcomputers, programs have been developed to control them. The reality is that the number of programs, especially APs, has already reached a huge amount. However, since these APs are generally designed and developed under the condition that they run on a specific O8, there are already APs with the required functions, and they are executed on the same processing device. Even if there is, if the O8 of the diverted AP is different from the existing O8, there are many cases where it cannot be executed as is. Therefore, in order to run on the target O8,
P may be ported, but this porting requires not only changes to O3 itself, but also testing and subsequent maintenance;
Even when it comes to porting or appropriating P, it is necessary to go through many processes.

As mentioned above, it is desired that the AP can be used as is, but generally speaking, the O8 of the diverted AP is
There are two possible methods: one is to bring in multiple O8s at the same time and run them on the same processing device, and the other is to make changes to the O8 side so that multiple OS interfaces can be provided at the same time.

The former includes a virtual computer system, and the latter includes changes to the existing O8 itself and newly added O8 to the existing O8.
It is being considered to provide a simulation program between the AP and the existing O3 for simulating under the following conditions.

However, when using the latter, it is necessary to change the existing O8 or add a simulation program every time a new OS support is required, and when using a simulation program, simulation overhead becomes a problem.

On the other hand, in the case of the former virtual computer system, it is possible to execute multiple O8s in parallel, for example in the ROSW theory.
(Kyoritsu Shuppan, published November 10, 1988, page 202
-205), is conventionally known. In this case, multiple virtual processing devices (hereinafter referred to as V
VM), and programs such as O8, which originally run occupying a processing unit, can be executed in parallel on each VM.

[Problem to be solved by the invention] Conventional virtual computer systems have emphasized independence between VMs, and even if an abnormality occurs in a program such as O8 on one VM, programs on other VMs or virtual The configuration is such that no adverse effects are spread to the computer system itself. Therefore, privileged instructions that change the state of the processing unit, such as changing control registers issued by a program on the VM, are not directly executed by the processing unit, and the virtual machine system control program cannot change the state of the virtual processing unit of the VM. It is simulated by Since the privileged instructions are simulated in the program as described above, there is a problem in that the overhead is large. To explain in more detail, in a virtual computer system in which multiple O8s are executed in parallel in a time-sharing manner, O8 instructions are directly executed by the CPU in order to improve execution speed, and therefore the registers of the CPU during O8 execution are is set to the value used by O8. However, if the values used by O8 are set to registers that control interrupt masks or storage (control registers), etc., it becomes impossible to control the virtual computer system itself, so these The control registers are simulated by a virtual computer system program.

On the other hand, privileged instructions are instructions for setting or changing the values of these control registers, so privileged instructions are directly executed by the CPU.
Instead of being executed by the virtual computer system, the program is simulated by the virtual computer system program, resulting in overhead.

In order to solve the above problems, methods have been adopted to reduce overhead by performing simulation using hardware and firmware, but in order to realize this method, special functions for virtual computer systems are required in the processing device. It has become so.

In addition to this, it not only causes an increase in hardware prices, but also
When using a general-purpose microprocessor, it is difficult to manually design a processor with such functions. Apart from the above, at present, virtual computer systems only exist as part of general-purpose computer systems, and in order to realize this with a general-purpose microprocessor, the user must create a virtual computer system control program. It was necessary to create a .

An object of the present invention is to provide a program execution control method that can easily cope with an increase in the number of O8s when executing a plurality of O8s in parallel on an information processing system, and can greatly improve the degree of AP utilization. be. Another object of the present invention is to provide a program execution control method in which some of the required functions are realized by a program when the control method is executed, and furthermore, when O8 selection is switched, an interrupt from a peripheral device is generated. A program execution control method that does not malfunction in some cases, and a program execution control method in which the selected time pre-assigned to the O8 can be changed by instructions from the O8 depending on whether or not there is processing in progress. It is to serve.

[Means for solving the problem] The above purpose is to solve the problem by
In order to time-divisionally and cyclically execute 8-compatible APs, each time each O8 is selected in sequence, the O8 selection switching means provided outside the CPU selects the selected time previously allocated to that O8. During this period, the type of O8 is displayed to the outside, and when the type display starts, the O8 is displayed on the CPU.
When a switching interrupt occurs, the information save/recovery means temporarily saves and saves information related to the previously selected O3 in the memory until the next execution is resumed. , processing requests as interrupts to the CPU from each peripheral device are mask-controlled by the peripheral processing request notification means based on the O8 type display, unless the O8 assigned in advance to that device is currently selected. This is achieved by In addition, another purpose is to function as an information evacuation storage/recovery means by executing a program stored in advance in memory;
When an 8 switching interrupt occurs, all interrupts from each peripheral device are handled by the CPU until the information necessary for resuming execution of the currently selected O8 is recovered by the information save/recovery means. Another purpose of masking is to prevent the O8 selection switching means from receiving an instruction to change the selected time assigned to the O8 from the currently selected and executed O3 before the end of the selected time. In this case, the selection time is shortened or extended as instructed.

[Operation] The point is to eliminate interference between O8s running in parallel or between APs running on O3, that is, to degenerate the independence of VMs guaranteed in conventional virtual machine systems. As a result, the privileged instruction simulation that had been performed in previous virtual computer systems was abolished. This elimination of privileged instruction simulation makes it possible to simplify the control mechanism and reduce overhead. Now, in order for the O8 stored in advance in the memory and the AP compatible with this O8 to be executed as a pair in a time-sharing and cyclical manner,
The O8 selection switching means is configured to sequentially select O8s at selected time intervals that are previously assigned to each O8. As a result, O8 is apparently executed in parallel. Each time O8 is selected from the O8 selection means, the type of O3 is displayed externally, and when this type display starts, an O8 switching interrupt is made to the CPU. When this interrupt occurs, as a pre-processing for O8 execution, a program is executed as a means of saving and restoring information, so that the information necessary for restarting the next execution regarding the previously executed O8 is acquired. At the same time, the saved information related to the currently selected O8 that is required to resume execution is restored, but during this time all interrupts from peripheral devices are masked to avoid malfunctions. It has become. Only after the saved information regarding the currently selected O8 is recovered can that O8 and its corresponding AP become executable.

Therefore, saving and restoring information guarantees normal execution in each O8 when a plurality of O8s are executed.

By the way, processing requests from peripheral devices are generated regardless of O8 selection switching, but the peripheral processing request notification means masks processing requests other than those from peripheral devices assigned to the currently selected O8. It looks like this. This is because, if it were not masked, the execution control of multiple O8s would be disrupted, such as the execution of the currently selected O8 being interrupted or the O8 processing the processing request running. In addition, although the selection time pre-allocated to each O8 is said to be semi-fixed, processing efficiency can be improved by shortening or extending the time depending on whether there is processing in progress. It turns out.

[Example] The present invention will be explained below with reference to FIGS. 1 to 10.

First, an information processing system according to the present invention will be described. FIG. 1 shows an example of the system configuration. In this example, a system with memory map I10 architecture is assumed, and for example, two O8#
1. #2 is run in parallel. As shown in the figure, the information system basically includes a CPU 1 and a memory 4 accommodated therein via an address bus 3 and a data bus 2, and further includes an O8 selection switching circuit 8 and a peripheral processing request notification circuit 7. , interrupt control circuit 6, peripheral device 1
4. '15 is placed in a predetermined position. O8
The functions of the selection switching circuit 8 and the peripheral processing request notification circuit 7 have already been outlined, but the interrupt control circuit 6 receives the O8 selection switching interrupt signal 9 from the O8 selection switching circuit 8 and the peripheral devices 14 and 15 respectively. The processing request (interrupt) signals 12 and 13 are converted into a vector number and then notified to the CPUI as an interrupt signal 5. Also, O3
Based on the O8 selection type signal 16 from the selection switching circuit 8, the peripheral processing request notification circuit 7 selects the peripheral assigned to the currently selected O8 from among the processing request signals 10.11 from each of the peripheral devices 14.15. Only signals from the device are output as processing request (interrupt) signals 12.13, but signals from other peripheral devices are placed in an output standby state until another O8 is selected. ing.

In the end, O3#1. #2 are assigned to peripheral devices 14 and 15, respectively.

In addition, in this example, the information backup/storage/recovery method in the description is the CPU.
This is realized as a program on memory 4 executed on I, which will be described later.

Now, the memory 4 stores various data tables and programs, and FIG. 2 shows a memory map of one example thereof. In this case, a vector (jump) table area 4-1 indicating interrupt logic, an information save/recovery program area 4-2, and a memory map I
10 area (for communication with OS selection switching circuit 8) 4-3,
Memory map I10 area (for input/output control with peripheral devices 14 and 15) 4-4, O8# and its AP area 4-5
, O8#2 and its AP area 4-6 are stored or set. Of these, area 4-
3 consists of the currently selected O8 type setting area 4-3-1 and other areas 4-3-2. Area 4-3-1 in particular is accessed by the information save/recovery program, The currently selected O8 type can be known.

In addition, Figure 3 shows the information backup/save/recovery program area 4.
-2 shows the flow of the program stored in the area, and specific areas 4-2-8 to 4-4 within that area.
2-10 is also adapted to function as an information-time storage. In this program, the O8 selection switching interrupt is
When in the PUI, register information, etc. related to the immediately selected O8 is saved and saved until the next execution resumes, and register information, etc. related to the newly selected O81, that is, the currently selected O8, that was saved until then is saved. This will be described in detail later.

FIG. 4 also shows the contents of the vector table. As shown in the figure, unique vector numbers are prepared for each interrupt factor, such as interrupt control circuit 6, O8#1. Every time there is an interrupt from #2, the vector number included in the interrupt is analyzed by the CPU, and it is determined based on the analysis result whether or not the interrupt can be masked.

Except for those from peripheral devices 14 and 15, which are maskable, all other interrupts cannot be masked, and if there is an interrupt that cannot be masked, processing will be performed according to that interrupt. This is what has become.

FIG. 5 also shows a specific configuration of an example of the O8 selection switching circuit 8. According to this case, O8#1. #2
A selected time setter 8-2, 8-3 is provided corresponding to each of the selected time setters 8-2.
After counting the time corresponding to one of the selected times from 8-3 based on the clock, it is reset, and after that, the operation is repeated such that the time corresponding to the other selected time is counted and then reset. It has become. The fact that the output of the counter 8-1 has reached each of the selected times is detected by the comparator 8-5, which compares the selected time with the output of the counter 8-1. This is output as the switching interrupt signal 9. At the same time, depending on the detection output, the count value at the counter (binary counter in this example) 8-7 serving as the currently selected O8 display circuit is incremented via the update circuit 8-6, and the count value is the O8 selection type signal. It is outputted to the outside as a selection control signal 16, and also controls the selection output of the selected time from the selector 8-4 as a selection control signal. The O8 selection type signal 16 indicates the type of O8 currently selected, but this type can be easily known by the CPU accessing the area 4-3-1 described above when an O8 selection switching interrupt occurs. It has become a thing. When accessing the area 4-3-1, an access address exists on the address bus 3, but this address is not connected to the interface circuit 8-
8, the O8 selection type signal 16 from the counter is output onto the data bus 2 via the interface circuit 8-8, so that the CPU 1 detects the currently selected O8 type. can be known.

Now, a general explanation of the above operation is as follows.

That is, assuming that O3#1 is currently selected, the counter 8-7 outputs the O8 selection type signal 16 to that effect.
is outputted, and the selected time is given from the setter 8-2 to the comparator 8-5 via the selector 8-4, and is compared with the count value from the counter 8-1. . When the count value eventually reaches the selected time, the O8 selection switching interrupt signal 9 is output from the comparator 8-5. This signal 9 also acts as a reset signal for the counter 8-1 and increments the counter 8-7. That is, at the time when the O8 selection switching interrupt signal 9 is obtained, the previously selected O8#1 is switched to O8#2. By this switching, the counter 8-
1 starts the once-reset profit counting operation, and the count value is compared with the selected time from the setter 8-3 by the comparator 8-5. While this comparison is being performed, the O8 selection switching interrupt signal 9 from the comparator 8-5 is determined by the interrupt control circuit 6 to be an O8 selection switching interrupt, and is converted into a vector number m. There is. When an interrupt occurs, the CPU sends an interrupt signal 5.
The vector number m as the interrupt type factor is notified to the CPU I via the data bus 2.

On the other hand, in the CPUI, the vector number is immediately accepted as a non-maskable one, and the above-mentioned information evacuation preservation/recovery program is activated. When this program is started, all interrupts from the peripheral devices 14.15 are first masked in step 4-2-1 in order to prevent malfunctions caused by interrupts from the peripheral devices 14.15.

This is because, at this point, the type of the newly selected O8 (currently selected O8 type) and the immediately previous selected O8 type are generally unknown. After this, register information in the CPUI is temporarily stored in area 4-2 by process 4-2-2.
-8, and the most recently selected O8 type is further extracted from area 4-2-10 by process 4-2-3. Through this extraction, it is known that the previous O8 type is O3#1, and the information in area 4-2-8 is determined to be related to O8#1, and in process 4-2-4, area 4-2-
It is transferred and saved in the part corresponding to O8#1 in 9. Furthermore, after this, area 4-3-1 is accessed in process 4-2-5, and the currently selected O8 type is read out from O8 selection switching circuit 8, and the type is identified as O8 #2. After that, the type is saved and set in area 4-2-10 by process 4-2-6.

Depending on process 4-2-7, O3 from area 4-2-9
Register information and the like that had been saved up to that point related to #2 are restored in the CPUI, and only then can O8 #2 become executable. While O8#2 and its AP are being executed in this way, the count value from counter 8-1 reaches the selected time from setter 8-2, and O8 selection is switched by comparator 8-5. When the interrupt signal 9 is obtained, the previous selection O3 and the current selection O8 are assumed to be ○S#2 and #1, respectively, and the same operation as in the above case is performed.

Next, assuming that the currently selected O8 type is O3#2, the interrupt operation from the peripheral device 14.15 will be explained.
Based on the O8 selection type signal 16 notified from the selection switching circuit 8, the peripheral processing request notification circuit 7 always knows the currently selected O8 type, and based on this, the processing request signal 10.11 from the peripheral device 14.15 is set to O8. It is designed to be masked by the selection type signal 16. That is, O3#2
If there is a processing request signal 11 from the peripheral device 15 while the is selected, this is sent to the peripheral processing request notification circuit 7
This is notified to the interrupt control circuit 6 as a processing request signal 13, and the interrupt control circuit 6 converts it into a vector number I and notifies the CPUI of the occurrence of an interrupt using the interrupt signal 5. This is notified to the CPUI via the data bus 2. C.P.U.I.
Just because a notice is received does not necessarily mean that it will be accepted immediately. Depending on the notification timing,
The interrupt is masked until O3#2 becomes executable. On the other hand, if there is a processing request signal 10 from the peripheral device 14 while O8 #2 is selected, the peripheral device 14 is assigned to O8 #1, so the peripheral processing request notification circuit 7 The processing request signal 10 is masked until O8#1 is selected. If O8#1 is selected, the CPU is notified that an interrupt has occurred from the peripheral device 14, as in the previous case.

The operation has been explained in general above, but as can be seen from the above explanation, in the case of the information processing system according to the present invention, only a small amount of hardware circuits 2.3 are added in terms of hardware. Since some of the hardware circuits are implemented as programs, the hardware configuration is simplified and multiple O3s can be easily executed in parallel.

Figure 6 shows the system call T that requests service from O8.
In cases where duplicate RAP numbers are used,
1 shows a configuration example of an information processing system according to the present invention. In such a case, since the memory for storing the vector table is provided for O8, an O8 selection type signal is required in addition to the memory address to determine the address when accessing the vector table. As shown in the figure, the memory equivalent to memory 4 in this example is O8#1. It consists of a vector table memory 4-1-1.4-1-2 corresponding to #2 and a memory 18 obtained by removing those vector tables from the memory 4, and these memories 4-1-1.4-1-2゜18
are provided between the address bus 3 and data bus 2, but the memory 4. For -1-1.4-1-2, a selector for read data selection or a demultiplexer for allocating read addresses is provided. This example shows a case where a demultiplexer 17 is provided, and the allocation of memory addresses from the address bus 3 is controlled by the O8 selection type signal 16 from the O8 selection switching circuit 8.

Now, finally, to explain how to change the selection time that is pre-allocated for O8, Figure 7 shows the memory map I10 area (for communication with the OS selection switching circuit 8) 4-3 in that case. It is something.

As shown, a communication area 4-3-3 has been newly added to the one shown in FIG. 2 to further shorten the selection time, and FIG. 8 also shows the O8 selection switching circuit accordingly. 8 shows the circuit portions added in 8. For example, suppose that O3#1 is selected and communication area 4-3-3 is accessed by O8#1 in order to forcibly end the selected time before the original end. For example, in the interface circuit 8-9, the access address on the address bus 3 is detected by its address decoding function. Communication area 4-3-
When an access to O8 is detected, this is determined to be an early end to the non-selection time, and the comparator 8-5 forcibly generates an O8 selection switching interrupt signal 9. .

Specifically, the access detection output is ORed with the output of the comparator 8-5 by an OR gate, and the output is
8 selection switching interrupt signal 9 is generated.

Therefore, when communication area 4-3-3 is accessed, the non-selection time in O8#1 is shortened, and O3#
Switching to 2 can be accelerated. The same holds true when the communication area 4-3-3 is accessed while OS #'2 is selected.

Next, to explain the case where the non-selection time is extended, FIG. 9 shows the memory map I10 area (O
3 (for communication with the selection switching circuit 8) 4-3. Communication area 4-3-4, 4-3-5 is newly added to the one shown in Fig. 2 to further extend the selection time, and Fig. 10 also shows O8 selection switching accordingly. This shows a circuit portion added to the circuit 8. As shown in FIG. 10, in this example, a latch circuit 8-11 is interposed between the counter 8-1 and the comparator 8-5, and the latch circuit 8-11 is connected to the interface circuit 8.
-10, when access to communication area 4-3-4 is detected, the count value from counter 8-1 at that time is held and output as is, while access to communication area 4-3-5 is detected. When detected, the count value from the counter 8-1 is output to the comparator 8-5 in pass mode. Therefore, from O8, it is necessary to extend the non-selection time, and before the non-selection time ends, communication area 4-
If 3-4 is accessed, comparator 8-5
As a result, the update of the count value to O8 is temporarily stopped, so that even if the count value of the counter 8-1 reaches the non-selection time or more, the O8 selection switching interrupt signal 9 is not output. However, if the communication area 4-3-5 is subsequently accessed, the temporary stop of the count value update is canceled and the count value from the counter 8-1 is directly compared with the non-selected time by the comparator 8-5. Therefore,
If the count value at that point is greater than or equal to the non-selection time, the O8 selection switching interrupt signal 9 is obtained immediately, and if it is less than the non-selection time, the O8 selection switching interrupt signal 9 is obtained when the non-selection time is reached. .

Of course, it is also possible to forcibly generate the O8 selection switching interrupt signal 9 at the time when access to the communication area 4-3-5 is detected. This can be generated in the same manner as in the case of shortening the non-selection time. In addition, since the non-selection time will be shortened or extended as necessary, there are communication areas 4-3-3 to 4-3-3 within area 4-3.
5 will generally be provided. Of course, there are various other methods that can be considered to shorten or extend the non-selection time.

[Effect of the invention] As explained above, according to claim 1, when a plurality of O8s are executed in parallel on an information processing system,
It is possible to easily deal with an increase in O8, and the AP diversion dust can be greatly improved.In addition, in the case of claim 2, when the control method is executed, part of the required functions is If this is realized by a program and further according to claim 3, the malfunction will not occur due to an interrupt from a peripheral device even immediately after O8 selection switching, and furthermore if according to claim 4, if the The selected time can be changed arbitrarily by an instruction from the O8 depending on whether or not there is a process in progress.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a system configuration of an example of an information processing system according to the present invention, FIG. 2 is a diagram showing a memory map of a memory as a component of the system, and FIG. 3 is a diagram showing information in the memory. FIG. 4 is a diagram showing the flow of an example of a program for evacuation, storage, and recovery. FIG. 4 is a diagram showing the contents of the vector table, and FIG. FIG. 6 is a diagram illustrating a configuration in one example, and FIGS. 7, 8, and 9 are diagrams illustrating configurations of an information processing system in other embodiments. FIG. 10 is a diagram for explaining a method of shortening and extending the non-selection time allocated to each O8. DESCRIPTION OF SYMBOLS 1...CPU, 2...Data bus, 3...Address bus, 4...Memory, 6...Interrupt control circuit, 7
. . . Peripheral processing request notification circuit, 8 . . O8 selection switching circuit, 14, 15 . . . Peripheral device, 4-2 .

Claims (1)

[Claims] 1. Two or more operating systems are executed on a processing device including a CPU and memory that accommodates a plurality of peripheral devices, and processing requests from each of the peripheral devices are sent to the peripheral device in advance. A program execution control method in an information processing system that is processed by an assigned operating system, in which an operating system previously stored in memory and application programs compatible with the operating system are executed in a time-sharing manner and cyclically. In order to do this, the operating system selection switching means provided outside the CPU displays the type of the operating system to the outside during the selection time pre-assigned to the operating system each time each operating system is selected in sequence. On the other hand, if the CPU receives an operating system switching interrupt when the type display starts, the information save/recovery means displays the information necessary for the next execution restart regarding the operating system selected immediately before. is temporarily saved in the memory until the next execution resumes, and processing requests from each peripheral device as an interrupt to the CPU are not processed unless the operating system assigned in advance to that device is currently selected. A program execution control method characterized in that mask control is performed by a peripheral processing request notification means based on an operating system type display. 2. The program execution control system according to claim 1, wherein the function as the information evacuation storage/recovery means is realized by executing a program stored in advance in the memory. 3. When there is an operating system switching interrupt,
1. All interrupts from each peripheral device are masked by the CPU until the information necessary for resuming execution of the currently selected operating system is recovered by the information saving/recovering means. 2. The program execution control method according to any one of 2. 4. If the operating system selection switching means receives an instruction to change the time from the currently selected and executed operating system before the end of the selected time previously allocated to the operating system, the instruction 4. The program execution control method according to claim 1, wherein the selection time is shortened or extended as required.