JPH036703A - Data converting device - Google Patents

Abstract

PURPOSE:To perform the conversion of data at a high speed by connecting one of two pairs of address and data terminals of a dual port RAM (DP-RAM) to a control part with the other pair connected directly to an input/output circuit respectively. CONSTITUTION:In a DP-RAM 4 the table data is rewritten by an instruction of a one-chip microcomputer 1 containing an I/O port. At the same time, the data having its address designated by the signal of an input circuit 7 is outputted directly to an output circuit 9 via a data latch 8. Thus the conversion of data is carried out with no intervention of the CPU of the microcomputer 1. As a result, a data converting speed equal to or higher than a conventional data converter using an EP-RAM can be attained. Furthermore it is possible to secure the handling easiness equal to or higher than a conventional soft correspondence type data converter owing to a fact that the table contents of the DP-RAM 4 can be freely rewritten via the microcomputer 1. Thus it is possible to easily cope with the change of the control contents in the present working state.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to improvements in data conversion devices suitable for use as sensor controllers, rotary positioners for absolute encoders, digital processing type fuzzy controllers, and the like.

(Summary of the Invention) This invention provides a
Contains memory such as P-RAM (dual port RAM), one set of which is connected to the control unit, and the other set is connected to the controller.
By connecting directly to the output circuit, it is possible to perform high-speed online data conversion, and it is possible to easily respond to changes in control content.

(Prior art and its problems) Conventional data conversion devices, such as rotary positioners and sensor controllers, convert multiple bits of input data into corresponding output data according to a fixed conversion table. There is. In such a data conversion device, not only the rewriting process of the conversion table but also the input/output conversion operation based on the rewritten conversion table is performed via the CPU of the control unit.

Therefore, the response time from the arrival of input data until the output data is obtained is greatly influenced by the processing speed of the CPU, so it is necessary to shorten the response time to 1 to 5 ms or less to speed up the conversion process. The problem was that it was not possible.

Therefore, in order to speed up such data table conversion processing, data conversion apparatuses that use memory elements such as ROM as they are have recently been used. This type of data conversion device is mainly applied to digital fuzzy controllers and absolute encoders, and is connected so that the address bus of 11ζ or PROM etc. can be used as an input side and the data bus can be used directly as an output side. ing.

However, according to this method, EP-
Since memory elements such as ROM are used, if it is necessary to make frequent changes to the contents of data tables such as fuzzy rules on site, new data can be stored in memory such as EP-ROM using a special dedicated device each time. Data table modification work becomes extremely troublesome because input has to be made.
There is a problem in that it is not possible to easily respond to changes in control contents as described above.

This invention was made in response to these conventional problems, and its main purpose is to enable high-speed processing of data conversion and to easily change control contents on site. The object of the present invention is to provide a data conversion device that can handle the following.

(Structure and Effects of the Invention) In order to achieve the above-mentioned objects, the present invention includes an operation section for inputting conversion data to be rewritten, an input circuit for taking in input data given from the outside, and two sets of address terminals. and a data terminal, and is capable of writing data in at least one direction and reading data in both directions; an output circuit that outputs converted data read from a data table in this memory to the outside; A control unit is connected to one set of address terminals and data terminals and rewrites the data table in the memory using conversion data, and the other set of address terminals and data terminals are connected to the input circuit and output circuit, respectively. It is characterized by:

Therefore, according to the present invention, the memory is provided with two
Since one set of address terminals and data terminals is connected to the control unit, the contents of the table in memory can be freely rewritten by the CPU of the control unit, making it possible to frequently change control contents on site. However, this can be easily accommodated.

In addition, since the address terminal and data terminal of the other set of memory are connected to the input circuit and output circuit, respectively, input/output control can be performed by using the table in the memory as input data in the same way as when using a normal EP-RROM. In this case, the data is processed without going through the CPU, so the response time is shortened accordingly, and data conversion can be performed at high speed.

(Example) Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing an embodiment of a data conversion device according to the present invention.

In the figure, reference numeral 1 denotes a one-chip microcomputer, which is equipped with an I10 port and has a function of controlling the entire data conversion device. This one-chip microcomputer 1 operates in synchronization with the clock of an oscillator 10a, and a DP-RAM 4, a ROM 5, and a RAM 6 are connected to its memory space via an address bus A.

A keyboard (operation unit) 2 consisting of a large number of key switches etc. is connected to the input side of the one-chip microcomputer 1, and various setting operations are performed using this keyboard 2 when inputting conversion data to the DP-RAM 4. It is done like this. On the other hand, on the output side of the one-chip microcomputer 1, there is an LED
A display 3 composed of a display, an LCD display, etc. is connected, and the display 3 displays mode setting contents and human output data.

In addition, the input section of the one-chip microcomputer 1 and the DPRAM
An input circuit 7 is provided between the input circuit 4 and the input circuit 4.

In this example, this input circuit 7 is designed for inputting 12-bit data, and is designed for inputting 12-bit data.
The level is converted to a signal level suitable for the internal circuit, and this is taken into a device such as a one-chip microcomputer 1.

The input circuit 7 is connected to the input section of the DP-RAM 4 via the address bus B, and the output section of this DP-RAM 4 is connected via the data bus B to the input section of the data latch 8. Furthermore, the output section of this data latch 8 is an output circuit 9.
, and data is sent from the data latch 8 to the output circuit 9 when in the unlatched state.

Reference numeral 10b is an oscillation circuit that generates a signal waveform of a predetermined frequency, and the output section of this oscillation circuit 10b is connected to the input section of an AND gate 11 to which the signal OE is input. The output part of this AND gate 11 is the gate RD of DP-RAM4.
2, and is also connected to the gate CE of the data latch 8 via the waveform changing circuit 12.

Further, the output part of the oscillation circuit 10b is directly connected to the waveform changing circuit 12, and from there the output part of the data latch 8 is
A pulse signal is sent to the As a result, when the signal OE is "H", the signal CE becomes "H", that is, the latch state, so that data output from the data latch 8 to the output circuit 9 is stopped.

Then, as shown in FIG. 2, the DP-RAM 4 arranged in the memory space of the one-chip microcomputer 1 has addresses $0000 to $
DP-RAM with a capacity of 4 bytes by 0FFF (A)
4a is located, and the address is $1000 ~
4 byte capacity DP-RAM (B
) 4b is placed. These DP-RAM (A)
4a and DP-RAM (B) 4b are each designed to be able to exchange 8-bit data.

On the other hand, when looking at the DP-RAM 4 from the input/output side, both DP-RAM (A) 4a and DP-RAM (B) 4b are located between addresses $000 and $FFF, as shown in Figure 3. The second 8 bits of output data D8 to D15 correspond to DP-RA to 1(B)4b, and the lower 8 bits of output data DO to D7 correspond to DP-RAM (A).
Compatible with 4a. Therefore, although this data conversion device can change the contents of the data table using an 8-bit CPU, the input data is
It is designed to perform input/output control of 2 bits and 16 bits of output data DO to D15.

That is, the DP-RAM 4 is provided with a table area for input/output data as shown in FIG.
(input data 12 bits) is set as a table area, and the corresponding output data 16 bits conversion data can be arbitrarily rewritten. More specifically, the upper 8 bits and lower 8 bits of the 16 bits of output data
The bits are DP-RAM (B) 4b and DP-R, respectively.
It is designed to be rewritten to AM (A) 4a.

In this DP-RAM 4, table data is rewritten according to instructions from the one-chip mine 1, and data addressed by a signal from the input circuit 7 is output directly to the output circuit 9 via the data latch 8. being done.

The data latch 8 operates similar to a so-called transparent latch. That is, gate C
When the gate is opened by the signal "L" of the gate E, the data on the data bus B14 is directly applied to the output circuit 9, whereas when it is closed by the signal "H" of the gate CE, the data from the data bus B14 is directly applied to the output circuit 9. It is designed to hold data.

Then, the data given to the gate RD2 of the DP-RAM4 = sale signal, and the gate 1-C of the data latch 8.
The signals applied to the gates RD2. The data is sent to the CE.

The timing of the signal generated in this oscillation circuit 10b is set in consideration of the access time T of the DP-RAM 4, as shown in FIG. That is, gate RD2
The clock of the oscillator 10a is set to be divided and outputted so that the time from the falling state of the signal to the rising state of the gate CE signal is longer than the access time T of the DP-RAM 4.

Here, the signal OE input to the gate 11 is used to prevent the data being rewritten from being inadvertently sent to the output circuit 9 when the one-chip microcomputer 1 rewrites the data contents of the DP-RAM 4. Gate RD2 and CE
When the signal OE is in the "H" state, the output of the signal OE is stopped and the operation of the output circuit 9 is fixed.

Next, the operation of this data conversion device will be explained according to the flowchart shown in FIG.

First, in step 401, the input data 15 from the input circuit 7 is
Read the contents with one-chip microcomputer 1, step 40
At step 2, the microcomputer 1 reads the contents of the output data 16 from the output circuit 9. Next, in step 403, the data content of the input/output state read by the microcomputer 1 is displayed on the display 3.

Next, in step 404, input the data contents of the input/output state to the CPU by operating the keyboard 2, and step 40
Proceeding to step 4, predetermined program processing is executed.

Thereafter, in step 406, it is determined whether or not the data contents are to be rewritten by the DP-RAM 4.

If not, the process returns to step 401, and the operations up to step 405 are repeated until a decision to rewrite is made. If you want to rewrite this, step 40
Proceed to step 7. In step 407, the signal to the AND gate 11 is set to "H" to fix the output of the data latch 8. Next, in step 408, the one-chip microcomputer 1
Rewrite the data contents of RAM4. In this case, since the operating state of the output circuit 9 is stopped in advance in step 407, the data being rewritten will not be inadvertently output to the output circuit 9. When all data rewriting of the DP-RAM 4 is completed in this way, the signal OE to the AND gate 11 is changed to "L" in step 409, and then step 401
to continue the hard I/O control described above.

Thus, the DP-RAM 4 is directly addressed by the input data taken from the human horn circuit 7. Therefore, the output data corresponding to each input data is immediately read from the DP-RAM 4, and the data latch 8
The signal is sent out from the output circuit 9 through the output circuit 9. Therefore, according to this conversion device, the CP of the one-chip microcomputer 1
Since data conversion is performed without going through U, EP-RAM
Data conversion can be performed at speeds comparable to or faster than conventional devices of the type used.

Moreover, with this data conversion device, the table contents of the DP-RAM 4 can be freely rewritten using the one-chip microcomputer 1, making it as easy to use as or even better than conventional software-compatible devices. This makes it possible to easily respond to changes in control content at the site of use.

In the embodiment, the digital signals input and output to the data conversion device are used as they are, but the signal contents may be changed and used depending on the object to be controlled. For example, by grouping each input/output signal into four bits and weighting each signal appropriately, the data stored in the table in the memory can be used as fuzzy inference value data. In this case, this data conversion device itself functions as a three-person car, four-output type fuzzy controller.

Furthermore, in the present invention, the memory such as DP-RAM is not limited to one in which data is written only from the one-chip microcomputer side, but also one in which data is written from both sides of the same microcomputer and the input/output circuit. Also included.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of a data conversion device according to the present invention, Fig. 2 is a main part configuration diagram showing the data input/output state of the DP-RAM, and Fig. 3 is the table contents of the DP-RAM. FIG. 4 is a timing chart of a signal generated by an oscillation circuit, and FIG. 5 is a flowchart showing the processing contents of data conversion operation. 1... One-chip microcomputer (control unit) 2... Keyboard (operation unit) 3... Display unit 4... DP-RAM (memory) 7... Input circuit 8... Data latch 9. ...output circuit], Ob...oscillation circuit

Claims (1)

[Scope of Claims] 1. An operating unit for inputting conversion data to be rewritten, an input circuit for taking in input data given from the outside, and two sets of address terminals and data terminals, and capable of receiving data from at least one direction. A memory that can write data and read data from both directions; an output circuit that sends converted data read from a data table in this memory to the outside; and an output circuit that is connected to the address terminal and data terminal of one set of the memory. A data conversion device comprising: a control unit that rewrites a data table in a memory using conversion data; and an address terminal and a data terminal of the other set are connected to the input circuit and the output circuit, respectively.