JPH0366275A - Television signal processing circuit - Google Patents

Abstract

PURPOSE:To attain effective utilization of an NTSC display screen by displaying all the picture of the High Vision signal to upper or lower side of the NTSC system picture as a master picture and displaying a small picture onto a video image missing part of the picture of the NTSC signal caused due to the difference from the aspect ratio. CONSTITUTION:A scanning line conversion circuit 15 discards 75 scanning lines among 1125 scanning lines into 1050 lines and outputs as it is without throwing away information of both left and right ends. An output signal of luminance signal processing circuit 6 is inputted to an input terminal 19, a vertical signal compression circuit 20 compresses the video signal into 350 lines to form a main picture F1 and the result is inputted to a changeover circuit 24. On the other hand, the signal inputted to the input terminal 19 is inputted to a vertical direction compression circuit 21, where the number of scanning lines is compressed into 175 lines, and the time axis is compressed to nearly 1/3 by a horizontal direction compression circuit 22 to form a small pattern F2.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a television signal processing circuit for a television receiver configured to display a high-definition signal on a screen of the current NTSC system. .

[Prior art] Figure 6 shows the 1986 Institute of Electronics, Information and Communication Engineers Spring National Conference D-
169 is a block diagram showing the configuration of a conventional television signal processing circuit reported and disclosed as a MUSE-525 main converter. In the same figure, (1
) is an input terminal that inputs the MUSE signal, (2) is an A/D conversion circuit that receives the signal arriving at its input terminal (1), and (3) is an input terminal that receives the output signal of A/D conversion circuit (2). The input de-emphasis circuit, 0) is the A/D conversion circuit (2
This is a PLL circuit that receives the output signal of ) as input.

(5) is a scanning line conversion circuit that inputs the output signal of the de-emphasis circuit (3) and converts the number of scanning lines from 1125 to 1050, and (6) inputs the output signal of the scanning line conversion circuit (5). A luminance signal processing circuit (7) is a color difference signal processing circuit which inputs the output signal of the scanning line conversion circuit (5).

(8) is a D/A conversion circuit which receives the output signal of the luminance signal processing circuit (6) as input, and (8) and (10) have D/A conversion circuits which receive the output signal of the color difference signal processing circuit (7) as input. /A conversion circuit, (10) is a D/A conversion circuit that receives the output signal of the color difference signal processing circuit (7), and (11) is each of the above D/A conversion circuits.
Inverse matrix circuits (12), (13), which receive the output signals of conversion circuits (8), (9), and (10) as inputs;
(14) is an output terminal for outputting the output signal of the inverse matrix circuit (11) to the outside.

Next, the operation of the above configuration will be explained.

A MUSE signal obtained by band-compressing a high-definition signal is input to an input terminal (1). In detail, high-definition signals have a scanning line count of 1125 and a field frequency of 60).
1z, 2:1 interlaced signal.

In the MUSE system, the high-definition signal is band-compressed to about 8 MHz in order to be transmitted on one channel of satellite broadcasting. Band compression in this case is performed by offset subsampling, and for the stationary part,
Inter-field and inter-frame offset subsampling For video portions, inter-line offset subsampling is used.

In addition, in order to transmit in one channel, two phase difference signals (hereinafter referred to as R-Y signal and B-Y signal) are used as a luminance signal (
The signal is time-compressed and multiplexed during the blanking period of the Y signal (hereinafter referred to as the Y signal).

The MUSE signal input to terminal (1) is sent to the A/D converter (
After being quantized by step 2), it is input to the PLL circuit 0). This PLL circuit (4) reproduces a correct sampling clock based on the phase information in the MUSE signal.

The signal sampled with the correct phase as described above is then input to the de-emphasis circuit (3).
The frequency characteristics are corrected, and the signal with the corrected frequency characteristics is converted from a signal of 1125 trees/frame to a signal of 1050 trees/frame by a scanning line conversion circuit (5).

Since the high-definition signal handles images with an aspect ratio of 9=16, it cannot be displayed on a conventional 3:4 screen as it is. Therefore, in the scanning line conversion circuit (5) described in 1:, by discarding part of the scanning line information, that is, 75 lines, and discarding information at both left and right ends, 1050 trees/frame are obtained as shown in FIG. , aspect ratio 3:
Convert to 4 information.

The signal thus converted is processed separately into a Y signal, a RY signal, and a BY signal. The luminance signal processing circuit (8) performs intra-field interpolation corresponding to line-to-line offset subsampling. After that, 525
The signal is converted into the main interlaced signal, and is also converted into an analog signal in the D/A conversion circuit (8).

On the other hand, in the color difference signal processing circuit (7), each of the time compression multiplexed RY signal and BY signal is expanded in time and subjected to field interpolation.

After this, it is converted into a 525-line interlaced signal and D
By converting the signal into an analog signal using the /A conversion circuits (9) and (io), 525 interlaced signals of RY signal and BY signal are obtained. The Y signal, RY signal, and B-Y signal thus obtained are input to an inverse matrix circuit (11), converted into R.G-H, and displayed on the CRT screen (F).

In addition, at the above-mentioned 1986 Institute of Electronics, Information and Communication Engineers Spring National Conference D-169, the full screen of high-definition signals (
In order to display Fl) on the NTSC display screen (F), a proposal has also been proposed in which the upper and lower portions (Fa) of the NTSC display screen (F) are cut off and displayed, as shown in FIG.

[Problem to be solved by the invention] Conventional television signal processing FF! Since the circuit is configured as described above, the video of the high-definition signal can be converted to NTS.
When displaying on a C display, information on both ends of the high-definition signal may be cut off due to the difference in aspect ratio.
There is a problem in that there are wasted areas at the top and bottom of the NTSC display, making it impossible to use one screen effectively.

This invention was made to solve the above-mentioned problems, and it is possible to display the entire screen of a high-definition signal on an NTSC display, and it also makes it possible to effectively display the part that does not produce an image due to the difference in aspect ratio. It is an object of the present invention to provide a television signal processing circuit that can be utilized.

[Means for Solving the Problems] The television signal processing circuit according to the present invention projects the entire screen of a high-definition signal as the main screen on the -L side or lower side of the NTSC screen, and eliminates the problem caused by the difference in aspect ratio. The present invention is characterized in that a small screen is displayed on the lower or upper portion of the NTSC screen where the video is missing.

[Operation] According to the present invention, by projecting a small screen created from a high-definition signal on the lower or upper part of the NTSC screen that is missing due to the difference in aspect ratio of the high-definition signal, the NTSC The display screen can be used effectively.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the configuration of a television signal processing circuit according to an embodiment of the present invention.
Since (1) to (14) are the same as the conventional example shown in Fig. 6,
The same reference numerals are given to the corresponding parts, and detailed explanation thereof will be omitted.

In FIG. 1, (16) is a composite screen creation circuit that receives the output signal of the luminance signal processing circuit (6), (17), (
18) is a composite screen creation circuit which receives the output signals of the color difference signal processing circuit (7) as inputs.

Next, the operation of the above configuration will be explained.

The scanning line conversion circuit (15) discards 75 scanning lines out of 1125 scanning lines and creates 1050 scanning lines, 2:1 interlacing, and a field frequency of 60 Hz, but outputs the information as it is without discarding the information at both left and right ends. do. The output signals Y signal, RY signal and BY signal are each processed separately.

The Y signal is subjected to intra-field interpolation corresponding to line-to-line offset subsampling in the luminance signal processing circuit (8), and then converted to a 525-line interlaced signal as shown in Figure 2 (b), resulting in a composite screen. Creation circuit (16
) is entered. This composite screen creation circuit (16) is the third
It has the configuration shown in the figure, and the luminance signal processing circuit (6
) is input to the input terminal (19). This input signal is compressed into 350 video signals in the vertical compression circuit (20) to create a main screen (Fl) as shown in Fig. 2(c), and then output to the switching circuit (20). .

On the other hand, the signal input to the input terminal (18) is input to the vertical compression circuit (21), where the video signal is compressed into 175 lines, and the horizontal compression circuit (22) converts the time axis by about 1
/3, and as shown in Figure 2(d), the small screen (F2)
is being created.

Next, the output signal of this horizontal direction compression circuit (22) is input to a memory circuit (23), and this memory circuit (23)
In this case, one frame's worth of data is delayed, and when a stop signal is input, memory writing is stopped and only one frame's worth of the same data is repeatedly read out. That is, the small screen (F2) is a frozen screen.

Next, the output signal of the memory circuit (23) is input to the switching circuit (24), and this switching circuit (24) receives the output signals of the vertical compression circuit (20) corresponding to 350 lines on the screen. , the next 175 lines are displayed as shown in Fig. 2(e) by taking the output signal of the memory circuit (23), and are sent to the D/A conversion circuit (8) through the output terminal (25).
It is output to.

Regarding the color difference signals, the two time compression multiplexed color difference signals, that is, the RY signal and the BY signal, are time-expanded and subjected to intra-field interpolation in the color difference signal processing circuit (7). After this, it is converted into a 525-line interlaced signal.

The R-Y signal is sent to the composite screen creation circuit (17), and also to the B-
The Y signal is output to a composite screen creation circuit (18).

The composite screen creation circuits (17) and (18) described above have the same configuration as the composite screen creation circuit (16), and after the same processing is performed, the D/A conversion circuit (9).

It is output to (lO). Below, as in the conventional example, R-
It is converted into G-H and displayed on the CRT screen (F).

In the above embodiment, the small screen (F2) is placed at the bottom right, but it may be placed at the bottom left or center, or the main screen (Fl)
may be placed at the bottom and the small screen (F2) at the top.

Further, in the above embodiment, the small screen (F2) is arranged only at - location, but as shown in FIG. 4, it may be arranged at three locations and a strobe function may be provided.

Furthermore, in the above embodiment, the main screen is a moving image and the small screen is frozen, but as shown in FIG. In FIG. 5, the same components as in FIG. 3 are denoted by the same reference numerals, and their explanation will be omitted.

In FIG. 5 above, the memory circuit (2B) receives the output signal of the vertical compression circuit (20) as input, delays data for one frame, and stops writing to the memory upon input of the stop signal. Then, only the same data for one frame is read out repeatedly. That is, the main screen (Fl) is a fleece screen. The output signal of this memory circuit (2B) is
Input to 0.

Hereinafter, by the same operation as the composite screen creation circuit shown in Figure 3,
The main screen is frozen and the small screen is displayed as a moving image on the CRT.

[Effect of the invention 1 As described above, according to the present invention, when displaying an image of a high-definition signal on an NTSG display, it is possible to display the entire screen, and at the same time, it is possible to display a small screen in the part where no image is generated due to the difference in aspect ratio. By displaying the screen, the screen can be used effectively.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a television signal processing circuit according to an embodiment of the present invention, FIG. 2 is a diagram explaining the operation, and FIG. 3 is a block diagram showing the specific configuration of the composite screen creation circuit 1 2 , FIG. 4 is a diagram for explaining the operation of another embodiment of the invention, FIG. 5 is a block diagram showing the configuration of a composite screen creation circuit according to another embodiment of the invention, and FIG. 6 is a conventional example. FIGS. 7 and 8 are block diagrams showing the configuration of a television signal processing circuit, respectively, for explaining the operation of the conventional example. (5)...Scanning line conversion circuit, (6)...Luminance signal processing circuit, (7)...Color difference signal processing circuit, (8), (9)...
), (10)...D/A conversion circuit, (11)...inverse matrix circuit, (18), (17), (18)...
Composite screen creation circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A television signal processing circuit for a television receiver configured to display high-definition signals on NTSC screens with different numbers of scanning lines and aspect ratios,
A scanning line number conversion circuit that converts the number of scanning lines, a signal processing circuit that processes the output signal of this scanning line number conversion circuit, and a system that displays the entire screen of the high-definition signal as the main screen on the top or bottom of the NTSC screen. and a composite screen creation circuit that synthesizes a small screen created from the high-definition signal so that it is projected on the lower or upper video missing portion of the NTSC screen caused by the difference in aspect ratio. A television signal processing circuit comprising: