JPH0365695B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a time division multiple access communication device suitable for satellite communication. In particular, the present invention relates to a time division multiple access (hereinafter referred to as TDMA) communication device that allows testing and maintenance of a single device efficiently and economically.

[Conventional technology]

In the TDMA communication system, each station transmits a burst-like signal at a specified timing based on a TDMA frame determined by a reference synchronization burst sent out by a reference station, and communicates by controlling so that the bursts do not overlap with each other. .

When operating this TDMA communication device, it is necessary to periodically confirm that there is no deterioration in the transmit signal system and the receive signal system. Conventionally, this test has been performed using a test device as shown in FIG. 4, which uses a pseudo reference station device that generates a signal with the same shape as the reference burst sent out by the reference station. FIG. 4 is a block diagram showing the connection between a conventional time division multiple access communication device and a test device. In Figure 4, TD is
TDMA communication device, PAT is line pattern writing device, TRE is pseudo reference station device, NOC is noise generator, ERM is error rate measuring device, and H ₃ and H ₄ are hybrid circuits.

Here, first, the line pattern writing device PAT writes a test line pattern that receives the signal transmitted by the TDMA communication device TD of the device under test as it is.
Next, the reference burst transmitted by the pseudo reference station device TRE is received, and after establishing reception frame synchronization, initial acquisition is performed, transmission burst synchronization is established, and a state is established in which the transmission signal can be returned and received. Furthermore, an appropriate level of noise is added from the noise generator NOC, and the data error rate at this time is measured by the error rate measuring device ERM.

[Problem that the invention seeks to solve]

However, in order to conduct this test, the pseudo reference station equipment TRE was indispensable in order to establish the TDMA frame standards as described above. Also, recent
In some TDMA satellite communication systems, in order to economically configure the slave station equipment, the transmission timing of the slave station is determined from the reference station. A function for inputting control signals and the like to the reference burst is required, which poses a problem in that the pseudo reference station device TRE becomes complicated and expensive.

The present invention solves the above-mentioned problems.
The purpose of the present invention is to provide a TDMA communication device that allows testing and maintenance of a transmitting/receiving system on a standalone device efficiently and economically.

[Means for solving problems]

The present invention includes a transmission/reception control memory that stores line patterns of transmission bursts and reception bursts, and a transmission/reception timing generation means that generates a transmission timing control signal and a reception timing control signal based on the line patterns from the transmission/reception control memory. , a time division multiple access communication device comprising a modulation circuit for transmitting the transmission burst, and a demodulation circuit for receiving the reception burst, further comprising a folding means for folding back an output signal of the modulation circuit to the demodulation circuit; a phase difference setting means for setting a phase difference between the timing control signal and the received timing control signal to a value corresponding to a delay time between the transmitted signal and the received signal via the folding means, and receiving the transmission burst of the own station as it is; and test line pattern setting means for setting a test line pattern corresponding to a state in which the transmitting/receiving timing generation circuit is set.

The present invention can include means for superimposing noise on the folding means. Further, the test line pattern may have a configuration stored in a transmission/reception control memory.

[Effect]

In the present invention, each device is prepared with a test line pattern corresponding to a state in which it receives its own transmission burst as is. Based on this line pattern, a transmission burst is sent out from the modulation circuit, and the transmission burst is input to the demodulation circuit as it is (or with noise superimposed and the level adjusted) by a return means.
The device receives and processes the signal returned by the return means using the reception timing control signal whose phase is shifted by the phase difference setting means by a value corresponding to the delay time during which the transmission signal passes through the return means from the transmission timing control signal. Testing and maintenance of a single transmission/reception system can be performed efficiently and economically.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a time division multiple access communication device according to an embodiment of the present invention. In FIG. 1, a normal line pattern 11 and a control signal 12 such as a clock are connected to respective inputs of a line pattern memory control circuit MEM-CONT from a line pattern writing device PAT (not shown). A line pattern 15 and a control signal 16 from the line pattern memory control circuit MEM-CONT are connected to respective inputs of the transmission control memory TX-MEM, and a normal transmission side line pattern is written. Further, the line pattern 17 and the control signal 18 are connected to respective inputs of the reception control memory RX-MEM, and a normal reception side line pattern is written therein.

The features of the present invention are the test line pattern storage section, the transmission signal loopback section, and the loopback time delay section surrounded by the dashed line. That is, the test signal 51 from the control circuit CONT is connected to the control inputs of the transmission control memory TX-MEM and the transmission timing generation circuit TX-TMG. Also,
A test signal 51 from the control circuit CONT is connected to the control inputs of the reception control memory RX-MEM and the reception timing generation circuit RX-TMG. moreover,
A test signal 51 from the control circuit CONT is connected to the coaxial switch COS.

Here, in the normal case, the test signal 51 is "0" and the transmission control memory TX-MEM and the reception control memory RX-MEM are the line pattern writing device.
It operates based on the normal line pattern written from PAT. In addition, a received burst 41 is inputted to one input of the coaxial switch COS from a satellite not shown, and this received burst 41 is selected by the demodulation circuit.
Connected to the DEM input. A demodulated signal 43 from the demodulation circuit DEM is connected to the inputs of the scrambler DSCR and the synchronization signal detection circuit STNC-DET.
The demodulated signal 43 is decoded by the desk clamp DSCR and connected to the input of the separation control circuit DE-MUX. The synchronization signal detection circuit SYNC-DET detects the first synchronization signal transmitted by the reference station and the local station from the demodulated signal 43, and the frame synchronization control circuit
Connected to the FRM-SYNC input. The control signal that establishes the reception timing from the complaint synchronization control circuit FRM-SYNC is sent to the reception timing generation circuit RX.
- connected to the receive timing control input of the TMG;
The reception timing generation circuit RX-TMG frame counter is reset. A timing signal from the reception timing generation circuit RX-TMG is connected to the timing input of the reception control memory RX-MEM,
The normal receiving line pattern is transferred from the reception control memory RX-MEM to the reception timing generation circuit RX-TMG.
connected to the line pattern input. The reception timing control signal from the reception timing generation circuit RX-TMG is connected to the control input of the separation control circuit DE-MUX, and the control signal 4 is connected from the separation control circuit DE-MUX.
5 is connected to a DSI/DNI interface device (not shown), and the output signal 46 of the separation control circuit from which only the channel for the own station is extracted is connected to the specified DSI/DNI interface device.

In addition, the control signal from the frame synchronization control circuit FRM-SYNC is transmitted to the burst synchronization control circuit BST-
SYNC, a control signal that establishes the transmit timing is connected to the reset input of the transmit timing generation circuit TX-TMG, and the control signal that establishes the transmit timing is connected to the reset input of the transmit timing generation circuit TX-TMG.
The TX-TMG frame counter is reset. The timing signal from the transmission timing generation circuit TX-TMG is connected to the timing signal input of the transmission control memory TX-MEM, and the timing signal is connected to the transmission control memory TX-MEM.
The normal transmission side line pattern from TX-MEM is connected to the line pattern input of the transmission timing generation circuit TX-TMG, and the transmission timing generation circuit TX-
A transmission timing control signal is connected from the TMG to a control input of a multiplex control circuit MUX. multiple control circuit
The sub-burst control signal 32 from MUX is not shown in the diagram.
The data is output to the DSI/DNI interface device, and the transmission data 31 from the designated DSI/DNI interface device is input to the multiplex control circuit MUX. Also, the timing signal is sent from the transmission timing generation circuit TX-TMG to the preamble generation circuit SYNC-GEN.
connected to the input of the preamble generation circuit SYNC
-Preamble 30 from GEN is a multiplex control circuit
Connected to the preamble input of the MUX. The preamble 30 and the transmission data 31 are synthesized and multiplexed from the multiplex control circuit MUX and sent to the scrambler.
Connected to the input of the SCR. The code-converted signal from the scrambler SCR is connected to the input of the modulation circuit MOD. The carrier wave is modulated from the modulation circuit MOD and the transmission burst signal 33 is sent to the hybrid circuit H ₁
The transmission signal 34 is sent to a satellite (not shown) from one output of the hybrid circuit _H1 .

In the case of a test, when the test signal 51 is set to "1" by a switch or remote control, the transmission control memory TX-MEM and the reception control memory RX-
MEM operates based on the contents of its internal read-only memory (ROM). The transmission timing generation circuit TX-TMG free-runs in a frame period, and a transmission frame pulse 52 indicating the beginning of a transmission frame is connected to the transmission control memory TX-MEM. Transmission timing generation circuit TX−
The TMG outputs the sub-burst control signal 32 via the multiplex control circuit MUX based on the test line pattern of the transmission control memory TX-MEM, and
Transmission data 3 from DSI/DNI interface device
Enter 1. Similarly to when the test signal 51 is "1", the timing signal is sent from the transmission timing generation circuit TX-TMG to the preamble generation circuit SYNC.
The preamble 30 from the preamble generation circuit SYNC-GEN is connected to the preamble input of the multiplex control circuit MUX, and the output signal of the multiplex control circuit MUX is the scrambler SCR.
and is connected to the input of the hybrid circuit _H1 via the modulation circuit MOD.

A folded signal 35 from the other output of the hybrid circuit _H1 is connected to one input of the hybrid circuit _H2 via the isolation amplifier IA and the attenuator _AT1 . Noise from the noise generator NOC is connected via an attenuator AT ₂ to the other input of the hybrid circuit H ₂ . Return signal 36 with noise superimposed from hybrid circuit _H2
is connected to the other input of the coaxial switch COS.
When the strike signal is “1”, this return signal 36
is selected and connected to the demodulation circuit DEM. The demodulation circuit is similar to when the test signal 51 is "0".
The demodulated signal 43 of the DEM is connected to the separation control circuit DE-MUX via the descrambler DSCR.

Further, a transmission frame pulse 52 indicating the beginning of the transmission frame is connected from the transmission timing circuit TX-TMG to the delay circuit DEL. A delayed pulse 53 delayed by a time corresponding to the delay time of the test system is sent from the delay circuit DEL to the reception timing generation circuit RX-.
The frame counter of the reception timing generation circuit RX-TMG is reset to the beginning of the frame, and the test signal 51 is connected to the delay pulse input of the TMG.
Reception processing is performed in the same way as when is "1".

The operation of the time division multiple access communication device having such a configuration will be explained. Transmission control memory in Figure 1
TX-MEM and reception control memory RX-MEM
In this case, the transmission line pattern that specifies the type and position of the transmission burst is written in the transmission control memory TX-MEM, and the transmission side line pattern that specifies the type and position of the transmission burst is written in the reception control memory RX-MEM.
The receiving side line pattern that specifies the type and position of the receiving burst is written in , but the hardware may be the same.

Usually, the line pattern is transferred from the line pattern writing device PAT shown in FIG.
Input to CONT. A transmitting side circuit pattern 15 and a control signal 16 are input from the line pattern memory control circuit MEM-CONT to the transmitting control memory TX-MEM, and a receiving side line pattern 17 and a control signal 18 are inputted to the receiving control memory RX-MEM.

Furthermore, when the test signal 51 input from the control circuit CONT is "0", the transmission control memory TX-MEM and the reception control memory RX-MEM operate based on the contents written from the line pattern writing device PAT, When the test signal 51 is "1", it operates based on the contents of an internal read-only memory (ROM).

The transmission timing generation circuit TX-TMG outputs the sub-burst control signal 32 through the multiplex control circuit MUX based on the transmission line pattern stored in the transmission control memory TX-MEM, and
Transmission data 3 from DSI/DNI interface device
Power 1. Preamble generation circuit SYNC−
GEN generates a preamble 30 based on the timing signal output from the transmission timing generation path TX-TMG.

The multiplex control circuit MUX synthesizes the transmission data 31 input from multiple DSI/DNI interface devices and the preamble 30 input from the preamble generation circuit SYNC-GEM and generates a scrambler.
Output to SCR. The signal thus synthesized is subjected to necessary scrambling by a scrambler SCR, modulated by a modulation circuit MOD, and transmitted as a burst signal 33.
is output as An example of the transmission burst 33 formed in this way is shown in FIG. FIG. 2 is a frame format of a transmission burst of the time division multiple access communication device of the present invention. In Figure 2, 30
31 indicates a preamble, and 31 indicates transmission data such as an audio signal.

The transmission burst 33 is divided by the hybrid circuit _H1 into a transmission signal 34 connected to an antenna and a return signal 35 used for a return test.
The loopback test system connects the attenuator AT ₁ for level adjustment after passing through the isolation amplifier 1A.
and the noise generator NOC via the attenuator AT ₂ for level adjustment in the hybrid circuit H ₂
is combined with the output signal of , and becomes a folded signal 36.

FIG. 3 is a frame format showing a state in which bursts transmitted by each station are time-division multiplexed.
The bursts transmitted by each station are controlled by the satellite transponder so that they do not overlap with each other, and are time-division multiplexed as shown in FIG. In FIG. 3, preamble 30 and transmission data 31 indicate the burst transmitted by the first earth station, and preamble 30',
Transmission data 31' indicates a burst transmitted by the second earth station, preamble 30'', transmission data 3
1'' indicates the burst transmitted by the third earth station.

In the normal case, that is, when the test signal 51 output by the control circuit CONT is "0", the TDMA frame signal in the format shown in FIG. 3 is the received signal 4.
It is input to the demodulation circuit DEM as 1.

When performing a local station loopback test, that is, the control circuit
When the test signal 51 output by CONT is "1", a folded signal 36 obtained by superimposing noise on the folded signal 35 of the TDMA frame shown in FIG. 2 is input to the demodulation circuit DEM.

This input signal is demodulated by the demodulation circuit DEM and then input to the synchronization signal detection circuit SYNC-DET and the descrambler DSCR. Synchronous detection circuit
SYNC-DET detects the burst synchronization signal transmitted by the reference station and its own station from this demodulated signal 43, and establishes frame synchronization and reception timing using the frame synchronization control circuit FRM-SYNC and burst synchronization control circuit BST-SYNC. Then, it controls the transmission timing generation circuit TX-TMG so that burst synchronization is achieved and the bursts transmitted by the own station do not overlap with the bursts transmitted by other stations on the satellite.

The reception timing generation circuit RX-TMG outputs the control signal 45 from the separation control circuit DE-MUX to the specified DSI/DNI interface device based on the reception line pattern stored in the reception control memory RX-MEM. The output signal 46 of the separation control circuit DE-MUX is controlled to be input.

Next, we will discuss the case where a signal loopback test is performed using the TDMA communication device TD alone. In this case, this test operation is entered by a switch or remote control, and the test signal 51 output by the control circuit CONT is
It is distinguished from normal operation by having the value "1".

The transmission control memory TX-MEM and the reception control memory RX-MEM operate based on the contents of an internal read-only memory (ROM). The frame counter of the transmission timing generation path TX-TMG free runs at the frame period. The transmission frame pulse 52 indicating the beginning of the transmission frame output by the frame counter of the transmission timing generation circuit TX-TMG is converted to the delay time of the test system by the delay circuit DEL, that is, multiplex control circuit MUX→scrambler SCR→modulation circuit MOD →Hybrid circuit H ₁ →Isolation amplifier IA →Attenuator AT ₁ →Hybrid circuit H ₂ →Coaxial switch
COS→Demodulation circuit DEM→Descrambler DSCR→
The delayed pulse 53 is delayed by a time corresponding to the time required to pass through the separation control circuit DE-MUX.
This slow pulse 53 is input to the reception timing generation circuit RX-TMG, and the frame counter of the reception timing generation circuit RX-TMG is reset to the beginning of the frame by this slow pulse 53.

A return signal 36 of the test return system is selectively connected to the input of the demodulation circuit DEM by a coaxial switch COS. The return signal 36 of this test return system is the second
Although the TDMA frame shown in the figure does not include the reference burst REF shown in Figure 3, the beginning of the frame of the reception timing generation circuit RX-TMG is delayed by the delay time of the test system. Since it has been reset by the delayed delay pulse 53, this received signal can be received and processed.

Attenuator connected to noise generator NOC
By setting AT ₂ and measuring the signal error rate at that time, it is possible to determine whether the transmission and reception characteristics of this TDM communication device have deteriorated.

In this embodiment, the transmission timing generation circuit TX-
Although we have shown how to reset the frame counter of the reception timing generation circuit RX-TMG using the frame pulse output from the TMG frame counter,
Conversely, the transmission timing generation circuit TX− is based on the pulse output from the reception timing generation circuit.
It is also possible to reset the TMG frame counter.

In addition, the test line pattern was explained assuming that the transmission/reception control memory is written in the read-only memory (ROM), but it is stored in the line pattern memory control circuit MEM-CONT, which is the interface for writing the line pattern from the outside. You can also make it so that

〔Effect of the invention〕

As described above in detail, the present invention has the excellent effect of being able to receive transmission signals from a TDMA communication device and test whether there is any deterioration in the transmission/reception system without a pseudo reference station device or a line pattern writing device. Therefore,
Testing and maintenance can be carried out efficiently and economically, which has a great effect on the practical application of TDMA communications.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a time division multiple access communication device according to an embodiment of the present invention. FIG. 2 is a frame format of a transmission burst of the time division multiple access communication device of the present invention. FIG. 3 shows a frame format in which bursts transmitted by each station are time-division multiplexed. FIG. 4 is a block diagram showing the connection between a conventional time division multiple access communication device and a test device. AT ₁ ~ AT ₂ ...Attenuator, BST-SYNC...
Burst synchronization control circuit, CONT...control circuit,
COS…Coaxial switch, DEL…Delay circuit, DEM…
Demodulation circuit, DSCR...descrambler, DE-MUX
...Separation control circuit, ERM...Error rate measurement circuit, FRM
-SYNC...Frame synchronization control circuit, H ₁ to _{H 4} ...Hybrid circuit, IA...Isolation amplifier,
MEM-CONT...Line pattern memory control circuit,
NOC...Noise generator, PAT...Line pattern writing device, RX-MEM...Reception control memory, RX-TMG
…Reception timing generation circuit, SCR…Scrambler, SYNC-DET…Synchronization signal detection circuit, SYNC
-GEM...Preamble generation circuit, TD...Time division multiple access communication device, TRE...Pseudo reference station device, TX
-MEM... Transmission control memory, TX-TMG... Transmission timing generation circuit, 11, 15, 17... Line pattern, 12, 16, 18... Control signal, 30... Preamble, 31... Transmission signal of DSI/DNI interface device, 32...Subburst control signal, 33...
Transmission burst, 34... Transmission signal, 35, 36... Return signal, 41... Reception signal, 43... Demodulation signal, 4
5... Control signal of separation control circuit (DE-MUX),
46... Output signal of separation control circuit (DE-MUX),
51...Test signal, 52...Transmission hoom pulse, 5
3...Delayed pulse.

Claims (1)

[Scope of Claims] 1. A transmission/reception control memory that stores line patterns of transmission bursts and reception bursts, and a transmission timing generation circuit that generates a transmission timing control signal based on the line patterns from the transmission/reception control memory; a reception timing generation circuit that generates a reception timing control signal based on a line pattern from a transmission and reception control memory; a modulation circuit that modulates the transmission burst as a transmission signal; a demodulation circuit that demodulates the reception burst from the reception signal; and a demodulation circuit that demodulates the reception burst from the reception signal. a synchronization signal detection circuit that detects the synchronization signal of the burst transmitted by the reference station from among the output reception bursts of the circuit; and a frame synchronization control that controls frame synchronization of the reception timing generation circuit according to the output of the synchronization signal detection circuit. and a burst synchronization control circuit for controlling burst synchronization of the transmission timing generation circuit in accordance with the output of the synchronization signal detection circuit, wherein the switch means performs the automatic transmission in place of the received signal. A loopback means for loopback connecting the output signal of the modulation circuit of the station to the demodulation circuit, and a delay circuit for delaying the output pulse of the transmission timing generation circuit and supplying the delayed output pulse to the reception timing generation circuit, the reception timing generation circuit When the switch means sets the return state to the return means, synchronization is performed with the output of the delay circuit instead of the control of the frame synchronization control circuit, and
It is equipped with means for setting a test line pattern that can receive the transmission burst of the own station as is, and the delay time of the delay circuit is such that the transmission signal transmitted by the transmission timing signal generated by the transmission timing generation circuit is A time division multiple access communications device, characterized in that it is configured to generate a receive timing signal capable of receiving bursts appearing at the output of said demodulation circuit via means. 2. The time division multiple access communication device according to claim 1, wherein the folding means includes means for superimposing noise on the passing signal. 3. The time division multiple access communication device according to claim 1, wherein the test line pattern is stored in the transmission/reception control memory.