JPH0365573B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to a parallel multiplier that uses binary data as an operand, particularly a parallel multiplier based on a modified Booth's algorithm. (Insulated gate type)
It is used when realized with an integrated circuit. [Technical Background of the Invention] Conventionally, various methods have been proposed for realizing high-speed parallel multiplication of binary numbers. These methods are described in, for example, "Nikkei Electronics" 1978,
5, No. 29, P.76-89 and "High-speed calculation method for computers," translated by Horikoshi, Kindai Kagakusha, 1980, P.129
~213. Next, a conventional parallel multiplier using a modified Booth's algorithm, which is known as a method for increasing the speed of multiplication, will be described. Here, the modified Booth's algorithm itself is explained in detail in the above-mentioned document, so it will be omitted, and the basic cells used in the parallel multiplier that realizes the above-mentioned algorithm will be explained below. FIG. 4 shows one basic cell of a group of basic cells used in a parallel multiplier constructed based on the known modified quadratic Booth's algorithm. In this basic cell, 1 is the input terminal for data Xi of 1 bit of the multiplicand data X given corresponding to the bit position assigned to this basic cell, and 2 is the input terminal for data Xi- ₁ which is one bit lower than the data Xi. , 3 and 4 are input terminals for selection control signals X and 2X, 5 is a two-input AND gate whose two input terminals are connected to the input terminals 1 and 3, and 6 is the input terminal 2 and 4.
A two-input AND gate with two input terminals connected to the
7 is connected to each output terminal of the above AND gates 5 and 6.
8 is an input terminal for an inverted control signal INV; 9 is an exclusive OR gate having two input terminals connected to the output terminal of the OR gate 7 and the input terminal 8; , its output terminal is connected to the summand input terminal of the full adder (F・A) 10, and 11 and 12 correspond to the sum output of the full adder in the basic cells corresponding to the same digit in the previous stage. and input terminals for the carry output of the full adder in the basic cell corresponding to the lower digit of the previous stage, which are connected to the addend input terminal and the carry input terminal of the full adder 10, and 13 and 14 are This is an output terminal for the sum output and the carry output of the full adder 10. Here, two inputs 1 have an inversion function by the AND gates 5 and 6 and the OR gate 7.
An output selector is formed, and a selection control signal
When the selection control signal 2X goes to the "1" level, the input bit Xi is selected, and when the selection control signal 2X goes to the "1" level, the input bit Xi- ₁ is selected. Furthermore, when the inverted control signal INV is at the "1" level, the output of the selector is inverted and output, and the inverted control signal INV is output.
When INV is at the "0" level, the output of the selector is output as is. Note that the selection control signals X, 2X and the inverted control signal INV are provided by a decoder (not shown) that decodes the multiplier data y based on the following logical formula. Here, three consecutive digit data of the multiplier data are represented by y _2i+2 , y _2i+1 , and y _2i , and their inverted data are represented by _2i+2 , _2i+1 , and _2i . X=y _2i y _2i+1 2X= _2i+2・y _2i+1・y _2i +y _2i+2・_2i+1・_2i INV= _2i+2 However, the logical symbols ・ and + are exclusive ORs, respectively. , represents logical product and logical sum. [Problems with the Background Art] By the way, a parallel multiplier based on the second-order Booth's algorithm, which is constructed by arranging the basic cells in two dimensions, is simply constructed by arranging full adders in two dimensions. Compared to a parallel multiplier, the number of cell array stages and the number of used cells are halved, but the number of constituent transistors in each cell increases. Now, when a parallel multiplier is configured with all CMOS circuits suitable for realizing large-scale integrated circuits that are advantageous in terms of power consumption, input control circuit parts other than the full adder in the basic cell (control logic of the summand input) The number of transistors required for the circuit section is 18. That is, various systems have been proposed for the configuration of the exclusive OR circuit 9, but here, as shown in FIG. 15
and a two-input NOR gate 16, ten MOS transistors would be used. Furthermore, if two two-input AND gates and one two-input NOR gate are realized as the two-input one-output selector with one stage of composite gate 17 as shown in FIG. MOS transistors will be used. In this way, an increase in the number of transistors used in each cell not only increases the size of the multiplier and power consumption, but also increases the length of wiring between cells, which reduces the signal propagation speed. There are drawbacks that cause deterioration. Furthermore, since the number of transistors used in the control logic circuit section for the summand input in the basic cell is large, there is a drawback that the speed of the summand input of the full adder is reduced. [Object of the invention] The present invention has been made in view of the above circumstances, and
The number of MOS transistors used in the control logic circuit section of the summand input in the basic cell can be reduced, and the speed of the summand input of the full adder as a basic cell can be improved, as well as size reduction and power consumption reduction. The object of the present invention is to provide a parallel multiplier that can be made smaller in size, lower in power consumption, and faster in operation. [Summary of the Invention] That is, the parallel multiplier of the present invention is capable of processing digital data of multiplicand data corresponding to each basic cell.
Xi, its inverted data, and digit data one bit lower than these Xi- ₁ , its inverted data
By supplying Xi− ₁ , decoding the multiplier data based on a predetermined logical formula, and selectively supplying three selection control signals to each basic cell, each basic cell has 5 inputs and 1 output. The four data inputs and one input fixed at the "1" level or "0" level are selected by the selector by the selection control input and are set as the summand input of the full adder. It is characterized by the fact that Therefore, as the above 5 input 1 output selector
It can be realized with a small number of MOS transistors, about 10, and has advantages in terms of size, power consumption, and operating speed. [Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 1, 20... are two-dimensionally arranged basic cells, 21 to 26 are the normal rotation signal and its complementary signal (inversion signal) of each digit of binary multiplicand data X, which is an operand.
(Xi+ ₁ ,+ ₁ ),(Xi,),(Xi− ₁ , ₋₁
)...
The data line 27 to which . line 2
8, 29, . . . FIG. 2 shows one representative basic cell 20 of the parallel multiplier shown in FIG.
26 and selection control signal lines 28 ₁ to 28 ₃ are extracted and shown in detail. That is, in the basic cell 20, 31 to 36 are transmission gates (hereinafter abbreviated as TG) each consisting of an N-channel MOS transistor. TG31-34
Each drain is connected to the data lines 23 to 26 via corresponding input terminals 41 to 44,
The sources of TG31 and TG32 above are commonly connected.
Connected to the drain of TG35, TG33, 34
The respective sources of the TG35 are commonly connected to the drain of the TG35. 45 to 47 are input terminals connected to the three selection control signal lines 28 ₁ to 28 ₃ respectively, the input terminal 45 is connected to the gate of the TG 35, and the input terminal 46 is connected to the gate of the TG 36.
The input terminal 47 is connected to the gate of the TG3.
Connected to each gate of 1 and 33 and CMOS
It is connected to the input end of an inverter 37, and the output end of this inverter 37 is connected to each gate of the TGs 32 and 34. 38 and 39 are TGs consisting of P-channel MOS transistors, and TG3
The drain of TG 8 is connected to a fixed level "0" (ground potential), its gate is connected to the input terminal 45, its source is connected to the drain of TG 39, and the gate of TG 39 is connected to the input terminal 46. There is. And said TG35, 36, 39
The sources of are commonly connected to the summand input terminal Xin of the full adder 10. This full adder 1
The sum output of the full adder in the basic cell corresponding to the same digit in the previous stage basic cell string is input to the 0 summand input terminal Sin via the input terminal 11. Similarly, the carry input terminal Cin of the full adder 10 is
The carry output of the full adder in the basic cell corresponding to the lower digit in the previous basic cell string is input to the input terminal 12.
Enter via. Note that for a first-stage basic cell in which there is no previous-stage basic cell column, a fixed "0" level is given as an input from the previous stage. 1
3 and 14 are the sum output terminals of the full adder 10.
It is an output terminal connected to Sout and the carrier output terminal Cout. On the other hand, the selection control signal lines 28 ₁ to 28 ₃ include
The corresponding selection control signals S(X), S(2X), and S(M) are applied from the decoder (FIG. 1, 27). These selection control signals are obtained by decoding three consecutive digits y _2i+2 , y _2i+1 , y _2i of the multiplier data y based on the following logical formula,
The "1" level of each is active. S(X)=y _2i y _2i+1 S(2X)=y _2i・y _2i+1・y _2i+2 +y _2i・y _2i+1・y _2i+2 S(M)=y _2i+2 ( 1) Here, , , and + are exclusive OR, logical product, and logical sum symbols, respectively. Next, the operation of the basic cell 20 will be explained. As can be seen from the previous equation (1), the logic levels of the three selection control signals are determined depending on the combination of the three digits, and the logic level of the basic cell is determined depending on the combination of the logic levels of these three selection control signals. Any one of the five inputs is selected and becomes the summand input of the full adder 10. Details of the combinations in this case are shown in the table below.

〔Effect of the invention〕

As described above, according to the parallel multiplier of the present invention,
It is possible to reduce the number of MOS transistors used in the control logic circuit for the summand input in the basic cell, improve the speed of the summand input of the full adder in the basic cell, and reduce the size and power consumption. It becomes possible to reduce the Moreover, only three selection control signals are required, and the configuration of the multiplier decoder and the wiring of the selection control signal lines are simple. Therefore, the overall size can be reduced, power consumption can be reduced, and operation speed can be increased.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing a part of the parallel multiplier of the present invention, FIG. 2 is a circuit diagram showing an example of the basic cell in FIG. 1, and FIG. 3 is a modification of the basic cell in FIG. 2. 4 is a circuit diagram showing a basic cell used in a conventional parallel multiplier based on the modified quadratic Booth's algorithm. FIG. 5 is a circuit diagram showing the summand input control logic circuit in FIG. 1. FIG. 10...Full adder, 11, 12, 41-47...
...Input terminal, 13,14...Output terminal, 20,2
0'...Basic cell, 21-26...Data line, 2
7... Decoder, 28, 28 ₁ to 28 ₃ , 29...
Selection control signal lines, 31 to 36, 38, 39... Transmission gate, 37, 40...
CMOS inverter.

Claims (1)

[Claims] 1. A plurality of basic cells arranged two-dimensionally based on multiplicand data and multiplier data, digit data Xi of multiplicand data corresponding to each basic cell, its inverted data, and 1 from these. a data line that supplies lower bit digit data Xi− ₁ and its inverted data ₋₁ , respectively;
Decode the multiplier data based on a predetermined logical formula,
a multiplier decoder that selectively supplies a selection control signal to each basic cell via three selection control lines; The full adder selects one output from among the four data inputs from each data line and one input fixed at the "1" level or "0" level in accordance with the selection control signal input of the full adder. A parallel multiplier, wherein a predetermined sum output and a carry output from a preceding basic cell string are respectively inputted as an addend input and a carry input of the full adder. 2 The multiplier decoder converts the three consecutive digit data y _2i+2 , y _2i+1 , y _2i of the multiplier data y into the following logical formula y _2i y _2i+1 y _2i・y _2i+1・_2i+2 + _2i・_2i+1・y _{2i+2 2i+2} (However, is the exclusive OR symbol, ・is the conjunction symbol,
2. The parallel multiplier according to claim 1, wherein the parallel multiplier performs decoding based on a logical sum (+ is a logical sum symbol).