JPH0364039A - Evaluation of semiconductor substrate - Google Patents

Abstract

PURPOSE:To evaluate the uniformity of a semi-insulating substrate by measuring the density of impurity level in the vicinity of an interface between the active layer of an FET transistor and the semi-insulating substrate. CONSTITUTION:Shallow acceptor impurities in a semi-insulating substrate 1 are compensated by a deep hole trap type donnor level. An n-channel FET 2 is manufactured on the semi-insulating substrate 1. Electric potential of respective electrodes of source, gate, and drain 3, 4, and 5 is fixed and voltage of the 2nd electrode 7 is changed to negative. In such a case, the density of impurity level in the vicinity of an interface between the active layer of an FET transistor and the semi-insulating substrate is obtained by a drain current and a voltage applied to the 2nd electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor substrate evaluation method for measuring the density of levels contained in a semiconductor substrate.

[Conventional technology]

Semi-insulating substrates have high resistance (107Ω·Cl11 or more) and are suitable for high-speed circuits with little parasitic capacitance. However, since it can be obtained by compensating shallow impurities with deep impurities, field effect transistors (
The electrical characteristics of a FET (FET) are greatly influenced by the impurity density of the substrate via the homo-interface (n-1 interface) between its n-type channel and the semi-insulating substrate. Therefore, if the impurity density fluctuates within the substrate surface, the characteristics of the FET will vary, and when designing a high-density IC, it is necessary to take this variation in FET characteristics into account. This will slow down the process, and the advantage of using a semi-insulating substrate will be lost. Therefore, it is important to establish a manufacturing method that improves the uniformity of the substrate and a method for evaluating the same.

As mentioned above, semi-insulating substrates have high resistance, so the evaluation methods include the usual electrical measurement methods such as current-voltage measurement method, capacitance-voltage measurement method, and DLTS (Deep Level
Techniques such as the Transient 5 pectroscopy method are difficult to use. Conventional evaluation methods include a method in which carriers are generated in a substrate by optical excitation and the photoelectric groove is measured, a photoluminescence method, an infrared absorption method, and the like, which are not electrical methods.

On the other hand, in the 51-MOSFET, it is recognized that the drain current of the FET is modulated by the voltage of the second electrode via the FET and the substrate, as a so-called back gate effect. This is because the St substrate is a p-type substrate for an n-type channel FET, so all the negative voltage applied to the second electrode is applied to the depletion layer at the interface between the channel and the substrate, so-called pn
Since the junction is in a reverse bias state, the relationship between the drain current and the impurity density of the substrate and the applied voltage can be obtained. However, in an n-type channel FET fabricated on a semi-insulating substrate, the substrate itself has a high resistance, so the usual pn junction concept cannot be considered.

[Problem to be solved by the invention]

In conventional evaluation methods, the relationship between the characteristics of the field effect transistor and the characteristics of the substrate is unclear, as described above.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for evaluating a semiconductor substrate in which the relationship between the characteristics of a field effect transistor and the characteristics of a semiconductor substrate to be measured becomes clear.

[Means to solve the problem]

The method for evaluating a semi-insulating substrate of the present invention includes forming a field-effect transistor having an active layer of the same conductivity type as the type of carriers that easily trap holes or electrons on a semi-insulating substrate compensated with a deep level that easily traps holes or electrons. and a second electrode structure is formed on the active layer next to the field effect transistor or on the lower surface of the semi-insulating substrate with a semi-insulating substrate interposed as an insulator, and a second electrode structure is formed on the active layer. The drain current when the effect transistor is operated in a linear region is modulated by changing the voltage applied to the second electrode, and from the drain current and the voltage applied to the second electrode at that time, the field effect transistor is The semi-insulating substrate is evaluated by obtaining the density of impurity levels near the interface between the active layer and the semi-insulating substrate.

[Effect]

At least one FE, r', having an active layer of the same conductivity type as the type of carriers that easily trap holes or electrons is formed on a semi-insulating substrate compensated with a deep level that easily traps holes or electrons, and the FET A second electrode structure is formed on the active layer next to or on the lower surface of the substrate with a semi-insulating substrate as an insulator, and the drain current when operated in the FET@linear region is determined by the second electrode structure. For the voltage applied to
Since it is modulated by changes in the depletion layer at the interface between the active layer of the FET and the semi-insulating substrate, it becomes possible to obtain the density of impurity levels near the interface and evaluate the semi-insulating substrate.

〔Example〕

FIG. 1 shows a specific example of a device structure for implementing the method of the present invention.

First, a semi-insulating substrate 1 to be measured is prepared. In this semi-insulating substrate 1, shallow acceptor impurities are compensated by a hole trap type deep donor level. One n-channel FET 2 is fabricated on this semi-insulating substrate 1. 3 is a source electrode of this FET, 4 is a gate electrode, and 5 is a drain electrode. Next, a second electrode 6 is formed next to the FET 2 or a second electrode 7 is formed on the lower surface of the substrate 1. In addition, 8 is n
type channel layer.

In the device having the above structure, the source electrode 3.
Gate electrode 4. The potential of the drain electrode 5 is fixed, and the voltage of the second electrode 7 is changed to negative. FIG. 2 shows a calculated potential distribution along the cross-sectional line A-A in FIG. 1 at this time. The ordinate is the potential, and the abscissa is the distance from the n-channel 9 side to the second electrode 7 side. Curve ■～
■The channel potential is 20V, IOV, 5V, respectively.
2V.

The case of IV, 0.5V, and OV is shown. Almost all of the voltage applied in this way is applied to the channel side n- to the interface 10.
and the depletion layer is widening. In this carrier-depleted region, the deep level is a hole trap, so it captures almost 100% of the electrons, and the charge in that region is determined by the total amount of shallow acceptors. Therefore, in this case, the channel side n-i interface 10 may be considered to be a pn junction without consideration of deep level charging.

The above is the second electrode 7 formed on the lower surface of the semi-insulating substrate 1.
This is a case where the voltage of the second electrode 6 formed next to the FET 2 is changed to a negative value, a depletion layer similarly spreads at the channel side n-i interface 10, and the channel side n The interface IO can be considered as a pn junction in which deep level charging is not considered.

FIG. 3 shows the calculated dependence of the drain current on the second electrode voltage for the device structure shown in FIG. The ordinate shows the normalized drain current, and the abscissa shows the voltage at the second electrode.

The density of the deep level N7 is fixed as 2 x 1016 cm-', and the density of the shallow level Na is set as 5 x 1QI4~IXl01
It is changed to 6c+*-'. In this way, the density dependence of shallow levels clearly appears. Here, when the donor density of the n-type channel is set as N, the ratio of change in drain current to change in voltage of the second electrode is expressed as θ IゎθV2 . . . (1). Here, 1. is the drain current.

v2 is the voltage of the second electrode, q is the level charge, ε is the dielectric constant of the substrate 1, V b i is the diffusion potential of the n-i interface 10 on the n-channel side, Lw is the gate width of FET 2, and σ is the n-type The conductivity of the channel, E, represents the average electric field in the source-drain direction in the channel. By taking the reciprocal of the square of equation (1), it can be shown that if A is around 1 on the graph of 1/(θrn/θV2)2 and voltage v2, the following is given. For example, 1/(θre/
θVri! The graph of (2) and (2) is shown in Figure 4.

The ordinate indicates 1/(θ1./θV,)2, and the abscissa indicates the voltage V2 of the second electrode. 13 is a graph of equation (1), and 14 represents the results of a two-dimensional device simulator of the device shown in FIG. In this way, by using the slope of the analytical equation (1) where the drain current begins to be modulated by the second electrode voltage, the shallow impurity density can be determined with high accuracy.

In the above example, the case of hole trap was explained, but in the case of electron trap type deep level, hole is converted into electron,
The explanation is exactly the same if n is changed to p and the polarity of the electrode voltage is changed.

〔Effect of the invention〕

As described above, the method of the present invention enables evaluation that specifically links the density of shallow impurities in a semi-insulating substrate and the electrical characteristics of an FET.

[Brief explanation of drawings]

Figure 1 is a diagram showing the device structure for evaluating the substrate, Figures 2 and 3 are diagrams for explaining the present invention in detail, and Figure 4 is the analysis necessary to determine the density of shallow impurities. FIG. 2 is a diagram illustrating the method. l...Semi-insulating substrate 2...N-channel FET 3...Source electrode 4...Gate electrode 5...Drain electrode 6... Second electrode (attached next to the FET) 7... Second electrode (attached to the back side of the substrate) 8... N-type channel layer 9... N-channel 10... ... Channel side n-i interface 11 ... Second electrode side n-i interface 13 ... Analytical formula graph 14 ... Results of two-dimensional simulator of the device in Figure 1

Claims (1)

[Claims] (1) At least one field effect transistor having an active layer of the same conductivity type as the type of carriers that easily trap holes or electrons is formed on a semi-insulating substrate compensated with a deep level that easily traps holes or electrons, and A second electrode structure is formed on the active layer next to the field effect transistor or on the lower surface of the semi-insulating substrate via a semi-insulating substrate as an insulator, and the field-effect transistor is operated in a linear region. The drain current at that time is modulated by changing the voltage applied to the second electrode, and the drain current at that time and the second
A method for evaluating a semi-insulating substrate by obtaining the density of impurity levels near the interface between the active layer of the field effect transistor and the semi-insulating substrate from the voltage applied to the electrode of the field effect transistor.