JPH0363777A - Microcomputer device - Google Patents

Abstract

PURPOSE:To easily change, check, and correct logic specifications to efficiently perform development and improvement by using a PLD module and immediately changing peripheral logic specifications which the core of a microcomputer as the base while identifying them correspondingly to each block. CONSTITUTION:With respect to configuration of a microcomputer device, a PLD identification signal and a code, which sets the signal to numerical value corresponding to a PLD code to be discriminated by a switch, or a signal code are inputted, this code is decoded, and a write/erase signal controlled through a PLD select gate part 30 is transmitted to designated one of PLDs 33 to 36. At this time, each block in a PLD module 31 is picked up through a required pin from a PLD writer to write/erase the logic. The PLD module 31 is coupled to a microcomputer core part 4 as the base like a CPU, a ROM, or a RAM. Thus, simulation and debugging in the actual operation state are performed when the logic is changed in accordance with specifications, and the microcomputer device where specifications are easily changed is constituted.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is a microcomputer (hereinafter referred to as a microcomputer) that is composed of a CPU ROM-RAM Ilo and a logic circuit block connected therebetween, and whose specifications can be easily changed.
Regarding equipment, the logic circuit blocks in the PLD module are picked up according to changes in logic specifications, and the configuration is easy to rewrite and change, and microcontroller-related equipment,
It is applied to the development of LSI, and allows changes in logic specifications, depacking, and simulations to be easily performed.

[Conventional technology]

Conventional microcomputer equipped 5tHCPU, ROM, RAM,
I/l) G, the logic circuit section between them is an IC, LSI,
It is assembled on a substrate board using circuit elements. or,
In some cases, most of these circuit functions are created as a single-chip VLS1. Sometimes IC, LSl, V
The LSI is incorporated into the RC card. Therefore, changes in the program are usually handled by EAROM (ML rewritable ROM), but changes in the logical specifications cannot be handled.

When changing the logic circuit of the microcomputer function made up of VLSI and IC cards, it is necessary to create a new one. Currently, if logical changes are possible,
When a PLD is installed on a circuit board, the PLD package must be inserted into and removed from the socket and rewritten using a different pattern. Furthermore, when a plurality of PLDs are composed of chips, rewriting is difficult.

FIG. 2 is a block diagram showing the circuit functional configuration of a conventional microcomputer device. In Figure VC, (1) is CPtJ.

(21 is the system controller, (31 is the ROM,
+41 is RAM.

(6) Hada Pass, +81i Funtrol Bus, +7
11-j address bus, (8) is the I10 communication interface, (9) is the 110 peripheral interface, (lol is the interrupt extension, (Ill is the address bus from the CPU ill, and α21 is the interrupt signal line.

The block configuration in Figure 2 is basically to to1808
This is generally known as the operation of a 0-series microcomputer.

CPU +11 has 61 8-bit registers.
There are data registers, status registers, instruction registers and an accumulator. The 16-bit register includes a stack pointer and a program counter. In this case, the instruction H78ff is 1 to 3 bytes long. Addressing modes include direct, register, register indirect, and immediate. The second Og series has enhanced addressing modes such as index relative mode. External buses include a data bus (6), a control bus (6), and an address bus (7), which are used to interface with memory and input/output. It also has the function of 11+l extension αω. Furthermore, some devices have additional circuits such as a DMA transfer function, an AD converter, and a timer function.

The microcontrollers mentioned above are single-chip LSIs.

Even if it is made into an IC card and configured so that the program can be rewritten, it cannot respond to logical specification changes. In addition, for example, a system controller +21 using a PLD,
Multiple chips must be used to enable logic changes such as around I10. In those rewrites, each P
You have to insert and remove the LD pins and use another PLD writer. When these PLD chips are composed of a plurality of PLD chips, it is difficult to individually identify and rewrite and change them while they are set in a microcomputer device.

[Problem to be solved by the invention]

Conventional microcontroller devices are one-chip microcontrollers, boards,
When configured with an IC card etc., the system controller,
Interrupt, I10/i! Logic circuit parts such as edges are usually fixed and must be rebuilt if they are to be changed.

Each time you replace the chip mounted on the board for each package, or rewrite it if it is programmable,
Those packages must be inserted and removed individually.

When modularized with chips such as IC cards and HICs, multiple elements such as EPROMs and PLDs cannot be individually identified and erased or written to when set in a microcontroller. Therefore, it is difficult to immediately change the hardware logical specifications of conventional microcontrollers. These depacking and simulations had problems such as requiring a lot of time and labor.

The microcomputer device of the present invention has been developed in order to improve the above-mentioned problems, and includes a PLO identification signal, a write/erase control section consisting of a switch section (!), a decoder section, and a PLD select/gate section. The PLD module section is arbitrarily connected and configured, and for each PLD chip,
Select either the switch setting or signal code, and press PL.
By identifying the D symbol, logic can be written/erased to any block in the module immediately.

Conventionally, it has been difficult to arbitrarily select and write/erase multiple chips in a PLD module, but the present invention aims to make these points easier. be.

[Means to solve the problem]

The microcomputer device according to the present invention uses a PLD identification signal.

It has a write/erase control section consisting of a signal switch section, a decoder section, and a PLD select/gate section, and is designated by the symbol (
A means for coupling and controlling a plurality of PLD modules identified by a PLD identification symbol (or a number), a means for setting a switch corresponding to a PLD identification symbol, or a means for picking up a required PLD by either a signal code, A means of writing/erasing logic in any block, CPU,
A means is provided for combining ROM, RAM, and PLD modules and constructing a designated block while changing the logical specifications.

[Effect]

The construction of the microcomputer device according to the present invention involves setting the numerical value corresponding to the PLD symbol to be identified using the PLD identification signal and signal switch, or inputting a signal code, decoding the code, and passing the signal through the PLD select gate section. A write signal and an erase signal controlled by the PLD are transmitted to a designated PLD. At this time, each block in the PLD module is picked up from the PLD writer via necessary pins, and logic is written/erased. These PLD modules are combined with basic microcomputer core parts such as CPU, ROM, and RAM, and when the logic is changed according to specifications, simulation and debugging can be performed under actual operation conditions, making it easy to change specifications. A microcomputer device was constructed.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings. 1st
The figure is a block diagram showing the circuit configuration of a microcomputer device that is an embodiment of the present invention. Note that the diagram shows the data bus, @ is the control bus, address bus is the address bus, (goods) is the write signal, 4 is the erase signal, the pen is the PLD identification signal, □
□□ is the write/erase control section, (c) is the switch section, r
23 is a decoder section, - is a PLD select gate section, al
) is the PLD module part, (31 Hatake) is the connector part, the figure shows the PLD identification wiring extraction part, Mfl PLDO%e
n is PLDl, - is PLD2, - is PLD3, If)
, n , @ , al is the write signal line, (50 m), (
51m).

(52 Hatake), (53s) are erase signal lines, 0 power is pRoM
, (3!1 is CPtJ.

The handle is the RAM, the decoy is the microcomputer core, (40m)
are microcomputer core part i4Q and PLD module part OIJ
This is the connector part to which is connected.

Next, the operation will be explained. Once the PLD symbols that need to be changed are defined according to the logic specifications and the logic diagram data necessary for the change is created, the data is converted for PLD using the conventional method and stored as code in the memory section of the PLD writer (not shown). is stored in The data is transferred to the PLD between the switch sections.
When the number of PLD Q is specified and a separate PLD Q signal (To) is sent, the signal that becomes the switch "of1" is encoded in the decoder section, controls the gate of the PLO select gate section (G), and outputs the write signal ( 241, the erase signal (to) is selected, and the write signal line ω~0 and the erase signal (50m) to (53
m) are selected and coupled to their respective corresponding PLDs.

For example, if switch 001 is specified, PLDI is selected. At this time, logic-IF write data is sent to the data stored in the memory section of the PLD writer through each pin, and writing is performed through the input pins of PLDl in write mode.

Similarly, data is written to other PLDs as necessary.

In this way, necessary circuit blocks of the PLD module section 鵠υ are written. On the other hand, the CPU (38).

PROM□□□, RAMfi microcomputer book core part htn
But, through the connector part (40a), the PLD module part! 11 are connected.

At this time, the microcomputer's t source, clock, input signals, etc. are applied, and the necessary programs are stored in FROM□□□. Therefore, as soon as the writing to the PLD is completed, the microcomputer device is activated and the necessary functions of the microcomputer are activated to check whether the PLD is normal or not. At this time, if the logical operation is abnormal, find the abnormal PLD block, specify that part using the method described above,
Write in the same manner as described above.

As a result, when the logical specifications are changed, debugging can be performed while simulating the actual operation, and a microcomputer device whose specifications can be easily changed can be constructed.

As explained above, in this embodiment, write/erase II
11 Part (b) By combining the PLD module H and the microcomputer core part, the logic code data from the PLD writer is input, multiple PLD symbols are identified, and the logic of the necessary block is created. Writing/erasing can be performed correspondingly.

Among them, in the above embodiment, the PLD module (3υ is P
Although we have explained the case where only the logic part of the LD is included,
FROM, RAM, etc. can also be installed and expanded if necessary.

In addition, the microcomputer core part (a) and the PLD module f31
11-Although the case is shown in which they are made separately and connected to the connector part (40a), they may be assembled on the same board. Similarly, the case where the PLD module Q1) and the write/erase control unit □□□ are connected by connector 00 is shown, but between this connector part (3h) and the write/erase control unit □□□ You may also include a wiring bus. Furthermore, the write/erase control port except for the connector (31a) can also be incorporated into the PLD module rules.

〔Effect of the invention〕

As described above, according to the present invention, based on the core of the microcomputer, the peripheral logical specifications are identified and changed immediately in correspondence with each block, making it easy to change and check the logical specifications, and quickly. Since functions can be simulated and debugged, it is expected to improve the efficiency of development and improvement related to this.

[Brief explanation of drawings]

f! ! , FIG. 1 is a block diagram of a microcomputer device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional microcomputer device. Ql)...Data bus, □□□...Control bus, □□□...Address bus, Shaving...Write signal, (To)...Erase signal, (To)...PLD identification Signal, Q71...Writing/erase control unit, Co., Ltd....Switch unit, I...Decoder unit, Seki...PLD select gate unit, el)...PLD module, (31
m)... Connector part, Figure... PLD identification wiring extraction part, (35・PLDQ, PLDI, PL
D2. PLD3.1ll)~aS-...Write signal line, (5011)~(53m)...Erase signal line, target...
...FROM. (to)...CPU, ("+1 ・RAM, Q
l-...Microcomputer core section, (40a), (c)...
Connector part.

Claims (1)

[Claims] PLD identification signal, signal switch section, decoder section, PL
a write/erase control section consisting of a D select gate section;
PLD module parts made of multiple chips are arbitrarily combined, and corresponding to the identification name of the PLD chip, the identification name of the PLD chip is picked up either by switch settings or signal code, and written in accordance with the logic specifications. A microcomputer device is constructed by combining an erasable PLD module section with a CPU, ROM, and RAM, and changing logical specifications corresponding to each block.