JPH0363722A - Digital data processing circuit - Google Patents

Abstract

PURPOSE:To average the generation of a rounding error irrespective of a value of fraction data by adding a random noise generated by a multiple element M sequence, and executing a rounding processing of digital data, based on a result of this addition. CONSTITUTION:In input digital data DGIN of 16 bits, first of all, effective data DCIN1 of an 8-bit portion is inputted to a rounding processing circuit 2 from an MSB (most significant bit) to be brought to rounding, and fraction data DGIN2 consisting of an 8-bit portion being below the effective data DGIN1 is inputted to a fraction data processing circuit 3. To this fraction data processing circuit 3, in addition to the fraction data DGIN2, random noise data DRN consisting of, for instance, 3 bits outputted from a random noise generating circuit 4 is inputted. Subsequently, to the fraction data DIN2 of digital data, the random noise DRN generated by a multiple element M sequence is added, and based on a result of this addition, a rounding processing of the digital data is executed. In such a way, the generation of a rounding error can be averaged irrespective of the value of fraction data by a simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a digital data processing circuit, and is particularly suitable for application to circuits that perform rounding of digital data.

B. Summary of the Invention The present invention is such that, in a digital data processing circuit, random noise generated by a multi-dimensional M-sequence is added to fractional data of digital data, and rounding processing of the digital data is performed based on the addition result. By doing so, the occurrence of rounding errors can be averaged out regardless of the value of fractional data.

C. Prior Art Conventionally, in the digital signal processing circuit of a video tape recorder that handles digitized video signals,
For example, when controlling the level of 8-bit digital video data,
By multiplying by 8-bit level control data and rounding the 16-bit digital video data obtained as a result of this calculation, 8-bit digital video data that is allowed on the transmission path is obtained. ing.

In rounding of such digital data, first, the M of 16 bits of digital data to be rounded is
S B (most 51gn1ficant bit
), the 8 bits are taken as valid data, and the following 8 bits are taken as fractional data.

Subsequently, a value "1" is added to the MSB of the fractional data in the digital data, and then 8 bits of fractional data are discarded, thereby obtaining valid data as rounded digital data.

D Problems to be solved by the invention By the way, the rounding process of digital data as described above is
This corresponds to so-called rounding, in which the value rO05 is added to the decimal point of the decimal data, and then the integer part is used as data.

However, in the case of such rounding processing, the error from the true value of the data (hereinafter referred to as rounding error) is at most ±0.
5 (to be exact, the value -0.5 to +0.4999...
), and when the fraction below the decimal point is around 065, the rounding error becomes maximum and there is a problem that the distribution of the rounding error becomes biased.

To solve this problem, a digital data processing method has been proposed in which noise data of an appropriate bit length is added together with the MSB of fractional data, and then truncated (Japanese Patent Laid-Open No. 183627/1983). .

According to this method, a carry for valid data occurs with a probability according to the value of fractional data, so information on fractional data is statistically preserved.

However, in this method, a dither noise generation source or the like is used as the noise generation circuit, and there is an unavoidable problem that the circuit configuration becomes complicated and large.

The present invention has been made in consideration of the above points, and we would like to propose a digital data processing circuit that has a simple configuration and can average out rounding errors regardless of the value of fractional data when rounding digital data. That is.

E Means for Solving Problem E In order to solve this problem, in the present invention, the digital data Random noise DIR (DIN3, DIM
4) is added, and the carry data D0 is the result of the addition.
is added to the LSB of the valid data DGI141.

Random noise D□ (D□
, , DIN4) and rounding the digital data DC, , based on the addition result, the fractional data Dc, H.

The occurrence of rounding errors can be averaged out regardless of the value of .

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, reference numeral 1 indicates a digital data processing circuit according to the present invention as a whole, and by performing a predetermined rounding process on 16-bit input digital data DCIN, an output consisting of 8-bit valid data is obtained. Digital data DGoua is obtained.

That is, among the 16-bit input digital data DG, effective data DCINI of 8 bits starting from the MSB to be rounded is first input to the rounding processing circuit 2.

On the other hand, the fractional data DC consisting of 8 bits below the valid data DGIN1 of the input digital data DC, .
+Mt is input to the fractional data processing circuit 3.

This fraction data processing circuit 3 contains fraction data Dc+Nz
In addition, for example, 3-bit random noise data DIN output from the random noise generation circuit 4 is input.

Actually, the rounding processing circuit 2 and the fractional data processing circuit 3 have an adding circuit configuration. First, the fractional data processing circuit 3 adds 3 bits from the MSB of the fractional data DG+st and the random noise data D□, and the result is , carry information to 1
The carry data D0 expressed in bits is obtained and sent to the rounding processing circuit 2.

As a result, the rounding processing circuit 2 calculates the valid data DC, □Nori, SB (l
east 51gn1ficant bit) and add the carry data I) cm sent from the fractional data processing circuit 3, and the 8-bit data obtained in this way is rounded to produce output digital data consisting of valid data. It is configured to send out as DGout.

Here, the random noise generation circuit 4 has a Galois field (G
It is composed of a multidimensional M-sequence generation circuit that uses primitive polynomials on F (p) (GALOIS field)).

Note that in the Galois field G F (p), p is selected as a prime number, and the generated sequence values are 0, 1.2,...
..., p-1.

In this way, by selecting p as a prime number, the autocorrelation function of the sequence becomes 1 for integral multiples of the period f, and -1/f for other times, so that it has the properties of a so-called pseudo-noise sequence. There is.

Furthermore, in this case, the prime number p is expressed as the following formula p-2" + 1 (n is any integer)... (1
) or the following formula % formula % (2) The n-bit sequence value obtained as a result is added to the n-biwa 1 minute from the MSB of the fraction data DG□2.

In this way, the average of the series values (+! (or 1
) is approximately equal to the center value of the value expressed by n biwa 1 minute from the MSB of the fractional data DC, □, and thus the probability of occurrence of a carry in the fractional data processing circuit 3 is averaged. I can do it.

In this embodiment, the random noise generation circuit 4
As shown in the figure, it is a 7-element, 3-order M-sequence generation circuit where n is 3 and p is 7, and in reality it consists of four latch circuits 10.
13, three coefficient multiplication circuits 14 to 16 and two addition circuits 17 and 18, each of which performs an operation modulo 7, is a linear feedback shift register, for example, the following formula % formula % (3) is constructed to have as a primitive polynomial.

In this case, the synchronization f is expressed by the following formula (4), which is the average value A of the generated 3-bit series values 0 to 6.
v is the following formula% formula% (5), and by adding the value 1 to each of the series values 0 to 6, (
11 to 7 are sent as random noise data D 11H3, and the average value is 4.00125 (!=i4.o).

In this way, carry occurs when random noise data DIIN3 is added to the three MSB bits of fractional data DGINt as shown in the diagram of FIG.

That is, in the chart of FIG. 3, rlJ in the table represents the case where a carry occurs, and "0" represents the case where no carry occurs.

According to this, fractional data DG1. For the 3 bits from the MSB of , between the value "3" and the value "4", cases where a carry occurs and cases where a carry does not occur are symmetrical, and as a result, the overall probability of a carry occurring is 1/2. It can be seen that

Furthermore, the larger the value of the 3 bits starting from the MSB of the fractional data DC+mt, the higher the probability that a carry will occur, so statistically speaking, the error is reduced.

Incidentally, in the conventional rounding method described above, the left half of the table corresponds to "0" and the right half to "1", and the probability of a carry occurring is determined by the fractional data DCI.
N! It can be seen that the data is biased according to the value of 3 bits from the MSB.

Note that when the 3 bits from the MSB of the fractional data DGl141 are the value "7", the random noise data DIN3
A carry occurs regardless of the value of , and conversely, when the value is "O", a carry does not occur regardless of the value of the random noise data 5018m.

According to the above configuration, digital data DC,.

Fractional data DG1. l! 3 bits of random noise data D generated from the MSB of
□, and the carry data I)c is the result of this addition.
m is the digital data D CI N's effective data DC+
Add to LSB of s+ and output digital data DGou
By obtaining y, the fractional data DGl14
! It is possible to realize a digital data processing circuit 1 that can average out the occurrence of rounding errors regardless of the value of .

In the above-mentioned embodiment, a case has been described in which the random noise generation circuit 4 is configured with a 7-element, 3-order M-sequence generation circuit, but the present invention is not limited to this, and other multi-element M-sequence generation circuits may be used. You can do it like this.

Incidentally, for example, in Figure 4, n is 4 and p is 17.
This shows an original 4th-order M-sequence generation circuit, and is actually a linear combination of three latch circuits 20 to 22, two coefficient multiplier circuits 23, 24, and an adder circuit 25, each of which performs an operation modulo 17. It is a feedback shift register, and is configured to have, for example, the following formula (6) as a primitive polynomial.

In this case, the period f is expressed by the following formula % formula % (7), and the average value Ay of the generated 4-bit series values is the following formula % formula % (8) In this case, the series values are from 0 to 16, Using this as random noise data DRN4, fractional data DCIN! MS of
Add 4 bits from B.

As a result, in the case of series value “16”, fraction data DC+
If a carry occurs regardless of the value of 4 bits from the MSB of sz, and the series value is "O", M of fraction data DGINt
No carry occurs regardless of the value of 4 bits from SB.

Therefore, even if the input digital data DC,, is not input, there is a probability of 1/17 that the valid data DC,,
There is a risk that the value "1" will be added to the LSB of , and in order to effectively avoid this, the series value "16" is
5'' and the series value r□ are converted to the value ``1''.

In this case, the average value is calculated using the following formula: % Formula % (9) Further, in the above embodiment, the case where the rounding process is performed by the digital data processing circuit 1 alone is described, but instead of this, the same digital data processing system When performing multiple rounding processes, if the random noise generation circuit 4 is configured with multi-dimensional M-sequence generating circuits that have no correlation with each other, the digital data generated when configured with the same multi-dimensional M-sequence generating circuit can be reduced. It is possible to prevent unusual level increases and decreases.

Furthermore, in the above embodiment, input digital data DGIN is converted into valid data DG, □ and fractional data D.
We have described the case where calculations are processed separately into G + Ht,
The circuit configuration is not limited to this, but the input digital data DC,
, the random noise data D□ is digit-aligned and added to the portion corresponding to the fractional data DC+Nt, and then the fractional data DGINg portion is discarded to achieve the same effect as in the above-described embodiment.

H Effects of the Invention As described above, according to the present invention, random noise generated by a multi-dimensional M sequence is added to fractional data of digital data, and rounding of the digital data is performed based on the addition result. As a result, it is possible to realize a digital data processing circuit that can average rounding errors regardless of the value of fractional data with a simple configuration.

DGINt ""・° Fractional data SDI H D 183・
DRN4・・・Random noise data, DCI・
...Carry data.

Claims (1)

[Scope of claims] In a digital data processing circuit that performs rounding processing of valid data consisting of a predetermined number of bits starting from the MSB of digital data, rounding processing is performed to round off valid data consisting of a predetermined number of bits starting from the MSB of the digital data, , random noise generated from a multi-component M-sequence having a corresponding number of bits are added, and carry data resulting from the addition is added to the LSB of the valid data.