JPH0362939A - Testing method for semiconductor - Google Patents
Testing method for semiconductorInfo
- Publication number
- JPH0362939A JPH0362939A JP1198499A JP19849989A JPH0362939A JP H0362939 A JPH0362939 A JP H0362939A JP 1198499 A JP1198499 A JP 1198499A JP 19849989 A JP19849989 A JP 19849989A JP H0362939 A JPH0362939 A JP H0362939A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- input
- level
- inputted
- socket
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 230000035945 sensitivity Effects 0.000 claims abstract description 25
- 238000010998 test method Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 230000002238 attenuated effect Effects 0.000 abstract description 2
- 238000001514 detection method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 238000011156 evaluation Methods 0.000 description 4
- 238000012544 monitoring process Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、高周波化、小型パッケージ化にともない
ＩＣの真の感度を試験する試験方法は関するものである
。[Detailed Description of the Invention] [Industrial Application Field] This invention has been developed in accordance with the trend toward higher frequencies and smaller packages.
Test methods to test the true sensitivity of an IC are relevant.
〔従来の技術）
従来の半導体試験方法は第３図のようなフローで行われ
ている。[Prior Art] A conventional semiconductor testing method is carried out according to the flow shown in FIG.
実装感度データαＱでは、実使用とほぼ同等の評価基板
上に実装し、ＩＣの実装感度すなわち真の感度データを
採取し、ソケット感度データａυではＩＣソケットを使
用した場合での感度データを採取する。しかし、高周波
化が進むにつれて、ソケットのリード長により、容量の
影響を受けるため真のデータとソケットでのデータとで
改ためて相関データを採取する必要がある。又、これら
のデータ採取は同一システムで行うことも必要である。Mounting sensitivity data αQ collects the mounting sensitivity of the IC, that is, true sensitivity data, by mounting it on an evaluation board that is almost the same as that used in actual use, and socket sensitivity data aυ collects sensitivity data when using an IC socket. . However, as the frequency becomes higher, the capacity is affected by the lead length of the socket, so it is necessary to collect correlation data again between the true data and the data at the socket. It is also necessary to collect these data using the same system.
次に、テストソケット感度データ四では、実際に半導体
試験を行う場合のテスト治具での感度データ採取を行う
。次にテストハンドラー感度データ□□□では、半導体
試験を行う場合、自動化のためにハンドラーを用いるた
め、このハンドラーを用いた時での感度データが必要と
なってくる。テストソケット感度データ□□□、テスト
ハンドラー感度データσ１のシステムは同一とするが、
上記実装感度データｑｑとソケット感度データＱηと同
様な理由により相関データが必要となる。又、テストソ
ケット感度データ管と、ソケット感度データｏＤとでは
使用している半導体試験治具が通常は異なるため、改た
めて相関データが必要となり、又、実装感度データ（Ｉ
Ｇ 、ソケット感度データＣ！υの評価システムと、テ
ストソケット感度データ□□□、テストハンドラー感度
データ０の評価システムとが異なることも、相関データ
が必要となってくる。Next, in test socket sensitivity data 4, sensitivity data is collected using a test jig when actually conducting a semiconductor test. Next, regarding test handler sensitivity data □□□, when performing semiconductor testing, a handler is used for automation, so sensitivity data when using this handler is required. The systems for test socket sensitivity data □□□ and test handler sensitivity data σ1 are the same, but
Correlation data is required for the same reason as the mounting sensitivity data qq and the socket sensitivity data Qη. In addition, since the semiconductor test jigs used for test socket sensitivity data tube and socket sensitivity data oD are usually different, correlation data is required again, and mounting sensitivity data (I
G, socket sensitivity data C! Correlation data is also required because the evaluation system for υ is different from the evaluation system for test socket sensitivity data □□□ and test handler sensitivity data 0.
これらの相関データを基に、規格を設定し感度試験を実
施している。Based on these correlation data, standards are set and sensitivity tests are conducted.
（発明が解決しようとする課題〕
従来の半導体試験方法は以上の様なフローのため、絶対
値での試験が出来ず、何回も相関データを採取すること
が必要であった。(Problems to be Solved by the Invention) Due to the flow described above in the conventional semiconductor testing method, testing using absolute values was not possible, and it was necessary to collect correlation data many times.
この発明は、このような相関データの採取を行うことな
く、絶対値での試験を行えるようにしたものである。This invention makes it possible to perform tests using absolute values without collecting such correlation data.
〔課題を解決するための手段ｊ
この発明に係る半導体試験方法は、ＩＣ内部に、どの位
のレベルの信号が入力されているかを検出する検出回路
配置し、ソケットの影響が出る高周波帯域においても、
検出回路の信号レベルをモニターすることで、絶対値評
価が行えるようにしたものである。[Means for Solving the Problems j] The semiconductor testing method according to the present invention includes a detection circuit that detects the level of a signal being input inside an IC, and is capable of detecting signals even in a high frequency band where the influence of a socket occurs. ,
Absolute value evaluation can be performed by monitoring the signal level of the detection circuit.
この発明における信号レベル検出回路で、ＩＣの入力ビ
ンでの入力レベルを把握し、入力レベルを変化させ、絶
対値での感度テストを実施できる。With the signal level detection circuit according to the present invention, it is possible to grasp the input level at the input bin of an IC, change the input level, and perform a sensitivity test using an absolute value.
〔実施例」
第１図はこの発明の一実施例による半導体試験方法で使
用する治具のブロック図、第２図は第１図の治具の断面
図である。図において（１）は入力信号を伝える同軸ケ
ーブル、（３）はＩＣソケット、（２）はＩＣソケット
（３）のリード、（４）は基板、（５ＪはＩＣ。[Embodiment] FIG. 1 is a block diagram of a jig used in a semiconductor testing method according to an embodiment of the present invention, and FIG. 2 is a sectional view of the jig shown in FIG. 1. In the figure, (1) is the coaxial cable that transmits the input signal, (3) is the IC socket, (2) is the lead of the IC socket (3), (4) is the board, and (5J is the IC).
（６）はＩＣ入力ビン、（７）はモニタービン、（８）
は信号レベル検出回路、（９）はＩＣ回路である。次に
動作について説明する。入力信号は同軸ケーブル（１）
を経てリード（２）に入力される。リード（２）の長さ
によって容量の影響を受は信号が減衰して入力されるが
、この信号は、信号レベル検出回路（８）へ入力される
。ここで、信号レベル検出回路（８）の出力をモニター
しておき、ＩＣ（５）の能力に応じた入力レベルになる
ように入力レベルを変化させる。これにより、ＩＣ（５
）の内部にどのくらいの信号レベルが入力されているか
を把握でき真の感度で試験が行えることになる。(6) is IC input bin, (7) is monitor bin, (8)
(9) is a signal level detection circuit, and (9) is an IC circuit. Next, the operation will be explained. Input signal is coaxial cable (1)
is input to lead (2) through. Although the signal is attenuated due to the capacitance depending on the length of the lead (2), this signal is input to the signal level detection circuit (8). Here, the output of the signal level detection circuit (8) is monitored and the input level is changed so that the input level corresponds to the capability of the IC (5). This allows IC(5
), it is possible to ascertain the signal level input inside the sensor, allowing tests to be performed with true sensitivity.
以上のように、この発明によれば、実装時とソケット使
用時による相関データ採取、ソケット使用時とハンドラ
ー時による相関データ採取が省略でき、アッテネータ等
の装置故障の早期発見が可能となる。As described above, according to the present invention, it is possible to omit the collection of correlation data when mounting and when using a socket, and the collection of correlation data when using a socket and when using a handler, and it is possible to detect failures of devices such as attenuators at an early stage.
第１図はこの発明の一実施例による半導体試験方法で使
用する治具のブロック図、第２図は第１図の治具の断簡
図、第３図は従来の半導体試験方法のフロー図である。
図において（１）は同軸ケーブル、（２）はリード、（
３）はＩＣソケット、（４）は基板、（５）はＩ Ｃ、
（６）はＩＣ入力ビン、（７）はモニタービン、（８Ｈ
，を信号レベル検出回路、（９）はＩＣ回路である。
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a block diagram of a jig used in a semiconductor testing method according to an embodiment of the present invention, FIG. 2 is a simplified diagram of the jig shown in FIG. 1, and FIG. 3 is a flow diagram of a conventional semiconductor testing method. be. In the figure, (1) is the coaxial cable, (2) is the lead, (
3) is an IC socket, (4) is a board, (5) is an IC,
(6) is the IC input bin, (7) is the monitor bin, (8H
, are signal level detection circuits, and (9) is an IC circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
入力感度測定テストを行う試験方法において、ＩＣ内部
に入力信号レベルを検出する回路を内蔵し、絶対値にて
試験をできるようにしたことを特徴とする半導体試験方
法。In a test method for measuring the input sensitivity of prescaler ICs, which are becoming increasingly high-frequency and compact in size, the IC has a built-in circuit that detects the input signal level, making it possible to perform tests using absolute values. Semiconductor test method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1198499A JPH0362939A (en) | 1989-07-31 | 1989-07-31 | Testing method for semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1198499A JPH0362939A (en) | 1989-07-31 | 1989-07-31 | Testing method for semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0362939A true JPH0362939A (en) | 1991-03-19 |
Family
ID=16392147
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1198499A Pending JPH0362939A (en) | 1989-07-31 | 1989-07-31 | Testing method for semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0362939A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08185762A (en) * | 1994-12-28 | 1996-07-16 | Nec Yamagata Ltd | Pre-scaler ic test method and test probe card |
-
1989
- 1989-07-31 JP JP1198499A patent/JPH0362939A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08185762A (en) * | 1994-12-28 | 1996-07-16 | Nec Yamagata Ltd | Pre-scaler ic test method and test probe card |
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