JPH0362623A - Method and apparatus for encoding - Google Patents

Abstract

PURPOSE: To generate encoded data increasing linear recording density at the time of recording data on an optical medium by providing a negative single shot device and an OR gate. CONSTITUTION: A negative single shot device 310 outputs an output pulse at the time of receiving transition toward a negative direction. Then an input data string 302 is impressed to the device 310 and the first input 322 of the OR gate 320, the output of the device 310 is cormected with the second input 324 of the gate 320, and the gate 320 gives an output 340 with a high pulse level when one of the input levels is high-ordered. Then the device 310 is adjusted by a reset signal in fractional relation or phase shifting relation with a data clock. Consequently additional asymoetry is easily given to attain desired asymmetric encoding to increase the linear recording density of data recorded on an optical medium under a run-length limited data restricting condition.

Description

DETAILED DESCRIPTION OF THE INVENTION A. INDUSTRIAL APPLICATION The present invention relates to a method of encoding data, and more particularly, to a method of encoding data from a string of input data bits to a Run Length Limit.
ed-RL L ) coded data bits, i.e.
The present invention relates to a method and apparatus for generating coded data bits of limited length. More specifically, the present invention provides an optical data recording method that increases the linear recording density of data recorded on an optical medium under RLL encoding constraints. and its apparatus.

B. Prior Art Traditionally, the computer industry has relied heavily on various magnetic media, such as 8-inch or 5.25-inch diskettes, or hard disk plates, to store data or information. Ta. This magnetic media storage uses special magnetic recording elements, or magnetic recording heads, placed in close proximity to the magnetic media to generate a magnetic field through the surface of the magnetic media and to change the direction of the magnetic field in the magnetic media. It includes that. By using this technology,
The leading edge of a series of transitions from north to south poles in a medium, or S
Data is recorded using the leading edge of a series of transitions from pole to north pole.

Generally, magnetic media consists of a group of adjacent tracks that are further subdivided into patterns of information such as sectors and clusters.

The predetermined format of tracks per unit length on a magnetic medium and the number of magnetic transitions per track are:
Maintain synchronization control and reliability for storage systems that transfer data to and from magnetic media. To increase the linear recording density of data storage within a track, the number of magnetic transitions per track can be increased. This has been particularly successfully done in modern magnetic media with higher coercivity and higher reluctance across the track. Timing techniques have made it possible to provide transition spacing of one micron or less within a given track. However, magnetic media is subject to track-to-track spatial and density limitations. This limitation relates to track-to-track dimensions of a few microns or less, and the ability of the mechanisms for positioning the read/write devices used to exchange data between the magnetic media and the associated data system to be limited. It is caused by a lack of it.

Instead of magnetic devices, optical means for storing data have been developed. Optical recording systems are of interest because they can operate with higher addressing speeds, higher bandwidths, and smaller track-to-track dimensions of the recording media, as compared to magnetic media. There is.

These features are achieved by using microscopically focused light to create a device that is smaller than magnetic read/write devices.
This is possible because it can be optically manipulated using the method. Refraction limited laser (diffraction-11m1
ttedlaser) can be positioned across the data storage tracks with dimensions of 1 to 2 microns. However, optical systems pose new problems with linear recording density.

Now, for all read/write systems based on optical means, the minimum spot size of the light ray or beam on the medium must be considered. Since this spot size is much larger than the magnetic transition, the linear recording density of the medium is lower than for magnetic media. Typical refractive-limited lasers provide a convergence size or wasted area of 1 to 2 microns. Also, the optical system must provide additional (not enough) space in adjacent recording medium portions to resolve between adjacent II incision patterns created by the laser. Furthermore, because the technology for optically recording data is different from that of magnetic media, the dimensions of the minimum optical pattern are large.

In optical data storage, data is recorded by the effect created by a spot of a laser beam (writing beam) on the medium, ie, by changes in the surface of the medium. These surface variations include "bubbles," ridges, depressions, or holes to form a generally circular pattern with several topologies. Currently, optical data storage can be divided into two basic classes, one class of material removal type and the other class of state change type. With respect to the surface ablation type, the energy of the laser is used to actually remove material from the media, resulting in different surface reflectances or different surface transmittances. Various materials as thin metal films on substrates belong to this class. The state-change class technology is
Using laser energy to change the state, or properties, of an optical medium. This type includes transitions between amorphous and crystalline states, electro-optic transitions, or phase transitions of chemical state changes. of state change,
A more preferred method is one that utilizes electro-optical changes. By changing the electro-optical properties of the medium, the polarization of the incident laser "read beam" is shifted,
That is, it is rotated, and a change in polarization is detected by this rotation.

The region of change state can be thought of as a circular mark on the optical medium. By reducing the separation distance between marks to increase the number of marks per track, the linear recording density of optically stored data can be increased. However, this will reach the inherent limits of the species very quickly. The reason is the first
This can be explained using the optical data recording pattern shown in the figure.

For one mark, if a laser beam (reading beam) used for reading the mark is accurately aligned with the mark, it is possible to obtain an output with high resolution. High resolution output can be obtained when two adjacent marks arranged in series are well aligned with the reading beam. In FIG. 1, a series of adjacent optical marks 10.12 and 14 are positioned on an optical medium 20, with a "non-mark" area 16
and 18, respectively. Assume that the nominal size of the mark is 1 micron, which is the same as the size of a typical writing beam. first two marks 10 and 1
In case 2, the area separating the marks is slightly larger than 1 micron, and the reading beam is reflected or refracted by the non-marked area, as shown by dashed line 16. However, the two marks 12 and 14 shown in FIG. 1 are less than 1 micron apart, resulting in overlapping mark areas, as shown by dashed line 18. In such a case, in the detection system, the resolution between the marked area and the non-marked area will start to degrade, and the detection system will produce an erroneous detection result of detecting the non-marked area as a marked area. This will also result in a degradation of resolution between adjacent marks 12 and 14 by the reading system. This is similar to the degradation of resolution between magnetic bits in magnetic media.

Another factor that affects linear recording density in optical media is the choice of how the data is encoded. Pulse Width Modulation (PWM) Coding Method and Run Length
Limited (RLL) encoding method is the most commonly used technology developed for magnetic data storage. When these techniques are applied to optical media, in order to record data so as to reduce the number of discontinuous marks, the PWM encoding method changes the size of the mark and also changes the size of the mark before the mark whose size has changed. The edge and trailing edge are detected. All RLL encoding methods encode data into unique data bit strings to increase the data density of the channel and reduce error propagation of the data.

Although both these techniques have a number of advantages, they are oriented towards equalizing and averaging the minimum dimensions of marks and non-marks, thereby reducing the linear recording density in optical storage media. limit to the extent that This means that a significant portion of the optical medium remains unused, limiting linear recording density.

Therefore, the emergence of a method capable of reducing the unmarked area on average without significantly reducing the resolution of internal symbols means improving the linear recording density of data recorded on optical storage media. . It is also desired to reduce data error propagation and increase linear recording density.

PROBLEM SOLVED BY THE INVENTION It is an object of the present invention to generate coded data that increases linear recording density when recording data on optical media.

Another object of the invention is to provide a novel data encoding device for use on optical media.

Means for Solving the D1 Problem The present invention stores unconstrained data bits in M/N
A run length of the form (d%1,k1).

The present invention relates to a method for encoding according to the encoding constraints of LIMITED. Here, M is the input data
is the number of bits, N is the number of data bits generated in response to M data bits, and d is the number of binary 1s between adjacent binary ones in the encoded data string. and k is the maximum number of binary O's between adjacent binary 1's in the encoded data string. In the present invention, each binary 1 in the encoded data string is defined as (d,
1, k1) Change the constraint conditions. According to the invention, (d
, 1, k1) constraint sets the value (d1, k1) and the value (d2.1゜) in response to the neighboring coded binary 1.
1k). In the present invention, d1≠d2.

In this way, the amount of space allocated for a binary O coded between binary 1's varies so that within a PWM mark the coding has one coded value, and the adjacent mark The minimum number of O's coded values between is small. Therefore, the present invention provides a new constraint that allows the non-mark area to use an area smaller than the mark area, thereby significantly increasing the linear recording density of optically recorded data.

Asymmetric encoding constraints can be implemented on either unprocessed input data strings or data strings that have already been encoded using conventional RLL techniques.

In one embodiment of the invention, an apparatus is provided for generating asymmetrically encoded data from a previously symmetrically RLL encoded data string, the apparatus comprising an input data string and an input data string. , and the means for combining the pulses from the means for generating a single pulse, the at least one pulse being connected to the means for combining the pulses from the means for generating a single pulse, and generating a single pulse of variable width in response to a negative going transition in the input data string. using means. The device generates an input signal by a positive transition that is substantially in phase with a corresponding positive transition in the input data string and a magnitude based on the width of the pulse from the means for generating a single pulse. An output data string is generated having a negative transition delayed in the same phase as a corresponding negative transition in the data string.

The duration of the pulse may be a fractional magnitude relative to the duration of the data clock pulse. Also, the pulse width is
Variations can be made to provide multiple asymmetric coding constraints, or more than one pulse generation means and means for combining them can be used.

In another embodiment of the invention, a decoding apparatus is provided for generating asymmetric data from oil asymmetric run length limited encoded data. The decoding apparatus includes at least one means for generating a single pulse in response to a positive going transition in an input data string, and means for inverting the pulse generated by the single pulse means; and a combination means responsive to a given input data string. The apparatus generates a negative transition substantially in phase with a corresponding negative transition in the input data string and a magnitude based on the width of the pulse from the means for generating a single pulse. generates an output data string with phase-delayed positive going transitions.

In another embodiment of the invention, from an uncoded input data string of rate M/N, asymmetrically An encoding device is provided for generating an encoded data string. The encoding device uses shift register means for receiving and receiving input data strings and means for determining a predetermined order of states of the device, each state of the order being one of the M bits of the input. The zero-set decoding logic means causes the encoding of the data into a predetermined N-bit output data asymmetrically encoded according to the encoding constraints corresponding to the order of the M data sets in the shift register means. The zero selection means detects a current pattern of bits and provides an output of a set of N bits in response to both the current pattern and a current state defined by the state determining means. the next state in the order responsive to the set of N bits given by and the predetermined value of the current state d
%k, select the current state defined by the state means. The selection means is connected to the state means for shifting the state means to the next state.

In another embodiment of the invention, an apparatus is provided for generating an uncoded data string from an N/M rate asymmetric run length limited encoded data string. For this example, the run length limited encoded input data is M/N(d k ); (d2, k2
) Codified constraints 1ゝ 1 item is complied with. The decoding device includes shift register means for receiving and taking a predetermined number of data bits, the number being greater than N, in a coded input data string; look ahead means for detecting the N bitwise pattern, comparing the pattern with a predefined order of data bit patterns, and generating a signal representation of the predetermined bit pattern. I'm here. The set decoding logic means, in response to the generated signal from the look ahead means, determines the M output data bits for every N bits of the input data and the predetermined values of the encoding constraints, d and k. Based on the data bits present in the shift register y and the predetermined combinations of allowed data bit patterns.

E. Embodiments The present invention relates to a method and apparatus for increasing linear recording density when recording data on optical media. In accordance with the present invention, the data in the form of a serial string of data bits is subjected to an encoding process that forms an asymmetrical pattern between mutually adjacent marked and non-marked areas before being recorded on an optical medium. directed towards. It takes data that has already been run length limited (RLL) encoded and creates a new encoded constraint (c
a coding relationship that changes between two binary 1 data bits by receiving and receiving unencoded and unconstrained data. This is accomplished by the device encoding its data by using new encoding constraints that create . The novel encoding technique of the present invention frees up unused data recording areas along a given recording track by providing a physically asymmetrical relationship to the data recorded on the optical medium and encoded in the code. It is possible to optimize the reduction.

In the following detailed description of the invention, it is assumed that data not encoded according to the invention includes information in a conventional electronic format. The uncoded alphabet is a binary code containing "1" and rOJ. Uncoded data is
called "bit". Encoding means changing between a recording medium having one information format and a recording medium having the other information format, so the encoded information unit is ``character J (Character)''.
, but are sometimes referred to as "bits". In the prior art, coding and decoding are performed on units called "symbols" (or "blocks" or "words"). A symbol is a unit that contains one or more characters in an uncoded character string.

As previously mentioned, common read/write devices for optically recording data use a finely focused beam of light generated by a small laser source, such as a diode laser.

The laser is focused to a predetermined spot size on the optical medium that changes the reflective or refractive properties of the medium within the focused spot of the beam. Changes in the medium can take various forms, from material removal to phase transitions or state transitions.

Optical data storage systems suitable for the present invention use electro-optical effects to create local changes in the state of the medium. In this technique, a polarized laser writing beam is used to focus energy into a circular, focused spot on the medium to change the optical reflective properties of the medium. After the writing process, the reflected laser beam from the converging spot on the medium has had its polarization rotated.

The resulting pattern of changes in nature, or state changes, can be thought of as circular "marks" of rotated polarization.

Therefore, in the following description, the predicate "mark" means a pattern created on an optical medium by a recording or writing operation.

In order to obtain a high recording density of data, it is desirable to use small marks to record information using as small a convergent spot as possible. Optical data storage devices involve many factors, such as reading resolution, required power output, optical element aberrations, and laser characteristics, all of which combine to produce a final result. The size of the mark is determined. However, even with the output of a typical commercially available laser device, a refraction-limited laser, the size of the focused spot on the optical medium is on the order of 1 to 2 microns.

When reading or writing data, the optical data storage system uses mark edge detection methods or
Alternatively, a method for detecting the center position of the mark is adopted. Center position detection relies on detecting most of the effects caused by the read laser beam marks in the dark of the data clock cycle. The edge detection method detects a change in the value of the laser beam above or below a minimum threshold of predetermined values.

Among these approaches, two main methods are employed to encode data onto optical media. The first method is pulse-pulse modulation, or pulse position modulation (PPM
). In this technique, data is recorded and detected by defining "marks" with binary 1 data bits and "non-marks" with binary 0 data bits.

Alternatively to the above technique, data is recorded as binary 1 data bits by determining the leading or trailing edge of the mark, and the number of O bits present between the binary 1 bits. It is possible to record by making the mark larger or smaller depending on the situation. In this mode, the writing laser continues to pulse at regular mark intervals according to the timing of the writing circuit until the last marked area (length) is obtained. This continuous mode pulsing method is used to avoid beam blooming and energy deposition problems. This technique is commonly referred to as pulse width modulation (PWM).

In addition to physical modulation of mark position and size during string recording, there are modulation and encoding techniques that affect mark position or mark size. That is, for example, NRZI (Non-Return-to-Return) to sense the presence of a binary 1 digital state or a binary 0 digital state and incorporate this information into the pulse train.
There are several methods such as zero (I). Also, M F used to increase data channel density
M (Modified Freq
14 odulation), typically a run length limited encoding method.

Although these modulation methods and coding methods are well known, they are purposely described here in order to better understand the embodiments of the present invention.

PPM with data modulation method identifier (such as NRZI)
The input data recorded under several encoding methods using the recording method and the resulting mark shapes are shown in Figure 2a, and under several encoding methods using the PWM recording method. The input data recorded in the above and the resulting mark figure are shown in Figure 2. In FIG. 2, the minimum mark size is 1 micron (μ), and to obtain the necessary resolution, the minimum spacing between mark centers is 1.5 microns. From these values it is possible to calculate the speed of the clock and therefore the data density for each recording method. Note that in the PWM recording method, it is necessary to pay attention to improving the linear recording density of the optical medium.

Even though it is understood that the recording density is improved by the PWM recording method, there are still wasted spaces between the formed marks, and there is a need to reduce these wasted spaces. Physically speaking, it is desirable to develop a coding technique that can reduce the area between marks while leaving only the minimum necessary portion of the medium. Since the area within a recorded mark can be reduced by encoding and recording techniques, techniques such as those described above can significantly increase density.

As with magnetic materials, several encoding methods can be applied to the encoded data to improve data density and reliability. The most effective conventional encoding technique is Run Length Limited (R
LL) encoding technique whereby a given set of M data bits is encoded into a set of N bits that are encoded before being recorded. This means that the number of M-bit pairs encoded is generally less than the number of N-bit pairs in the resulting encoded string (i.e., there is no 1:1 correspondence). Even though
Significantly improve data rate and channel density.

An example of RLL encoding technology is U.S. Patent No. 3,589,899.
No. 4488142 and No. 4413251.

The commonly used RLL recording method requires a minimum number of (d) binary O's between two binary 1's and a maximum of (1, k1) binary 0's. . The value of is determined by timing requirements and clock/data synchronization. Therefore, a common code used in the embodiments described below is a 1/2 (2,7) code, which encodes one data bit into two coded bits. , and there are at least two binary O's between two adjacent binary 1's,
Furthermore, it is a code that has a constraint that the number of codes does not exceed seven. In the case of magnetic media encoding, a minimum O bit count is also used to ensure minimal resolution of the internal symbols.

However, even if the overall density of data in the channel transfer data bits to the optical medium is increased by RLL encoding, the linear recording density is only slightly improved. The above is true because (d, 1, k1) type RLL coding operates symmetrically.

That is, if at least one or two or more binary O bits are used in one mark area, then the same minimum and maximum values (d, 1, k1
) also applies to unmarked areas, so the above is true. Therefore, the minimum space for a mark is fixed at (d+1) times the size of the mark, resulting in a much larger space on average.

The invention monitors the encoded data string;
Then, a method is provided for changing the constraint conditions of d and k according to whether the detected binary 1 data bit is an odd numbered or an even numbered data bit.

In other words, this means that every other binary 1 data bit changes the encoding constraints.

By such a method, the encoding within the PWM mark has the value of the conventional encoding, and the minimum encoding value of the darkness of adjacent marks is small.
The amount of space between the binary 1s allocated for recording the 1's is varied. Therefore, on average, the unmarked area will be smaller than the marked area of the smallest data string, and the spacing between marks will be reduced. This will increase linear recording density.

Table 1, listed separately, is a chart showing constraints on RLL (2,7) encoding. The constraint conditions for this encoding are eight constraint states S. I have -87.

Each permitted transition from one constrained state to another is represented by an arrow marked with either an O or a 1. The order of labels encountered when traversing any path shown in Table 1 is determined by the (2,7) encoding constraint of RLL, i.e. the number of O's between two successive 1's is at least 2. , and a maximum of 7, which satisfies the encoding constraints. Conversely, all orders that satisfy the RLL (2,7) encoding constraint correspond to a particular path in Table 1.

The M/N rate coding system can be derived from a diagram of coding constraints. Such a coding device can be completely represented by a similar diagram in which each constraint state has exactly 2M arrows pointing outward. These arrows are labeled by N bit blocks of 0 bits and 1 bits, in the manner
The sequence created by concatenating labels encountered along any path of the encoding diagram is such that the run length constraint is satisfied.

Coding devices of the RLL (d, 1, k1) type, especially (2,
7) Circuits showing the constraint conditions and states of the type coding device are disclosed in U.S. Pat.
No. 142 or No. 4413251.

As previously mentioned, RLL (dS 1, k1) type encoding methods offer benefits for data density in magnetic media, but have disadvantages when implemented in optical media. . The reason is that this encoding method still requires that, for all input data, the space between two adjacent binary 1 data bits is treated the same as a binary 1 bit. It's in what you're doing. Therefore, this encoding technique
Although density is improved by utilizing both the leading and trailing edges of the mark, it follows that the unmarked areas between binary ones are subject to the same constraints as the marked areas. In other words, the same encoding constraints apply to all spaces between all adjacent binary 1s as for marks, so the same minimum and maximum space constraints apply to unmarked regions as for marked regions. This means that conditions apply. Physically speaking, this means that the minimum space between two marks has the same size as the minimum length of the marks.

This automatic condition of applying the same area constraint on all dark marks can be tolerated on magnetic media, but on optical media it wastes extra storage media space. The present invention improves on this technique by introducing new constraints for using unmarked areas to be smaller than marked areas, thereby significantly increasing the linear recording density of optically stored data.

The present invention provides a new code or a new coding method that departs from the linearly uniform, ie symmetric, coding method. Unlike conventional codes, this new asymmetric code is created by treating neighboring binary 1's differently depending on their position within the string of data bits.

The novel encoding method of the present invention creates different (6% 1, k1) type codes for separating between adjacent binary ones by varying between two values of d. It is something. This means that the first code is the value (dl,
k, ) and then the value (d2, k2). Although the new encoding constraints can be expressed in several ways, the expression below is easily modified and easily understood.

Conventional: M/N (d, 1, k1) Present invention: M/N (d1/d2, 1, k1) M/N (d
,k')-(d2,k2)1 M/N(d,k)-(dl,k2)1M/N(d%1,k1);(d2,k2)1 If we increase the maximum size of As a general rule, it is preferable that k1 = 2, since the encoding function introduces problems with clock synchronization and error propagation of data bits; smaller values of k will result in excessive truncation of the data string. , and requires more complex encoding/decoding to prevent loss of information. However, in some applications it is possible to increase the value of k.

asymmetric R with parameter values (3,7); (1,7)
Table 2 shows the LL coding constraints.

In the upper row of Table 2, constraint states 81-S7 force at least 3 O's and up to 7 O's to be placed between adjacent binary 1's. In the lower row of the same table, the constraint state 88-S, 5 has at least one O1 maximum 7
Forces 0's to be placed between adjacent 1's. The upper and lower columns are interconnected in such a way that a (3,7) constraint and a (1,7) constraint are applied to modify the run of O in response to a neighboring 1. The ordinal labels encountered when traversing any path through this diagram satisfy the asymmetric encoding constraint (3,7); (1,7) and the asymmetric encoding constraint (3,7); );(
Each order satisfying 1, 7) corresponds to a path in this diagram.

The diagram of the asymmetric coding constraints provides a starting point for constructing an M/N rate coding system. Such an encoder or coding device can be designed with a similar diagram in which each constraint state has exactly 2M arrows pointing outward. These arrows are ordered in the coding diagram in such a way that the order created by concatenating the labels encountered along the path satisfies the asymmetric run length constraint.
and M bit blocks of 1. An example of this type of encoding is shown in Figure 10 (215(1
, 9); (4,9) code) and Figure 13 (4
15(1,11); for (0,10) code) are shown in table form.

This novel method of RLL encoding is useful for recording data on optical media following proper initialization of the encoding system. Restraint state S.

The binary 1 data bit corresponding to the incoming edge is
(The binary 1 bit is an example given for simplicity; the data is, of course, the binary 0 bit.) (can be started). A binary 1 bit is written to the media as the leading edge of the mark. The number of bits in O before the next binary 1 bit appears is 3 in this example.

During this time, the laser used in the writing device generates pulses in succession to create a series of marks (actually a continuous mark). When the next encoded binary 1 bit is encountered, the constraint state S. , S7 to 88, the laser writes a binary 1 as the end of the mark using the trailing edge of the mark to represent a binary 1. Restraint state 89~S1
．． When the encoding O corresponding to a transition to is encountered, no mark is written. The number of these O's is restricted to 1 to 7. At this point, the area on the medium that is being written is between the marks, so the minimum space is covered smaller until the next encoded binary 1 is encountered and the next mark begins. Ru.

In practical systems, the above means that the minimum space for areas where no marks are recorded is on average smaller than the marked areas, and the content of the information represented by the code remains unchanged. It means that. Therefore, the symmetric RLL (2,7) code is (1,7)
;(3,7) or (3,7);(1,7) (according to the position where the first state was set) by the average linear recording density.

FIG. 2C shows the results of applying asymmetric constraints using two coding methods.

In this figure, it is important to note that the recording density is increasing. The present invention also provides d, 1, k1)
If a code based on the order of (dt/d2, 1, k1) is converted to be implemented as a (d, k code) It is based on the discovery that higher densities can be achieved. The predicate "transformation" does not imply a simple transformation of conventionally encoded data, although this can be done in a simple embodiment.

As previously mentioned, conventional approaches to recording data on optical media use symmetrical encoding methods to increase density and control data error propagation. To create asymmetric RLL encoded data, the encoding method of the present invention can be implemented in an apparatus for further encoding conventional RLL encoded data. A circuit for carrying out the method of the invention is shown in schematic diagram 2 of FIG.

In FIG. 3a, encoding device 300 is single shot, ie, includes single shot electronics 310 and an OR gate 320. In FIG. The input data string 302 is a data string encoded under an arbitrary (d, 1, k1) constraint, which may be state dependent or state independent. There may be. String 302 is described in U.S. Pat. No. 3, discussed above.
Any conventional RLL such as that described in No. 689899
is provided by a coding device and represents a series of pulses, or a series of pulse transitions. For purposes of explanation, assume that the data has symmetric RLL (2,7) coding.

Data is input to single shot device 310, which is an electronic device or circuit configured to provide an output pulse when undergoing a negative going transition. This negative going transition occurs whenever the value of data string 302 transitions from a binary 1 to a binary 0 in a PWM mark column. One example of a single shot device 310 is a monostable multi-bibreak, which is widely known in the electronics arts. When such a device receives an input, it outputs a pulse of constant width with either a negative-going transition or a positive-going transition, depending on how the device is configured. . The length of the pulse, or pulse width, can be selected to match the clock period of the data, or any other desired period. This period can be achieved by using resistive and capacitive elements within the multivibrator circuit to set a specific RC time constant that determines the reset timing and pulse duration. A retriggerable multivibrator can also be used so that a control signal, such as from a data clock, can be stretched to a pulse width beyond the RC cutoff time.

Another variation is to use a monostable multivibrator that is resettable by using a reset or wake-up pulse provided by signal source 330 that is a data clock signal from other readily available circuitry. You can.

This circuit allows the end of the pulse width to be controlled by a control source independently of the multivibrator circuit. Therefore, new pulse widths (encoding constraints) can be created without directly changing the RC timing elements. In addition, single shot device 31
In order to control the zero reset period, or retrigger period, to the same period as the desired pulse width, experts in this field:
Other devices such as logic gates can be easily substituted.

At the same time that input data 302 is input to single shot device 310, the input data is input to OR gate 32.
0 is applied to the first input 322. The output from single shock I-310 is connected to a second input 324 of OR gate 820. OR GATE 320 is
If either input level is high, it will provide an output 340 with a high pulse level. Therefore, when writing a mark on an optical medium, the RLL-encoded data existing in the period between two adjacent binary ones is
As long as it has a high pulse level, the level of output 340 will be high.

As soon as the mark ends, the trailing edge of the current data pulse triggers the output from single shot device 310. When the level of data 302 is low, the output from single shot device 310 is output from OR gate 320.
provides a high output level to input 324 of , and OR gate 320 provides a continuous high output 340 until the single shot pulse falls. This situation is illustrated in Figure 3b, in which the data string is shown on line (a), the output of the single shot device 310 is shown on line (b), and the data string is shown on line (c). At the top, the output 320 of the OR gate is shown.

After single shot device 310 resets, single shot 310 has no effect on the length of the output pulse of OR gate 820 until the next negative going transition is provided.

In this way, for symmetrical codes, the previously given coded signal is converted into a single data string that is moved from the coded data string (non-marks) to the neighboring part (marks). - Since it has bit 0, any one area has at least a count of two or more binary O's. This achieves the desired asymmetrical encoding. Thus, symmetrically coded input data with a coding constraint of (2,7) is modified to have a coding constraint of (3,8); (1,6). Depending on the manner in which the single shot device 310 is triggered, the resulting output encoding constraints also have different maximum values.

the width of the output pulse from the single shot device 310;
That is, pulse lengths are shown assuming that they are equal to one data clock pulse period for clarity. However, this is not necessary, and an important requirement of the present invention is that additional asymmetries can be easily added and that odd or fractional asymmetries are
This is achieved by adjusting the pulse width of single shot device 310.

Single shot device 3 for additional asymmetry
The pulse width given by 10 can be adjusted by having the pulse width exceed one data clock period. By stretching the pulse width to the width of several data clock pulses, additional O
data bits are shifted into or out of the portion of data string 340. A less advanced circuit would be to add one or more additional single shot devices and an additional OR gate in series with output 340. This circuit also produces the same timing relationships and pulsing as previously described, and produces additional asymmetric shifts in the coded data.

Adjusting the single-shot device 310 by having the single-shot device 310 have a pulse width shorter than the data clock period (by adjusting the RC time constant) to provide a fractional asymmetry; Alternatively, it can be adjusted by resetting the single shot device 310 with a reset signal source 330 that has a fractional or phase-shifted relationship to the data clock. In other words, signal source 330 does not provide control pulses with the same pulse width as the data clock pulses. To compare the pulse widths, note that the standard clock pulse width is the same as the width of the data pulse shown on line (d) and the phase-offset or phase-shifted line ( e)
The width of the reset pulse above is also the same as that of the third b.
It is shown in the figure.

If the single shot device 310 were reset using the control pulse shown on line (e) of FIG. 3b, the output pulse in response to a negative going transition in the input data string would be: Shown as an output pulse on line (f).

The output pulse on line (f) is a narrower pulse than the previous output pulse shown on line (c). Therefore,
Output pulse 340 has a fractional data bit value, a region of low level compressed by the fractional value, and a high pulse level stretched only by non-marks. This is illustrated by the pulse pattern on line (g) of Figure 3b for the same data string input on line (a). As a result, (2/2.71
/) − (11/61/2) coded constraint 2
It becomes possible to achieve a coding method with 21 conditions. This makes it possible to modify RLL encoded data to area density limitations imposed by the optical medium or read/write system, as opposed to being limited to specific data encoding constraints. This means a high degree of flexibility.

The encoded data 340 is transferred along a data channel to a suitable writing device for recording onto optical media. At this point, the encoded data
The channels are used to modulate or control the laser's writing beam focused onto the optical medium. Modulation of the laser beam with the coded data produces a change in the energy applied onto the optical recording medium in response to a change in the coded data pulse. In other words, a low level pulse train will cause the laser to produce a low energy level output, and a high level pulse train will cause the laser to produce a low energy level output.
Causes the laser to generate a high energy level output.

In this case, a high energy level means an energy level above a predetermined threshold that causes a change in the recording medium.

High levels of laser power create a pattern of marks on the recording medium by changing its physical properties, as explained above. Typical lasers are usually pulsed laser sources, so modulation with data is It is usually an on/off type.

When data stored on optical media is accessed,
A reading beam of a laser scans the surface of the optical medium to detect local changes in the material properties of the medium. As already explained, this is what is known as a change in the polarization of the laser light caused by reflection of the medium in the mark area. The rotation of the polarization is detected in order to modulate the voltage source, or pulse source, to generate a pulse train with a predetermined voltage level corresponding to the mark and the non-mark low voltage level, i.e. the output without a pulse train. and used. These pulses are transferred over the data channel as a string of coded data bits to be detected.

To decode the data recorded by the encoder or coding device 300 of FIG. 3a,
A decoding circuit or decoder as shown in Figure 4a is used. In Figure 4a, a decoder 400 receives encoded data 402 from a read detection circuit. Coded data 402 is serially provided to a single shot device 410. The pulse level pattern as an example of the data 402 is shown in FIG. 4b (a).
is shown. A single shot device 410, such as single shot device 310, can include a device known as a monostable multivibrator. Single shot device 410 is configured to output a pulse when a positive transition is detected or taken. encoded data string 40
Single shot device 410 generates a pulse whenever a 2 transitions to a high level, ie, a binary 1 bit, state. Therefore, single shot device 410
generates a pulse when the leading edge of the marked area is input.

At the same time that input data 402 is provided to single shot device 410, the input data is applied to AND gate 420.
is also applied to the first input 422 of.

Single shot device 410 is inverted using inverter 412 and its output is applied to a second input 424 of AND gate 420. The resulting output 440 from AND gate 420 is at a positive pulse level if both levels of its inputs are positive. Therefore, if the RLL encoded input data string is at a positive level and the single shot device is not pulsing, the output level 440 will be high.

When single shot device 410 detects a positive going transition in the data string, it
) generates the output pulse shown in

The output of device 410 is connected to input 42 via inverter 412.
4 and give a low level signal to AND gate 44.
0 drops to low. This situation is illustrated in Figure 4b, in which the encoded data string 402 is shown on line (a), the output of the inverter 412 is shown on line (c), and the - The output of gate 420 is shown on line (d). In this way, an already coded signal with an asymmetric coding constraint can be decoded from a portion of the code data string (mark) such that its regions have the same minimum count of O. It has a single data bit O that is moved to an adjacent part (non-marked).

This sets the symmetry of the original code before the next encoding is done. Therefore, an input data string with a (3,8)-(1,6) encoding constraint is currently
(2, 7) Has encoded constraints.

As with encoding device 300, the pulse width, or timing, of single shot device 410 is typically
chosen to correspond with the data clock pulse.

However, as previously mentioned, the pulse width may be varied or the reset signal source 430 may provide a fractional reset or a phase shift reset compared to the data clock. This translates to (2/2.71/2) - (1/2.61/2) to decoder 1 400 as needed.
Incorporate fractional encoding/decoding methods such as This is shown in lines (e) and (f) of Figure 4b.

An advantage of the encoder and decoder embodiments described above is that they are fully compatible with conventional read/write circuits and encoding methods for recording data on optical media. That's true. The single shot device includes a data edge detection device that can be adjusted to the required operation according to the present invention;
It already exists as part of a read/write deskew device or similar device. In this case, conventional circuitry can be retroactively adjusted to implement the method of the invention and new asymmetric encoding constraints can be achieved.

In FIG. 5, a coding circuit according to another embodiment of the invention is shown. In FIG. 5, the data asymmetry encoding device 500 converts the 1/2 rate encoded signal of the "matrix" input data in the input data string 502 into (1,6); (3,8) is configured to asymmetrically encode data using encoding constraints.

In the encoding device 500, the data string 50
2 is provided to a 3-bit shift register 504.

An external clock source (not shown) provided by a system oscillator typically provided in conjunction with the optical media read/write circuit clocks the divider 508, which clocks the shift register 504 and the divider 508. Clock signal 510 used for other elements of encoding device 500
give.

When the data string input 502 is shifted in the 3-bit shift register 504, the corresponding register output for the first three data bits is the register output Q.
Q and Ql.

3.2 These outputs are input to two input terminals of the counter 512. The illustrated counter 512 is a 4-bit digital counter, with only two bits being used in this embodiment. The Q3 output, representing the first data bit shifted in register 504, is connected to the first input terminal (B) of counter 512, while the second bit (Q2) and the third data bit are connected to the first input terminal (B) of counter 512.
The bit output components are combined through NOR gates 514 and 515 and connected to input terminal A of counter 512. These inputs to the counter cause it to produce high or low signal levels at its output terminals Q- and QB. The outputs of Q and Q are connected to combinatorial logic B 520, where the output of counter 512 determines where to partition the input data and which data bits are assigned to a given data string. used to determine whether an activity should be performed in a given partition. This partitioning operation is based on the input data
The pattern of bits is partitioned into predetermined sets of 1/2 I note output bits. This provides a unique set of data string prefixes that can be encoded later.

The coded output for the partitioned input is as follows.

Input data Output data 10 0100 11 1000 000 000100 010 100100 011 0010000 0010 00100100 0011 00001000 The inputs of inputs B and A are 2.3 or 4 bit sections, respectively, with OO for 4 bits and 01 for 3 bits. For use, Then, it is decided that 10 is for 2 bits.

The values of B and A are determined by the pool expression.

B=Q3 Once the logic circuitry within encoder 500 determines the partition pattern, the first two data bits in shift register 504 are It is operated.

The outputs of these gates are coded data bits with a ratio of two output bits for each input data bit to OR gate 532 and AND gate 5.
34. AND gate 534 clocks circuit clock 51 such that the output of gate 528 is output first, and then the output of AND gate 534 is output.
Timed by 0. As a result, and gate 52
The output of 8 is the most significant bit (MSB), the two bit data string 53 assigned to the first input data bit from data string 502.
is the first number of 8, and the combinational logic section 520 is
The least significant bit (LSB) of encoded data string 538 assigned to the first input bit from data string 502 is output.

Next, as in the case of the encoding device 300, the data is
input to single shot device 544 and OR gate 546 resulting in asymmetric encoded data.
Output string 550.

A flip-flop 540 is also preferably used to provide the data signal 538 with a sharp-rising, convenient pulse before being input to the monostable multivibrator 544.

The decoder circuit of FIG. 6 can be used to decode the asymmetric encoded data string 550 when the data string is later read from an optical medium. In FIG. 6, a decoder 60
0 is a single shot device 604, an inverter 60
6 and an AND gate 608, the coded data string 602 is transferred to two 4-bit shift registers 81Qa and 61 by a clock source 612.
Input to 0b. Clock source 612 is face-locked to the encoded data clock and
To be the same as the initial coding rate, it operates twice as fast as the desired data output clock, which now has a 2/1 decoding rate. shift register 6
The output from 10 is provided to a combinational logic circuit 620. Combinational logic circuit 620 includes four AND gates 622
．． 624, 626 and 628 and Noah Gate 630.

The specific matching of register outputs to these gates is predetermined by the pooling expression applied to the data to achieve the desired encoding function.

Such a combinatorial method is described in U.S. Pat. No. 44,881.
4.2. Also, the Adler (R
oyAcller)'s "Algorithm for sliding block codes and application of symbolic mechanics to information theory" (
Algorithms for Sljding Bl
ock Codes, AnApplication
of Symbolic Dynamics t.

The document entitled Information Theory discusses theoretical considerations and methods for creating encoding and decoding tables and logic for symmetric (2,7) RLL codes.

Therefore, combinational logic 620 performs the actual decoding (
decryption). However, in the case of decoder 600, the data bits must decode only a valid set of data bits. This is accomplished by having AND gate 640 detect the register output for the data sync mark pattern.

Such synchronization patterns are known in the field of data decoding.

The output of AND gate 640 causes the output of NAND gate 642 to drop, causing flip-flop 644 to change state. This signals the start of the decode cycle and causes flip-flop 646 to strobe register 610 to [(ffi).

Although the embodiments described above can easily implement asymmetric coding constraints for conventional RLL circuits,
This gives a larger maximum value and a larger minimum value (ie 1≠to 2) for O bits in one region. As already mentioned, increasing this maximum value is not always necessary or always acceptable in data processing systems, so the asymmetric code of the present invention makes it possible for many applications to must be executed using one constraint of M/N (d k ) - (d2, k2) in 2.

An embodiment using a 1=to2 asymmetric encoding constraint on the data string is shown in FIG. 7 for recording data on optical media.

Figure 7 shows that the ``matrix'' data is accepted and the NRZ
Coding device 700 for coding data using the 215(1,9)-(4,9) coding constraint method in I
It shows. As mentioned above, NRZI applies to the level pattern of the data string being used and does not change unless it returns with a binary 0 data bit and does not change with a binary 1 data bit).
And the 215 rate means that the two input data bits are 5
coded output data bits. For this example, dl-d2
It should be noted that the =3 constraint is used to illustrate that the asymmetry can be set at various levels and is not fixed by the single shot device described above.

Encoder 700 receives "matrix" data 702 and applies the data string to the D1 gate of a two-bit D-type shift register 704, which serially shifts the data string. A clock signal 706, maintained at approximately five times the clock speed, is applied to encoding device 700. This is done to ensure proper partitioning and synchronization of the data. clock signal 706
is divided into five parts using dividing means 708 to provide a clock signal for the two-bit register 704, so that the bit register 704 operates on that clock signal at the clock speed. At the same time, the clock signal of the register is further divided into two parts by a dividing means 710 and a 10-bit status register 712, as explained below.
used for timing. In addition, other dividing means 71
4 divides the high power clock signal 706 into two and provides a clock input to a 5-bit shift register 724.

Divider 714 clocks each shifted two bits through shift register 704 into output register 724 at a rate of five bits. This produces a 215 data encoding rate specified in this code. Since the 10-bit state register 712 changes state every two input bits, it must therefore be further halved by the divider 710.

The data is shifted through shift register 704 and
appears at its output terminals Q and Q2, and the outputs of shift register Q and Q2 are applied to decode logic 716. Since Q2 represents the leading bit in a 2-bit data string such as 10, 01 or 11, the Q2 output is high for all leading bits of binary 1s, and the leading bit is O. Also high for all data bit pairs. Therefore, these two lines are combined in the set decode logic circuit 720.
It can be used for this distinction.

Decode logic 716 includes simple combinatorial logic circuits well known in the field of electronic circuits, such as four AND gates 718 shown in FIG. Decode 00%01
．． For input data pairs 10 and 11, a predetermined high output signal is generated. These data pairs are used to determine the encoding to encode two data bits into five bits. However, the functionality of decode logic 716 may be included in set decode logic 720.

This particular coding device is state sensitive in the sense that each coding operation occurs by a configured circuit in a predetermined specific state, and the next allowed coding is dependent on the previous state. It is a dependent coding device.

The data is encoded according to the encoding table shown in FIG. The table of FIG. 10 includes predefined states A through J that are set into 10-bit register 712 by a series of AND gates, OR gates, and flip-flops well known to those skilled in the art. The first state is chosen as state A and must be the initial state chosen for encoding.

After the state is determined by register 712, the next state is determined by go to 5tate decoder 730. Go-to state decoder 7
30 examines the current state used for encoding and the current data being encoded.

This is shown in the go-to state decoder 730 of FIG. 7a as inputs A through J and 1 through OO. Referring to FIG. 10, this encoding method constrains the 10-bit state register 712 to change to a particular new state depending on the input data bit currently being encoded and the previous state. do. Go-to state decoder 730 uses a series of state setting outputs connected to 10-bit state register 712 to change the current state of state register 712 to a new value subject to encoding constraints.

Set decoding logic device i! 720 includes encoding logic 71 to determine the allowed patterns of output data.
6 and the current status input from the 10-bit status register 712.
Code the input child from 04. For a given state and two of the six types of input data bit patterns, a special bit pattern is
” to 5 outputs 111 named “Group 5”
722.

Referring to the table in FIG. 10, the functions of the decoder 700 and the set decoding logic circuit are as follows:
This can be explained by the pool expression "encoding of tuple decoding logic".

After understanding these expressions, asymmetric (1,9) (4
, 9) Coding Constraints, An example of the coding process is described below.

Data string data string input 101001111
1 is input to the encoding device 700 of FIG. 7a starting at t=Q, when the initial state is set to A, and all registers are returned to their respective determined initial states. shall be taken as a thing. These returns can be performed by a signal to the write status line 732 of the register. The pattern of 2-bit input data generated by register 704 is shown at the top of FIG.

The first two bits 10 produce an output in "set 1" of 5-bit register 720 based on the following operations. That is, since register 712 is in state rAJ and the input is 10, a binary 1, ie, a high level signal, is generated in "set 1" of register 720 according to the table of FIG. 10 and the expression of set 1. . The output of "Group 2" is
Since register 712 is not in state 11 or state J,
It is binary O. The output of “group 3” is the register 712
Since it is not in the H or G state, it is a binary O. The output of "set 4" is 0 because the input is 10, and "
The output of set 5 is 0 because register 712 is not in state E or F. Therefore, to generate the output of the encoding device 700, the data bit pattern 000
01 is stored in 5-bit register 724. This is shown in the second line of FIG. It should be noted that the last data bits (in left-to-right order) of this string are set 1 (LSB) and the first bits are set 5 (MSB).

The next input data bit pair 10, 01.11 and 11 is the next output bit pair ooiooo, ooooo
, 10100 and 00100, and these bit pairs are shown in FIG. These bit patterns are obtained from the expression used for the first two bits in the input data string.

The encoded data string 740 is 0000
It becomes 100100000001010000100.

If the initial record of data automatically starts with a mark or binary 1 data bit that can be subtracted later, then this data string would be as follows according to the bottom line of FIG. (1)00001 00
It is divided into marked and unmarked areas with 100000001 01 00001 and OO data bit records. It should be noted that this makes the unmarked areas of the optical media consistently shorter than the marked areas, 5 resulting in improved linear recording density.

The coded data is programmed to generate a coded data string 750 with transitions on the data 1 edges, as opposed to a logic circuit that provides a high level only for binary 1 data bits. The output from 5-bit shift register 724 is applied to DC triggered flip-flop 728. The output of flip-flop 728 is then used to drive an NRZI type recording system. Note that S-bit shift register 724 is loaded every 5 bits as determined by load timer 726.

A decoder 900 shown in FIG. 9 is used to decode data coded according to the circuit of FIG. 7. Decoder 900 must use a series of look-up tables to identify the next state allowed by the data to determine the currently acceptable decoding pattern.

Encoded data string 902 is detected from the optical medium using one of the many optical data reading systems conventionally used or proposed. Data string 902 is input to a 15-bit shift register 904 in a serial manner. Shift register 904 is timed by data clock source 906;
Data clock source 906 also times output timer 908 . In the decoding process, 15 bits of input data are 7. It begins when clocked into register 904 .

The output signal from the 15-bit shift register 904 representing the first five bits of the data string 902 is:
is transferred to the set decode logic element 912, and this element 912
As explained in connection with the encoding device 700, the signal processing unit 700 processes a signal, that is, an input bit, using a “set” of five bits as one group. The set decode logic element 912 outputs two sets of bits based on which output bits a given set of inputs are assigned to according to the encoding constraints.

Set decode logic 912 accomplishes this decoding by using well-known look-ahead techniques. The next two sets of five data bits in 15-bit shift register 904 are read by look ahead logic 916. This look ahead logic element 916 is a 15-bit shift register 904
Depending on the data bit pattern inside, simply:
A high level output is provided on the Q to Z output lines.

The table of FIG. 11 is used to set the outputs applied to lines Q-Z.

For example, if the shift register 904 has Q6 to Qlo
If the output of the second five data bits, represented as , and the look ahead logic inputs F through J are 0000.1, then the Q output line of look ahead logic element 916 will be high. Also, the S, R, X, Y and Z output lines are high and the remaining output lines remain low. This indicates that the block S, R, X, Y or Z contains the subsequent data bit pattern and that the set decode logic element Call 912.

The logic used by set decode logic element 912 is:
This is shown in the look ahead table of FIG. Bit values based on this table are registered in set decode logic element 912z, and a special output for a given 5-bit human cover pattern is provided to a given look ahead block. Table 5 below is a table summarizing the relationship between an input data bit pattern and a look up table with that data pattern within its structure. However, look ahead blocks are only valid for one block at a time.

11 can be used to understand how specific data is decoded into a specific 2-bit string of decoded data.

The QOO used in the previous example (Figures 7 and 8)
Assume that the bit format in which the string of data bits OloooloooOOOOOOIOlooOolooo was encoded in the previous example is now input to the decoder 900 as read data 902.

This data is shifted in a 15-bit shift register 904, and then this data is transferred to a set decode logic element 912.
and look ahead decode logic 916. The 5-bit block is set to 00001.00100.00 by shift register 904.
It is divided into 000.10100 and 00100.

Referring to FIG. 11, which is a look up table for decoding, the first five bits are the output of the set of 10 data bits output to register 918, or the set of 11 data bits. can give any of the following outputs. Register 918 sets these bits to 9
Output to 20. However, the look up table value associated with the 10 bit output is W and the look up table value associated with the 11 bit output is Z. By pasting the next 5 bits, these bits are 00100 and exist in the W block,
It turns out that it is not in Z block. Therefore, the W line from look-ahead decode logic 916 is high, the Z line is not high, and the set decode logic 912 indicates that the decode process must select 10 bits as the current output. Let me know. The next 5 bits will produce either 10 bits or 11 bits, but the correct look ahead selection will select line X high and the output will be 10. This processing operation continues through the coded data string 902 to decode the data, and
1010011111 coded data string 920 is provided.

In order to reduce the number of interconnections required for the encoder, or coding device 700, or the decoder, or decoding device 900, other logic circuits can be easily substituted by experts in this field. That is clear.

It is not necessary that each state, or look ahead block, exist as a single output on a separate output line.

Consecutive 4-bit symbols of an unconstrained and unencoded data string are coded by changing the encoding constraints to (0, 1, 0) and (l, 11) according to the present invention. The run length limited encoding procedure for encoding an encoded data string into consecutive five character symbols is fully described in the encoding table of FIG. In FIG. 13, the coder's response to uncoded symbols (input) is given in the column labeled "Status". Each column shows the response of the coder in a particular coding state to possible possible combinations of the four uncoded input bits. This response consists of two parts (fold) and includes the next encoding state and the output symbol of the five encoded characters. In FIG. 13, the output of the symbols of the code is given in the form of NRZ, ie lands are indicated by the symbol "+" and marks are indicated by the symbol "-". These characters (including the +, - symbols) form an alphabet of binary representation, and they are easily translated into NRZI format by the following rules. That is, if different from the previous character, the current character is translated to "1", and if the same as the previous character, the current character is translated to rOJ. Run length constraints apply to the NRZI format, but the mark
It is more easily distinguished from the lower lands of the RZ format.

The encoding table shown in Figure 13 is for state 1
It has 14 states from state 14 to state 14.

For each coded state, 16 of the form "next coded state/coded output" correspond to the 16 possible 4-bit input symbols of uncoded data.
There are paired item lists. For example, the encoding device
Assume that we are in state 3 of the encoding table in Figure 3 and that the next four bits to be encoded are 1000. Under this assumption, the encoding device generates the response 3/----+ in response to the combination of the current state and the uncoded input bits.

Here, "3" indicates the next encoding state, and r
-1--+J indicates the encoded output.

The uncoded data string is divided into a series of overlapping 4-bit blocks (inputs), each block having a device to see the next state and an output in the table corresponding to the current state. coded by This output is concatenated with the previous output and the next state becomes the current state for encoding the next 4-bit block of data.

FIG. 14 shows an apparatus for implementing the encoding table of FIG. 13. The encoding device includes conventional registers 950, 952, and 954, which are programmable read-only memories (RO
M) 956 and storage driver 958,
It is timed by a clock pulse Ck. The state table is programmed into ROM 956 in a conventional manner, with each state table entry having an address location, "
It is stored in the "current state/input" location.

In the circuit of Figure 14, the address is an 8-bit number, ABCD represents the current state, and EFGH represents the 4-bit block to be encoded.
6 is a 9-bit word, i.e. ST1 to ST4, DA
I to DA5 are output; in this case, ST1 to ST4 are 4 bits that indicate the next status, and DAl to DA
5 is 5 bits indicating the encoded output. The operation of the encoder is synchronized to the Ck pulse by the responses of registers 950, 952 and 954. In this regard, registers 950 and 952 are EFGH and ABCD.
, while the ROM 956 stores formats STI to ST.
4 to the input of the register 952, and DAI to DA5 (output) to the register 954.
give to When clock pulse Ck transitions, the next 4-bit block of uncoded data is input into register 950, and STI through ST4 are input to register 950.
52, and DAl to DA5 are input to register 9.
54.

Signal format conversion and concatenation of the encoded data is performed by storage device 958. The formatted and encoded records are stored on storage medium 96
It is done with 0. In this regard, storage driver 958 serializes the output obtained from register 954;
and provides output in the form of an appropriate drive signal to storage medium 960. The entire encoding process suggested by the table of FIG. 13 involves the driver 958 properly formatting the symbols "+" and "-" in the table for presentation to (or for transfer to) a given storage medium. Those skilled in the art will easily understand that this includes the operations of such a format conversion device.

ROM 956 may be implemented by a separate logic circuit according to the pool representation of FIGS. 15A-B. 15th
In Figures A and B, signals STI to ST4 and DAI to DA5 correspond to what was described above in connection with FtOM956, as well as what was done for symbols A to H. In the notation of Figures 15A and B, the neighbors represent a logical AND function and a "+", a logical OR function.

The angline below the symbol represents the complement of the anglined symbol. Each symbol in FIGS. 15A and 8 corresponds to a combinational logic gate routinely constructed according to this expression.

A decoding process that is complementary to the encoding process of FIG. 13 is shown in FIG.

Referring to FIG. 17, when encoded data on storage medium 960 is retrieved, the encoded data is first detected by storage driver 958 and stored as a string of encoded data in three It is applied to registers 970-972 connected in series. The process of decoding a string of data coded according to the table of FIG. 13 requires knowledge of 12 consecutive characters in order to decode a block of 5 bits. The 12 characters include the two characters preceding the block and the five characters following the block. In Figure 16, the 12 characters are ab
cdefg hIjkl, where each character represents one of two binary symbols (+ or -).

To carry out the logic of FIG.
dc is provided to register 971 and the character +kjlh is provided to register 970. The decoding process is carried out in the form of a table according to the table shown in FIG.
4 in the usual way. Since the encoding device can be described by a table giving each 12-character input string and a corresponding 4-bit output string, ROM 974 stores 12-bit strings representing the 12 consecutive characters needed to decode the cdefg. Respond to addresses. However, a more compact representation of the decoder is given in a pair of tables in FIG.

In order to decode the five character blocks, cdefg, the upper table is provided with an ab column and a cdefg column. The "" mark in the ab column indicates that it is irrelevant. Looking at each column, there are two or more numbers, the binary representation of which represents a possible coded block. The column containing these numbers is (A
I and A2), or (B3, B4 and B5), or (C9, Cl0SC11 or Cl2), or (D3
7 and D48). The table at the bottom is used to select the appropriate columns to selectively read these numbers. In the bottom table, the hljkl column is used to find the current value of the five characters following the block to be decoded.

Next to this column are column labels A, B, C, and D. To select a particular number from the upper table, the labels contained in the A, BSC and D columns of the lower table are used, so the arrangement of the labels contained in the A, B, C and D columns is as follows: The table has been made to include all of the possibilities of selection.

The label shown in the row of the corresponding block in Kiryu of abcdefg in the upper table is hIj in the lower table.
The binary representation of the number found in Kiryu next to kl and indicated by the found label is the decoded data. Thus, after decoding block cdefg, the characters in registers 970-972 are shifted five positions to the right and the next block of five symbols is decoded.

To explain the above example more concretely, assume that the string to be decoded is as follows. That is, 1,,,+ −−+ −−+ −−++ −−−−10+
+ −−+ −−−++10, ,.

In this partial character string, the values of the five characters to be decoded (cdefg) are 10-10. The values of the index parameters in the first table (upper table) of ab cdefg in Figure 16 are:
+-1+--10, which corresponds to the 16th row of the table. The entry in the 16th row of the first table is
the first, indexed by the current value of hzkl.
6 is a three-binary representation of the data decoded by the selections made according to the rows in the second table of FIG. In this case, the value of hNkl is 11++-, which corresponds to the sixth row of the second table. The sixth row of the second table selects column B3 of the first table in which the data to be obtained is shown. Returning now to the intersection of row 16 and column B3 in the first table, a 4-bit binary representation of 3 (0011) is provided as the decoded output. This string fragment of the symbol is then moved five positions to the right, which causes it to be in the sixth position of the first table.
111+10- is given as the index of the first table mapping the rows, and in the sixth row of the first table the numbers 1 and 5 are found in columns A1 and A2, respectively.

The next block, ten, indexes the fourth row of the second table in FIG.
Select column A4 and give the decoded output from the binary representation of the number 1 (0O01).

The decoder of FIG. 17 for implementing the table of FIG. 16 includes a 4-bit wide decoding table with 4096 addressable locations, each of which corresponds to the 12 consecutive symbols described above. contains the 4-bit block obtained from the decoding process of the 5-character block in the block. Thus, a name storage location corresponds to one associated pattern out of 4096 possible bit patterns of a 12-bit character block.

The combinatorial logic for a decoder operating according to the table of FIG. 16 is shown in FIG.

In Figure 18, the notation has been changed, so AB
CDEFG HIJKL is W4W5 XlX2
It is expressed as X3X4X5 YIY2Y3Y4Y5. The 4-bit block generated by this decoder is
It is ZIZ2Z3Z4. The pool expression in Figure 18 is
Those skilled in the art will readily understand that this can be implemented in a routine manner using conventional logic circuit technology.

Thus far, a novel rast data code has been described, referred to as an asymmetric data code, which provides an asymmetrical spacing of binary O's between adjacent binary 1's. Also described is a novel data code processing apparatus useful for various encoding/decoding applications.

The above-described embodiments of the present invention do not need further explanation as experts in this field can easily make various changes and modifications within the scope of the technical idea of the present invention. This is self-evident.

(Margin below) Coming Q Or"0m0O+++0 00000000? + 0 1 1 1 1 1 1 1 1 1 ( mouth mouth ω seagull Table 4 Coding of tuple decoding logic Group 1 0 +11 10OX 10OO (A+B+C+E) (A+B+C+E+I1J) (E+F) (D) Group 2 = 10 +01 +IX (1+J) (D) (F) Group 3 X →−〇〇 (C+H+G) (D) Group 4 = OX +00 +11 (G+H) (E+F) (F) Group 5 = OX +01 +IX +10 (J) (E+F) (G) (F) Here, X represents no relation.

DETAILED DESCRIPTION OF THE F1 INVENTION As described above, the present invention provides a method and apparatus for generating a run length limited asymmetrically encoded string of data bits from a string of input data. Also, this method
Increases the linear recording density of data recorded on optical media under limited data constraints.

[Brief explanation of drawings]

FIG. 1 shows a physical pattern of marks representing data formed on an optical medium; FIG. 2a shows a physical pattern of data symmetrically encoded with PPM on an optical medium; Figure 2b is a diagram showing the physical pattern of PWM symmetrically encoded data on an optical medium;
Figure 3a shows an asymmetrical encoding apparatus constructed in accordance with the present invention for recording encoded data on an optical medium; Figure 3b shows the waveforms of pulses associated with the apparatus of Figure 3a; FIG. 4a is a diagram showing an asymmetric data decoder constructed in accordance with the present invention; FIG. 4b is a diagram showing pulse waveforms associated with the apparatus of FIG. 4a; and FIG. FIG. 6 is a diagram showing a second embodiment of an asymmetric encoding device according to the present invention for encoding a “data string” having a (1,6)-(3,8) constraint condition.
1/2 of LL A diagram illustrating a second embodiment of an asymmetric decoder constructed in accordance with the present invention for decoding coded data with (1,6)-(3,8) constraints;
FIG. 7a shows a third embodiment of an asymmetric encoding device according to the invention for encoding a data string with the 215(1,9)-(4,9) constraint of RLL; FIG. 7b The figure shows the decoding logic circuit used in the device of FIG. 7a, FIG. 8 shows the input data and output data of the encoding device of FIG. 7, and FIG. 9 shows the 215 (1, 9) of the RLL. −
(4,9) Figure 10 showing a third embodiment of a decoder according to the present invention for encoding a string of data with a constraint condition.
11 shows a decoding table for the decoder of FIG. 9, and FIG. 12 shows a look table for the decoder of FIG. 9. Diagram showing the ahead decoding table, first
Figure 3 shows 415 (1,11)-(0,10) asymmetric RL
14 is a block diagram of a coding device that executes a table that operates according to the coding table of FIG. 13; FIGS. 15A and 15B are diagrams showing the code of FIG. 14. FIG. 16 is a diagram showing a list of pool expressions applied to implement the encoding device; FIG. 16 is a diagram showing an encoding table for encoding a string coded according to the encoding table of FIG. 13; FIG. The figure is a block diagram of a decoder that is executed according to the coding table of FIG. 16, and FIG. 18 is a diagram showing a list of pool expressions for explaining an independent logic decoder that operates according to the present invention table of FIG. It is. 300.500... Coding device, 302.502
... Input data string, 504 ... Shift register, 508 ... Dividing device, 510 ...
Clock signal, 512...Counter, 514.51
5...Nor gate, 520...Combinational logic section, 522.524.526.534.528,...
And gate, 320.530,532...or...
Gate, 310,540,544...Single shot device, 340.550...Output signal. Applicant International Business Machines Corporation Representative Patent Attorney Hitoshi Yamamoto (External 1)
Name) MSa diagram MSb diagram Figure 4a Figure 4b Figure M11 Figure M+5 Figure 17★ GEE MISA diagram TOOLEl * 1 (CR+80)ill 158
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+++++++ AI Day 5 cll p46 No. 161i11 A1 Explosion Y5+ Engineering 2YSY4 A2 Explosion A1 1IT18 Fig.

Claims (4)

[Claims] (1) An input string of binary data bits,
A method of asymmetrically encoding binary coding characters into an output sling, wherein the input string has the form of a string of ones and zeros, and the output string includes first and second code characters. In an encoding method having the form of a sequence of code characters extracted from a binary character alphabet: (a) M/N(d_1, k_1); (d_2, k_2)
encode the above input string inductively according to the constraint , where M is the number of data bits encoded during induction, and N is the number of data bits encoded by encoding M data bits. d_1 and d_2 are the minimum number of said first code characters that occur between adjacent second code characters in said output string; k_1 and (b) k_2 is the maximum number of said first code characters that occur between adjacent second code characters in said output string; In response to the occurrence of code 2, the constraint condition is set to (d_1, k_1)
and changing between (d_2, k_2),
Run length limited encoding method. (2) an apparatus for generating constrained, run-length-limited, encoded data from a string of serialized input data bits, the apparatus responsive to M input data bits; Generates N output data bits and outputs N output data bits (d, k
) Output data bit 1 based on coding constraints
output data bit 0 between, where d is the minimum number of output data bits 0 and k is the maximum number of output data bits 1 between adjacent output data bits 1. In some cases, (a) the values of the above (d, k) coding constraints are set as (
A run length limited encoding device comprising means for changing between (d_1, k_1) and (d_2, k_2) (where d_1≠d_2). (3) An apparatus for generating asymmetrically encoded data from a symmetrically encoded run length limited input data string, comprising: (a) a symmetrically encoded run length limited input data string; - means for generating a single pulse of variable width in response to each negative going transition in a limited input data string; (b) said input data string and for generating said single pulse; having a positive transition approximately in phase with a corresponding positive transition in said input data string, said corresponding negative transition in said input data string generating said single pulse in response to a pulse from said input data string. means for generating an output data string having negative transitions delayed in phase by an amount based on the width of the pulse from the means for decoding. (4) An apparatus for generating symmetrically encoded data from an asymmetrically encoded run length limited data string that includes a plurality of negative and positive going transitions, the apparatus comprising: (a) means for generating a variable width single pulse in response to each positive going transition in a symmetrically encoded run length limited input data string; (b) generating said single pulse; (c) means for inverting the pulses generated by the means for generating a single pulse; (c) the input data string; In response to a pulse from the means, the input data string has a negative transition substantially in phase with a corresponding negative transition in the input data string, and is out of phase by an amount based on the width of the pulse from the means for generating the single pulse. An encoding device comprising: means for generating an output data string with delayed positive transitions.