JPH0360070A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To contrive the decline and reduction of a sensitivity subsequent on a difference in performances among MOSFETs by changing a pair of bit wires which are connected to respective drains and gates of a plurality of flip- flops in which two MOSFETs commonly comprising a source electrode diffusion layer in a sense amplifier and their gate electrodes are arranged symmetrically are connected so as to cross each other for each flip-flop. CONSTITUTION:N-channel MOSFETs 1101 and 1102, and 1103 and 1104 respectively comprise a common source electrode diffusion layer and these are arranged so that the 1101 and 1103, and the 1102 and 1104 are respectively irradiated with ion beams from the same direction and they show the same performance respectively. Then, the 1101 and 1104 are connected with one of bit wire 1401 and the 1102 and 1103 are connected with another bit wire 1402. As a result, an influence of a shady part at the time of ion implantation during a manufacturing process can be cancelled. Accordingly, the decline of a sensitivity of a sense amplifier due to a difference in performances of the composed field-effect transistors can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to semiconductor memory, particularly dynamic RAM.
between the sense amplifier circuits.

[Prior Art] Conventionally, an MO having N-channel and P-channel shared source electrode diffusion layers connected to bit lines 3401 and 3402 as shown in FIGS. 3(a) and 3(b) has been used.
C composed of balanced flip-flops with SFETs 3101, 3102, 3201, and 3202 cross-connected.
There is a MOS type sense amplifier circuit. When a slight potential difference occurs between the left and right bit lines 3401 and 3402 by reading data bits from the memory capacitor, N
When the potential of the channel sense amplifier driver 3501 is gradually lowered to activate the sense amplifier, only the lower potential side of the left and right bit lines 3401 and 3402 is discharged through the N-channel MO3FET 3101 or 3102, and the potential difference is amplified. At this time, the sensitivity of the sense amplifier is determined by the conductance constants βl and β2 of the two MOSFETs forming the flip-flop, and the difference in threshold voltage △VTH.
The sensitivity depends on each bit line capacitance CI, C2 and the voltage drop rate of the sense amplifier driver, and its sensitivity is m- for f and m+ΔVT)I for r. (Proceedings of the Institute of Telecommunications Engineers J61-C, 6PP
399), Here, from the formula, if the two MOSFETs have completely symmetrical performance, the sense amplifier will have infinitesimal sensitivity, but in reality, the characteristics of each MOSFET vary due to various factors that cannot be completely controlled. There is a difference. Therefore, the sense amplifier can only amplify a finite voltage difference. When a sufficient potential difference is generated between the bit lines 3401 and 3402, the N-channel sense amplifier driver 3501 is suddenly lowered to O■, the low potential side is completely set to O■, and then the P-channel sense amplifier driver 3502 is operated. Then, only the bit line potential on the high potential side is recharged to the vCC level. In this way, the bit line potential on the high level side is brought to a completely high level, the potential of the bit line on the low level side is brought to a completely low level, and this data is written into the memory cell again.

[Problems to be Solved by the Invention] As the capacity of dynamic RAM increases, the read voltage difference decreases due to the reduction in capacitor cell area. As a result, it is necessary to increase the sensitivity of the sense amplifier. In the conventional sense amplifier circuit described above, the difference in conductance constant of two MOSFETs constituting a flip-flop,
Its sensitivity is determined by the difference in threshold voltage and the difference in capacitance of the two bit lines. However, with the increase in capacity, MOS
Due to the miniaturization of FETs, it has become difficult to control each constant of the transistor. One such phenomenon is that when ions are implanted obliquely into the source/drain region at the periphery of the semiconductor substrate, the amount of ions implanted at the gate/source interface and the gate/drain interface differ due to the shadow of the gate electrode.

Usually, two MOSFETs constituting a flip-flop are arranged on a substrate so that they share a source region as shown in FIG. 3(b). Furthermore, since ion implantation is performed while swinging the ion beam from the ion beam source at the - point toward the semiconductor substrate, ion implantation is performed from an oblique direction in the peripheral area of the semiconductor substrate. From these conditions, Figure 3 (C)
, In the ion implantation into the shared source electrode diffusion layer region 4601 and drain regions 4602 and 4603 as shown in (d), the portion where the ion beam is blocked by the gate electrodes 4701 and 4702 is that one MOSFET is in the source region 4601 and the other MOSFET is in the source region 4601. MOSFET is located in the drain region 4602.

This causes a difference in conductance constant, dark voltage, etc. between two MOSFETs having a shared source electrode diffusion layer that constitute a flip-flop.

This asymmetrical effect of ion implantation in the direction perpendicular to the gate electrode due to the shadow of the gate electrode is a major cause of the decrease in sensitivity of the sense amplifier constituted by two MOSFETs having a shared source electrode diffusion layer. The purpose of the present invention is to alleviate this decrease in sensitivity.

[Means for Solving the Problems] The gist of the present invention is to provide a common source impurity region, two drain regions provided on both sides of the common source impurity region with a channel forming region in between, and the channel forming region. A flip-flop comprising two field effect transistors each including two gate structures provided on a region, the flip-flop being formed by cross-connecting the gate structures of the two field effect transistors and two train regions. A first bit line connected to a train region formed on one side of a common source impurity region of two field effect transistors constituting a flip-flop has a plurality of field effect transistors constituting another flip-flop. connected to a drain region formed on the other side of the common source impurity region of the transistor; and connected to a drain region formed on the other side of the common source impurity region of the two field effect transistors constituting the flip-flop. The second bit line is connected to the drain region formed on one side of the common source impurity region of the two field effect transistors forming the other flip-flop, thereby forming a sense amplifier.

[Operation of the Invention] In the sense amplifier according to the above configuration, the influence of shadow portions during ion implantation in the manufacturing process can be offset by alternately connecting the bit lines. Therefore, the sensitivity of the sense amplifier does not decrease due to the difference in characteristics of the constituent field effect transistors.

Embodiment FIG. 1(a) is a circuit diagram of a first embodiment of the present invention, and FIG. 1(b) is a plan view of a main part of the first embodiment. Nchi+l
I, MOSFETs 1101 and 1102 and 1103
．． 1104 each have a shared source electrode diffusion layer, ]10
1 and 1103 and 1102 and 1104 are arranged so that they receive the ion beam from the same direction and exhibit the same performance. Therefore, connect 1101 and 1104 to one bit line 1.
401, 1102 and 1103 to the other bit line 140
Connect to 2. At the time of cono, 1101.1103 (7) conductance constant is β1.1102, conductance constant of 1104 is β2.1ioi, ttoa and 1102.1
If the difference in threshold voltage between the sense amplifiers 104 and 104 is ΔVT41, the sensitivity of this sense amplifier is βl+β2. Here, from the equation, if the difference in bit line capacitance is O, βl and β2 have different values, and even if ΔVTH takes a finite value, the sensitivity becomes infinitely small.

This makes it possible to increase the sensitivity of the amplification effect performed by the flip-flop composed of N-channel MOSFETs.

FIG. 2(a) is a circuit diagram of a second embodiment of the present invention, and FIG. 2(b) is a plan view of a main part of the second embodiment. In the first embodiment of the present invention, only the amplification sensitivity of the flip-flop composed of N-channel MOSFETs is made high, and it is first necessary to operate only the N-channel driver to perform initial amplification. On the other hand, in addition to the first embodiment, this embodiment also has two sets of flip-flops composed of P-channel MOSFETs, and an N-channel MOSFET.
It is connected to the bit line as well. As a result, even a flip-flop composed of a P-channel MOSFET can perform highly sensitive amplification, and even if the N-channel driver and the P-channel driver are operated at arbitrary timings, the above-mentioned effects can be obtained.

[Effects of the Invention] As explained above, the present invention uses a plurality of flip-flops in which two MOSFETs, each of which shares a source electrode diffusion layer and whose gate electrodes are arranged symmetrically, are cross-connected in a sense amplifier. By exchanging the pair of bit lines connected to the drain and gate of each flip-flop, each MOSFET
This makes it possible to reduce the decrease in sensitivity caused by the difference in performance between the two.

[Brief explanation of drawings]

FIG. 1(a) is a circuit diagram showing a first embodiment of the present invention.
Figure (b) is a plan view of the main part showing the first embodiment, Figure 2 (a)
2 is a circuit diagram showing the second embodiment of the present invention, FIG. 2(b) is a plan view of the main part showing the second embodiment, FIG. b) is a plan view of the main part showing the conventional example, Fig. 3(c) is a sectional view taken along line A-A' in Fig. 3(b), and Fig. 3(d) is the equivalent of Fig. 3(c). It is a circuit diagram. 1101~1104°2101~2104°3101.3102...N channel MO5FE
T. 1201, 1202°2201~2204°3201.3202...◆...P channel MO5FE
T. 1401, 1402°2401, 2402°3401.3402...Bit line, 1501
, 1502°2501, 2502°3501.3602...◆...Session amplifier driver, 1601-1603°2601-2604°3601.3602...Source/drain diffusion layer region, 1701-1711°2701 ~2714°3701~3708...Aluminum wiring, 1801~1803°2801~2804°3801.3802...Polycrystalline silicon gate electrode, 1901, 2901°3901...・・・Contact hole, 41
01 ・ ・ ・ ・ ・ ・ 4201, 4202 ・ 4301, 4302 ・ 4601, 4602 ・ 4701, 4702 ◆ 4801 ・ ・ ・ ・ ・ ◆ ・・・Ion beam implantation direction, ・・・Element isolation region, ・・・Gate oxide film, ...Drain region, ...Polycrystalline silicon gate electrode, ...Semiconductor substrate.

Claims (1)

[Claims] A common source impurity region and two regions provided on both sides of the common source impurity region with a channel forming region in between.
two field effect transistors including one drain region and two gate structures provided respectively on the channel forming region, and the gate structures of the two field effect transistors and the two drain regions intersect. A first bit line connected to a drain region formed on one side of a common source impurity region of two field effect transistors constituting a flip-flop is connected to a plurality of flip-flops connected to each other. connected to the drain region formed on the other side of the common source impurity region of the two field effect transistors forming the flip-flop, and formed on the other side of the common source impurity region of the two field effect transistors forming the flip-flop. The second bit line connected to the sense amplifier is connected to the drain region formed on one side of the common source impurity region of the two field effect transistors constituting the other flip-flop. A semiconductor memory device characterized by comprising: