JPH0357979A - Inspecting device for memory - Google Patents

Abstract

PURPOSE:To enable detection of such a fault of a memory to be inspected as dependence of a memory cell of an observed address on data of a memory cell of a peripheral address by a method wherein random number data are written in the memory to be inspected and they are read out and determined. CONSTITUTION:A random data generator RDG outputs signals of three systems and address pattern signal ADD, a write-in data pattern signal WDATA and a write-in timing pattern signal W. These signals are outputted to the input of a memory MUT to be inspected through a reference memory RM and an waveform shaping device DRV, and an output of the memory MUT is delivered to an error detecting terminal ERR through a level determinator CMP. An entire circuit is synchronized by a timing generator TG. Next, the generator RDG generates a random pattern, and after random writing is made in all bits of the memory MUT, the same data are read out, while a discord output comes out to the detecting terminal ERR when the memory has a fault.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a memory testing device, and particularly to a testing device that performs a functional test of a semiconductor random access memory.

[Prior Art] Conventionally, this type of memory testing device manually applies address stamps, write data stamps, and write timing stamps to the memory under test from algorithmic test stamps generated by a test program. Furthermore, it is common to determine whether or not the output from the memory is appropriate based on an expected data button and a read timing button. FIG. 2 is a block diagram thereof. Here, the control memory CM stores a test program, and the algorithmic exerciser EXER is a part that generates an algorithmic test pattern based on this program.

Such conventional memory testing devices usually use algorithms such as "march bang" and "gallop bang" to perform memory function tests.

In this case, the normal algorithm uses a specific address in memory specified by the loop index (hereinafter referred to as the address of interest) and the addresses that will be accessed immediately before and after the address of interest (hereinafter referred to as target address). There is a field that describes how to determine the address, and for all remaining addresses (hereinafter referred to as fields) excluding the address of interest and target address, the data is either all 0 (aiQ.O) or all 1 (aiQ.O). It is a limited slam such as 1).

[Problems to be Solved by the Invention] In the conventional memory testing device described above, algorithmic test patterns are generated under program control, so the field data is not random as it is when the memory is actually used. Therefore, in semiconductor random access memories where the operation of a memory cell at an address of interest is affected by the contents of memory cells surrounding the address of interest, it is difficult to completely inspect the operation.

[Differences between the Invention and the Prior Art] The present invention differs from the conventional memory testing device described above in that it tests the memory using random data that is not based on a program.

[Means for Solving the Problems] The gist of the present invention is to provide at least one system of random number signal generators, a built-in memory having an address size equal to or larger than the address size of the memory to be tested, and a random number signal generator from the random number signal generator. It has a write circuit that writes to the internal memory at the same time as writing to the memory under test based on a signal, and a coincidence detection circuit that detects coincidence between data read from the memory under test and data read from the internal memory. It is.

[Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention. Here, the random data generator RDG outputs three systems of signals, namely, an address bang signal ADD, a write data bang signal WDATA, and a write timing bang signal W, and these signals are sent to the reference memory RM and the waveform shaping machine D.
It is applied to each of the inputs of the memory under test MUT via the RV.

The output of the memory under test MUT is also connected to the output data of the reference memory RM and the input of the exclusive-or-game FOR via the level determination machine CMP, and the result is output to the error detection terminal ERR. All circuits are also synchronized by timing from a timing generator TG.

Next, this operation will be explained. Random data generator RDG
By generating three systems of random bangs, random writes and reads are performed simultaneously to the memory under test MUT and the reference memory RM, so random writes were performed to all bits of the memory under test MUT. Later, unless the memory under test MUT is defective, the same data will be read out, and the error detection terminal ER
There is no mismatch output from R. If the memory under test MUT is defective, a mismatch output is output to the error detection terminal ERR at the time when the random data generator RDG outputs a defective address.

In this memory device to be tested, the field data on the memory to be tested MUT at the time of testing is completely random, and it is possible to continue testing as many situations as possible within the testing time.

FIG. 3 is a block diagram showing a memory testing device according to a second embodiment of the present invention. Unlike the first embodiment, the random data generator RDG only outputs one system of signals, the write data slam signal WDATA, and outputs two other systems of signals: the address button signal 80D, the write timing button signal W, and the read data button signal W. The timing bang signal R is outputted by the algorithmic equalizer EXER controlled by the program in the control memory CM as in the conventional memory testing device, and the mismatch signal outputted to the error detection terminal ERR is outputted by the AND gate AN.
D allows a mask operation to be performed in response to the read timing bang signal R.

During operation, this memory testing device determines the target address and target address by program control in the same way as conventional memory testing devices, but the field data in this case is random.

In this embodiment, it is possible to systematically operate the access order, writing, and reading by a program, which is effective in shortening test time.

[Effects of the Invention] As explained above, the present invention writes random number data into the memory under test, reads it and makes a determination so that the memory cell at the target address depends on the data of the memory cell at the peripheral address. This has the advantage that defects in the memory under test can be detected.

Furthermore, since the memory testing device of the present invention does not require programming of judgment data buttons, it is also effective in reducing programming errors.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a memory testing device according to a first embodiment of the present invention, FIG. 2 is a block diagram showing a conventional example, and FIG. 3 is a block diagram showing a second embodiment. MUT ・ ・ ・ ・ EXER ・ ・ ・ TG・ ● ・ ● ◆ RDG ・ ・ ・ RM・ ・ ・ ・ ・ DRV ・ ・ ・ CMP ・ ・ ・ ・ EOR◆Contest◆・ AND ● ・ ● ● CM・ ◆ ● ● ● ADD◆ ◆ ◆ ◆ WDATA- ● W・ ・ ● ● ● ・ RDATA◆ ● R・ ◆ ● ◆ ● ● ・・Memory under test, ・Algorithmic equalizer, ・Timing generator, ・Random data generator,・Reference memory, ・Waveform shaping machine, ・Level judgment machine, ・Exclusive OR gate, ・AND gate, ・Control memory, ・Address button signal, ・Write data button signal, ・Write timing button signal, ・Expected data button Signal: - Read timing bang signal, ERR - - Error detection terminal.

Claims (1)

[Claims] At least one random number signal generator, a built-in memory having an address size equal to or larger than the address size of the memory under test, and writing to the built-in memory at the same time as writing to the memory under test based on the signal from the random number signal generator. What is claimed is: 1. A memory testing device comprising: a write circuit that performs the above operations; and a coincidence detection circuit that detects coincidence between data read from the memory under test and data read from the built-in memory.