JPH0356518B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a control system for time division time switches in automatic exchanges and the like.

(Prior art) As a conventional time division time switch of this type,
For example, there is a maintenance switch for a communication path testing device, which is described in "D70 Automatic Switching System" edited by Nippon Telegraph and Telephone Public Corporation (Telecommunications Mutual Aid Association, pages 100-111). This will be explained below.

Figure 2 shows the configuration of the maintenance switch MSW mentioned above. In the figure, TSW is a call memory (time switch), SCM is a holding memory (control memory), and P
-GEN is a parity generator, P-CHK is a parity check circuit, CNT is a sequential counter, SEL0 is a data selector, SEL1 is an address selector, REG0 is an order register,
REG1 is an answer register, ORDDEC is an order decoder, and TIM is a timing generator. This maintenance switch MSW converts the time-division multiplexed data signal for each time slot on the input highway FHW to a sequential counter CNT.
The communication memory TSW is written in accordance with the address instruction of the communication memory TSW, while the output to the outgoing highway BHW is performed by reading the data signal of the communication memory TSW using the data signal of the holding memory SCM as the address.

FIG. 3 shows a specific example of the above-mentioned exchange process, in which an example in which #0 time slot of the outbound highway BHW and #3 time slot of the inbound highway FHW are connected, will be described in detail below.

Assuming that a time slot incoming highway FHW consisting of data signals of one frame A, B, C...Z is pulled in from the network (not shown), the speech memory TSW is filled in by the addressing information indicated by the sequential counter CNT. Then,
Data signals for each time slot are sequentially written starting from address #0 in the call memory TSW.

When exchanging the data signal [D] written at address 3 of the call memory TSW to the 0 time slot of the outgoing highway BHW, the supervisory test control device (not shown) writes the data signal [D] written at address #0 (outgoing highway #3 (corresponding to the time slot of BHW) is written to #3 (corresponding to the time slot of BHW).
data signal [D] time slot number) and writes it into the holding memory SCM. In this way, the address signal of the call memory TSW is randomly written in the holding memory SCM.

In the read operation of the data signal [D] to the output highway BHW, the sequential counter CNT sequentially reads out the address signals of the communication memory TSW written in the holding memory SCM.

Outputs the time slot signal from the read address signal of the call memory TSW
By sending it on the BHW, the data signal [D] is exchanged to a designated time slot.

In this normal replacement process, the maintenance switch
MSW performs sequential write and random read exchange operations.

By the way, in the above-mentioned exchange process, writing to the holding memory SCM is performed using the "holding memory write" order and the "holding memory write" order among the "ST bus sending orders" sent from the external control device that controls the time division time switch. ” order. The write operation to this holding memory SCM will be explained below.

The "holding memory write" order is held by the order register REG0, and is given as the write address WADD of the holding memory SCM via the address selector SEL1. Next, the "holding memory write" order is ordered by register REG0.
is held as the write data WD of the holding memory SCM via the data selector SEL0.
It is given with the parity bit WDP added by the parity generator P-GEN. Also,
The order part held in order register REG0 is
Decoded by the order decoder ORDDEC,
It is given as write information W to the holding memory SCM. The holding memory SCM performs a write operation based on the given write address WADD, write data WD, and write information W. Note that the write address WADD corresponds to the time slot on the output side, and the write data WD corresponds to the time slot on the input side. The above write operation closes a unidirectional path.

Also, when closing another unidirectional path,
This is achieved by changing the data contents of the "holding memory write" order and "holding memory writing" order and executing the same write operation as above.

Therefore, when closing a bidirectional path, the first "holding memory write" as shown in FIG.
A one-way path is closed by the order and the "holding memory write" order (holding memory write A),
Furthermore, another unidirectional path was closed and executed by the second "holding memory write" order and the "holding memory write" order (holding memory write B).

(Problems to be Solved by the Invention) As mentioned above, in the conventional time division time switch control system, in order to set one bidirectional path, the control device performs the first "holding memory write".
It is necessary to send out four orders: an order, a "holding memory write" order, a second "holding memory write" order, and a "holding memory write" order, which places a large load on the control device, and There was a problem that the bus occupancy time between the split time switch and the split time switch was long.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to realize a control system for a time division time switch that can reduce the load on the control device and the time occupied by the bus when setting bidirectional paths.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention includes a call memory, a holding memory, and a control section, and based on the control of the control section, the communication is performed every time slot on the incoming highway. data signals are sequentially written into the call memory, predetermined data signals are written into the hold memory according to a hold memory write order from an external control device, and the data signals in the hold memory are used as address signals of the call memory, and the data signals are written into the call memory. In a time-division time switch control method in which exchange processing is executed by reading data signals stored in the output highway for each time slot on the output highway, one of the data signal and address signal for the holding memory is transferred to the data signal for the holding memory. a first selection means for outputting one of a data signal and an address signal for the holding memory to an address line for the holding memory; and a holding memory write order from an external control device. and a signal generating means that generates a switching signal when the decoding means decodes a specific holding memory write order, and according to the switching signal, data is transmitted to the data line and the address line. One of the signals and the address signal, which are different from each other, is switched and sent.

(Function) According to the present invention, by sending the specific holding memory write order after the normal holding memory write order, it is possible to execute a holding memory write operation in which data signals and address signals are exchanged, and a bidirectional write operation is possible. The path can be closed.

(Embodiment) FIG. 1 is a schematic diagram of a time division time switch showing an embodiment of the present invention. In the figure, the same components as those of the conventional example are designated by the same reference numerals. That is, the MSW is a time division time switch, and is composed of a one-stage communication memory TSW, a holding memory SCM, and a control section CS. In addition, CC is an external control device that controls the time division time switch via the bus.
Connected to MSW and other equipment.

FIG. 5 shows details of the portion of the control unit CS related to write control to the holding memory SCM. In the figure, 1 is an interface section;
2 is a sequence control unit, 3 is a data register, 4
is an address register, 5 is an order register, 6 is a decoder, 7 is an AND gate, 8, 9, 10 are flip-flops, 11 is a timing control section for memory control, 12, 13, 14 are selectors, 15 is a parity addition section, 16 is a write gate, 17 is a timing generation circuit, 18 is a data line, and 19 is an address line.

The selector 12 constitutes a first selection means that outputs either a data signal or an address signal for the holding memory to a data line for the holding memory, and receives the outputs of the data register 3 and the address register 4, and Either one of them is output to the data line 18.

The selector 13 constitutes a second selection means that outputs either a data signal or an address signal for the holding memory to an address line for the holding memory, and receives the outputs of the data register 3 and the address register 4, and Either one of them is output to the address line 19.

The decoder 6 receives orders from an external control device,
For example, it constitutes a decoding means for decoding a holding memory write order, decoding the contents of the order register 5, and sending signals to each section.

The timing generation unit 11 constitutes a signal generation means that generates a switching signal when the decoder 6 decodes a specific holding memory write order,
It receives a specific signal, which will be described later, from the decoder 6 and sends a switching signal CHGTIM to the selectors 12 and 13.

FIG. 6 shows a configuration example of a holding memory write order from the control device CC. "Retained memory write"
The order is the write address of the holding memory SCM, that is, the time slot number of the outgoing highway BHW in this embodiment, and the "holding memory write" order is the data to be written in the holding memory SCM, that is, in this embodiment. Indicates the time slot number of the incoming highway FHW. The "bidirectional holding memory write" order is an order for bidirectional path closure, and in the case of this embodiment, indicates the time slot number of the incoming highway FHW.

FIG. 7a shows the order selection order for setting a unidirectional path. In FIG. 7, b is the order sending order for setting a bidirectional path. The operation when the order shown in FIG. 7a is received will be described below.

When a "hold memory write" order is sent from the control device CC, the data that has passed through the interface section 1 with the control device CC is latched in the data register 3 and order register 5 using synchronization information SYNC from the sequence control section 2. do. The sequence control unit 2 also detects a match between the name codes, and advances the subsequent sequence only when there is a match.

The data latched by the order register 5 is expanded by the decoder 6, W information is output, and the AND information with the address timing information ADTIM from the sequence control unit 2 is given to the address register 4 by the AND gate 7. register 3
The data held in the address register 4 is transferred to the address register 4.

Thereafter, although not shown, the sequence control unit 2 returns answer synchronization information ASYNC as response information to the control device CC, and the control sequence ends.

When a "holding memory write" order is sent from the control device CC, the data that has passed through the interface section 1 is transferred to the synchronization information from the sequence control section 2.
Data register 3 and order register 5 are latched by SYNC. The data latched by the order register 5 is decompressed by the decoder 6, and W information is output. If the name codes match, order strobe information from sequence control unit 2
W information is flip-flopped 8 by ORDSTB
is latched to.

The W information latched in the flip-flop 8 is given to the timing generator 11. The timing creation section 11 creates write gate enable timing WGETIM and memory control information MCONT synchronized with the clock of the holding memory SCM as shown in the time chart of FIG. The data held in the data register 3 passes through the selectors 12 and 14, has parity added by the parity addition circuit 15, and is then given to the write gate 16.
The write gate enable timing WGETIM shown in the time chart of FIG. 8 is applied to the holding memory SCM when the write gate enable timing WGETIM is at "H" level.

Further, the address information held in the address register 4 is transferred to the holding memory via the selector 13.
Given to SCM. When the memory control information MCONT shown in FIG. 8 is at the "H" level, data is written to the supplied address in the holding memory SCM.

After a certain period of time has elapsed, the sequence control unit 2 returns answer synchronization information ASYNC as response information to the control device CC (not shown). Also, reset timing information RSTTIM is outputted and applied to flip-flop 8, flip-flop 8 is reset, and the entire write order sequence is completed.

The write operation when setting the unidirectional path shown in FIG. 7a has been described above, and the write operation when setting the bidirectional path shown in FIG. 7b will be described below.

When a "holding memory write" order is received, the write operation is the same as the one-way path setting described above.

"Bidirectional retention memory write" from control device CC
When an order is sent out, the data that has passed through the interface section 1 is latched by the data register 3 and order register 5 using synchronization information SYNC from the sequence control section 2.

The data latched by the order register 5 is decompressed by the decoder 6, and BW information is output. If the name codes match, sequence control unit 2
More order strobe information by ORDSTB
BW information is latched into flip-flop 8.

The BW information latched in the flip-flop 8 is given to the timing generator 11. As shown in the time chart of FIG. 9, the timing generation unit 11 generates write gate enable timing WGETIM, memory control information MCONT, and switching timing synchronized with the clock of the holding memory SCM.
Create CHGTIM.

The data held in the data register 3 is passed through the selectors 12 and 14 to the parity addition circuit 1.
After parity is added by 5, write gate 1
6 and is applied to the holding memory SCM when the write gate enable timing WGETIM shown in the time chart of FIG. 9 is at "H" level. Further, the address information held in the address register 4 is transferred to the holding memory via the selector 13.
Given to SCM.

Data is written to the supplied address in the holding memory SCM when the memory control information MCONT shown in FIG. 9 is at the "H" level. Next, switching timing CHGTIM information is outputted from the timing generation section 11 and given to the selectors 12 and 13. The selectors 12 and 13 switch the information held in the data register 3 and address register 4 and provide it to the holding memory SCM.

That is, the data held in the data register 3 goes through the selector 13 to the address line 19 of the holding memory SCM, and the address information held in the address register 4 goes through the selectors 12 and 14 to the parity addition section. Parity is added at 15, and the data is transferred to the holding memory via the write gate 16.
Data is written to the address that is applied to the data line 18 of the SCM and is being supplied when the memory control information MCONT in FIG. 9 is at the "H" level.

After a certain period of time has elapsed, the sequence control unit 2 returns answer synchronization information ASYNC as response information to the control device CC (not shown). Also, reset timing information RSTTIM is outputted and applied to flip-flop 8, flip-flop 8 is reset, and the entire write order sequence is completed.

(Effects of the Invention) As explained above, according to the present invention, the first selection means outputs either a data signal or an address signal for the holding memory to a data line for the holding memory, and a data signal for the holding memory. and an address signal to the address line for the holding memory; a decoding unit for decoding a holding memory write order from an external control device; signal generating means for generating a switching signal when the order is decoded; and according to the switching signal, switching and transmitting one of the data signal and the address signal to the data line and the address line, respectively. Therefore, by sending the specific holding memory write order after the normal holding memory write order, it is possible to execute a holding memory write operation in which data signals and address signals are exchanged, thereby closing a bidirectional path. Therefore, it is only necessary to send a series of orders from the control device, which has the advantage of reducing the load on the control device and the time occupied by the bus between the control device and the time division time switch, etc. .

[Brief explanation of drawings]

The drawings serve to explain the present invention. FIG. 1 is a schematic diagram showing an embodiment of the method of the present invention, FIG. 2 is a diagram showing the configuration of a conventional time division time switch, and FIG. 4 is an explanatory diagram illustrating the exchange process by the circuit shown in the figure. FIG. 4 is an explanatory diagram illustrating the conventional ordering at the time of path closure. FIG. 5 is a diagram showing the configuration of the control unit CS in FIG. 6 is an explanatory diagram showing the configuration of the holding memory write order in the circuit of FIG. 1, FIG. 7 a and b are diagrams showing the order when the path is closed in the circuit of FIG. 1, and FIG. FIG. 9 is an operation time chart when a unidirectional path is closed in the circuit of FIG. 1, and FIG. 9 is an operation time chart when a bidirectional path is closed in the circuit of FIG. 1... Interface section, 2... Control sequence section, 3... Data register, 4... Address register, 5... Order register, 6... Decoder, 8... Flip-flop, 11... Timing creation section, 12 , 13, 14...Selector.

Claims (1)

[Claims] 1. Comprising a call memory, a holding memory, and a control section,
Based on the control of the control section, data signals for each time slot on the incoming highway are sequentially written into the communication memory, and predetermined data signals are written into the holding memory according to a holding memory write order from an external control device. In a control method for a time-division time switch in which exchange processing is executed by using the data signal in the holding memory as an address signal for the calling memory and reading out the data signal stored in the calling memory for each time slot on the outgoing highway, the holding memory is a first selection means for outputting one of a data signal and an address signal for the holding memory to a data line for the holding memory; and a first selection means for outputting either a data signal and an address signal for the holding memory to an address line for the holding memory. 2 selection means, decoding means for decoding a retention memory write order from an external control device, and signal generation means for generating a switching signal when the decoding means decodes a specific retention memory write order. . A control system for a time division time switch, characterized in that, according to the switching signal, different one of the data signal and the address signal is switched and sent to the data line and the address line, respectively.