JPH035616B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hardware time management system in an information processing device. In information processing equipment
In order to measure and record the actual operating time of the CPU and other input/output devices and use it as data for hardware management, there is a method of counting the basic clock that is synchronized with the internal clock of the hardware and recording it at a specific address in the main memory device. It has been taken. This counting result is used as the basis for calendar calculations, and is also expressed as the current year, month, day, and time. However, in this case, the internal clock is generated by a hardware timer and uses a crystal oscillator, so there is no need to install a special circuit and it can be used as a nearly accurate time meter. The oscillation frequency from the oscillator may differ from the expected value at the time of design depending on its manufacturing and usage conditions. Therefore, when counting the operating time of the hardware using the basic clock based on the internal clock, It has the disadvantage that as the usage time increases, errors accumulate and become too large to ignore.

The present invention seeks to provide a means for solving this drawback by correcting the number of basic clocks recorded at a specific address in the main memory device without requiring any special circuit modifications or additional circuits to the hardware timer. According to the present invention, this means that in an elapsed time counting circuit that accumulates and records the number of basic clocks in a specific address of the main memory device each time it receives a basic clock from a hardware timer, there is no error in the basic clock. In this case, the difference between the expected integrated value of the basic clock that should be integrated within a certain time and the actual integrated value of the basic clock that is actually integrated within the same time is calculated in advance, and from the calculated result, the elapsed time counting circuit The number of receptions of the basic clock that causes a certain difference between the expected integrated value and the actual integrated value is the correction cycle specified value, and the value to be corrected and integrated to eliminate the certain difference is the correction addition value (0 or positive or negative). the number of receptions of the basic clock is counted in the elapsed time counting circuit, and when the number of receptions matches the specified correction period value, the correction addition value is calculated. This is achieved by a hardware time management system characterized by performing cumulative recording with correction by performing cumulative integration. As a result, the basic clock count integrated value is constantly corrected, and errors can be greatly improved.

An embodiment of the present invention will be specifically described below with reference to the drawings.

FIG. 1 shows various clock diagrams in a hardware time management system, and FIGS. 2a and 2b show a circuit block diagram and its procedure diagram in a hardware operating time management system. In FIG. 1, 13 indicates the internal clock from the hardware timer, and 12 indicates the expected clock when designing the hardware timer, that is, the basic clock expected if there is no error in the internal clock 13 and other related circuits. It is. As shown in FIG. 2a, in the hardware timer 23, the basic clock generation circuit 25 is switched to the internal clock circuit 24 as the hardware operates.
Therefore, the basic clock 11 of FIG. 1 which has a period that is an integral multiple of the internal clock 13 shown in FIG. 1 is inputted.
occurs. Hardware time management processing unit 26
Each time it receives the basic clock 11 from the basic clock generating circuit 25, it sends an elapsed time counting command to the microcontroller 21, and the microcontroller 21 follows the command as shown in FIG. 2b. A specific address for elapsed time counting in the main memory device 22 is accessed to read the contents, that is, the elapsed time count value. In the case of the first basic clock, the content of this specific address is 0, so this value is read out, +1 is added to this value, and it is recorded again at the original specific address. As a result, 1 indicating the cumulative value of the number of receptions of the basic clock is recorded at the specific address. The second basic clock 11 is also sent to the microcontroller 21 when the hardware receives it.
accesses a specific address in the main memory device 22 and reads its contents. Since this seed is 1, add +1 to it and store it again at a specific address. In other words, the number 2, which indicates the cumulative value of the number of receptions of the basic clock, is recorded at the specific address. In this manner, the microcontrol circuit 21 repeats the above operation each time the hardware receives the basic clock 11, and the number of basic clocks received so far is accumulated and recorded at a specific address in the main memory device 22. Since the basic clock is sent out at a constant cycle, the integrated value of the basic clock is a count value indicating the elapsed time since the first basic clock was sent out.
Assume now that after a certain period of time has elapsed, a basic clock integrated value (referred to as an actual integrated value) Mm is obtained from the specific address. In this case, this actual integrated value Mm is the expected design value of the hardware timer.
However, depending on the manufacturing or usage conditions of the hardware timer, the basic clock 11 from the hardware timer may have a slight error from the clock expected at the time of design. Therefore, counting using only the basic clock will result in accumulation of errors after a long period of time, and the actual integrated value Mm of the basic clock will have a non-ignorable cumulative error of Mm - Nm = Dm with respect to the expected integrated value Nm. It comes to show.

FIGS. 3a and 3b are correction procedure diagrams when writing in the main memory device 22 by the basic clock 11 in one embodiment of the present invention.

In the present invention, when the hardware receives the basic clock 11 based on the internal clock from the hardware timer, the microcontroller 21 accesses a specific address in the main memory device 22 in response to a command for counting elapsed time. , reads its contents, adds +1 to it, records it again at a specific address, and repeats this operation each time the basic clock 11 is received. The integrated value (here Mn) is recorded as in the conventional case. On the other hand, when a hardware timer is completed, it is already known whether the basic clocks generated based on the internal clocks will be more or less than the number of generated clocks expected at the time of design. Therefore, according to the present invention, the actual integrated value in the main memory device 22 that counts and records the basic clock 11 at any given time is
The integrated value of the basic clock is corrected using the ratio Sn=Nn/Mn and Km=1/1-Sn of the expected integrated value Nn at the time of design of the hardware timer for the same time as Mn.

For example, if the basic number of clocks is greater than the planned number of clocks, the actual integrated value Mn and the expected integrated value Nn
The ratio of Sn=Nn/Mn<1. From this, when Kn=1/1-Sn, the time point at which both clocks coincide is Mn=7, and when Nn=6, Kn=7. The value of Kn is the number of integrations at which a difference of Dn (in this case, Dn = 1) occurs between the actual integration value Mn and the expected integration value Nn, and when the number of integrations reaches this value, it is time to perform correction. be. Therefore, Kn is written as the specified correction cycle value. Also, the difference between the actual integrated value Mn and the expected integrated value Nn
The value to which Dn is normally added, that is, the value subtracted from 1 Cn =
1-Dn (in this case, since Dn=1, Cn=0) is written as the corrected addition value. As shown in FIG. 3A as a correction period designation value 27 and a correction addition value 28, these can be stored in any memory device, for example, the main memory device 22.
Store it in any area within. This allows the third
As shown in Figure b, when the seventh basic clock arrives, the microcontroller reads the integrated value 6 recorded at a specific address in the main memory, and conventionally adds +1 to it and records it again. In the present invention, the number of receptions of the basic clock at this time is stored in the correction period designation value 27, Kn=7.
Since they match, Cn=0 stored in the correction addition value 28 is added to the content value, that is, the addition of +1 is omitted, and the read 6 is recorded at the specific address again.
In other words, the integrated value of the basic clock is corrected,
Mn=Nn.

On the other hand, if the basic clock number is less than the scheduled clock, the elapsed time count integrated value Mn and the recorded integrated value
The ratio of Nn is Sn=Nn/Mn>1. Here, if Mn = 6 and Nn = 7 at the time when both clocks are generated, then Kn = 1/1 - Sn = -6 Using the absolute value of 6, Kn = 6, but this Kn
The correction period designation value 27 shown in FIG. 3a in the same way as above
and Cn=1-Dn=1-(Mn-Nn)=1-
(-1)=2 is stored in the correction addition value 28. As a result, when the sixth basic clock is received, the integrated value 5 is read from a specific address in the main memory under the control of the microcontroller, and conventionally it is incremented by +1 and recorded at the specific address again, but this In the invention, a correction addition value Cn=2 is added and recorded at a specific address as an integrated value Mn=7.

This makes it possible to correct the integrated value of the basic clock. As described above, according to the present invention, the difference between the basic clock number based on the hardware timer and the expected clock number, which is the expected value at the time of design, is checked when the hardware timer is completed, and Sn and Kn are used to calculate the difference between both clocks. By finding Mn and Nn when the times of occurrence match, the correction cycle specified value Kn and correction addition value are determined.
By determining Cn and making corrections, the error in the integrated value of the basic clock can be greatly improved.

As is clear from the above, in the present invention, the difference between the actual integrated value and the expected integrated value that occurs due to usage conditions such as power supply voltage and temperature changes is not corrected.
Since errors caused by the oscillation frequency of the internal clock are corrected at regular intervals, it is possible to significantly reduce the frequency of cumulative errors that cannot be ignored.
Moreover, it can be realized with an extremely simple configuration.
Accuracy can be improved economically.

[Brief explanation of the drawing]

Figure 1 is a diagram of various clocks in a hardware time management system, Figures 2a and b are circuit block diagrams and their procedure diagrams in a hardware time management system, and Figures 3a and b are one embodiment of the present invention. This figure shows a procedure diagram based on the hardware time management method. In the figure, 21 is a micro control circuit, 22 is a main memory device, 23 is a hardware timer, 24 is an internal clock circuit, 25 is a basic clock generation circuit, 2
6 is a time management processing unit, 27 is a correction cycle specified value, 2
8 indicates a corrected addition value.

Claims (1)

[Scope of Claims] 1. In an elapsed time counting circuit that accumulates and records the number of basic clocks in a specific address of a main memory device each time a basic clock is received from a hardware timer, the elapsed time counting circuit accumulates and records the number of basic clocks at a specific address of a main memory device, and when there is no error in the basic clock, The difference between the expected integrated value of the basic clock that should be integrated within the same time and the actual integrated value of the basic clock that is actually integrated within the same time is calculated in advance, and from the calculation result, the elapsed time counting circuit calculates the expected integrated value. The number of receptions of the basic clock that causes a certain difference between the actual integrated value and the actual integrated value is determined as a specified correction cycle value, and the value to be corrected and integrated in order to eliminate the certain difference is determined as a correction addition value (0 or a positive integer). and by counting the number of receptions of the basic clock in the elapsed time counting circuit, and integrating the correction addition value when the number of receptions matches the specified correction period value. A hardware time management method characterized by performing cumulative recording with correction.