JPH0355993Y2 - - Google Patents

Description

[Detailed Description of the Invention] Purpose of the Invention Industrial Application Field The present invention relates to a display buffer circuit for a video RAM used in a videotex terminal or the like.

Conventional technology Video used in videotex terminals, etc.
In the RAM, display data is sequentially read out during the display period within one line, and the display data is updated by random access from the CPU between the display readout periods. That is, it generates a display gate signal that defines the display area on the CRT, and when it becomes active, the video
Reading of display data from the RAM is started, and when the CPU accesses the video RAM within this display area, it is placed in a wait state until the fall of the display gate.

As a method to allow random access by the CPU within the display area, a series of display data is read from the video RAM at a higher speed than the display speed and held, and a speed conversion system is used to supply the display data to the display section in synchronization with the display speed. One possible method is to install a buffer memory and allocate the intermittent period caused by the above-mentioned high-speed reading to random access by the CPU.

Normally, the read speed from video RAM is about the same or lower than the display speed, and the higher the read speed, the more expensive the video RAM becomes. Therefore, a method can be considered to increase the actual readout speed by simultaneously reading out a plurality of adjacent pixel data groups from the video RAM and expanding them into serial pixel columns using a parallel/serial conversion circuit.

Problems to be solved by the invention In the above method of simply combining readout in pixel group units and expansion into serial pixel columns, it is necessary to increase the number of pixel group units that can be simultaneously read out in order to lengthen the intermittent period for display readout. is required. however,
There is a problem in that the pixel group unit that can be simultaneously read cannot be made very large due to limitations in the configuration of the video RAM.

Means for solving the configuration problems of the invention The display buffer circuit of the invention is based on video RAM.
Immediately after the shifted adjacent pixel group, the adjacent pixel group simultaneously read out is shifted one pixel at a time in synchronization with the display speed and supplied to the display section. By providing a series of cascade-connected register groups, the intermittent period of display readout can be expanded without greatly increasing the number of pixel groups that can be simultaneously read out.

Hereinafter, the operation of the present invention will be explained in detail together with examples.

Embodiment FIG. 1 shows a video related to an embodiment of the present invention.
FIG. 2 is a block diagram showing the configuration of a RAM display buffer circuit.

This display buffer circuit consists of 8
latch circuits L1 to L8, seven selectors S1 to S8 installed between these latch circuits, and a latch circuit L0 that holds four adjacent pixel data read out simultaneously from the video RAM (VR). A timing supply circuit T is provided for supplying timing signals to the latch circuit group and selector group.

Display data for four pixels read simultaneously from the video RAM (VR) is stored in the latch circuit L in the order of display.
0 sections L01, L02, L03 and L0
4 and is supplied to selectors S1 to S7 and latch circuit L8 via data lines D1 to D4.

In accordance with the timing signal received from the timing supply circuit T, the selector S1 selects either the pixel data on the data line D1 or the pixel data held in the latch circuit L2 at the subsequent stage, and outputs the pixel data to the latch circuit L1.
Transfer to. In accordance with the timing signal received from the timing supply circuit T, the selector S2 selects either the pixel data on the data line D2 or the pixel data held in the latch circuit L3 at the subsequent stage and transfers it to the latch circuit L2. Similarly, selector S3
selects one of the pixel data on the data line D1 or D3 or the pixel data held in the latch circuit L4 at the subsequent stage and transfers it to the latch circuit L3. Selector S4 selects data line D2 or D4
The upper pixel data or one of the pixel data held in the subsequent latch circuit L5 is selected and transferred to the latch circuit L4.

The selector S5 selects one of the pixel data on the data line D1 or D3 or the pixel data held in the latch circuit L6 at the subsequent stage and transfers it to the latch circuit L5. Selector S6 selects data line D2
Alternatively, the pixel data on D4 or one of the pixel data held in the latch circuit L7 at the subsequent stage is selected and transferred to the latch circuit L6. Selector S7
selects one of the data line D3 and the pixel data held in the subsequent latch circuit L8 and transfers it to the latch circuit L7. The latch circuit L8 latches the pixel data on the data line D4 according to the timing signal supplied from the timing supply circuit T. The operation of the circuit shown in FIG. 1 will be explained with reference to the timing diagram shown in FIG.

At time T1, section L0 of latch circuit L0 is simultaneously read from video RAM (VR).
1 to 4 held in each of 1 to L04
The pixel data up to the pixel data is passed through data lines D1 to D4 and selectors S1 to S4 to latch circuits L1 to L4.
will be forwarded to. The first pixel data held in the front-stage latch circuit L1 is immediately supplied to the display section and displayed. In order to avoid complicating the explanation, the time required for latching in each latch circuit and the transfer time between latch circuits will be ignored.

At the next time T2, the selectors S1 to S7 all select the output of the latch circuit in the subsequent stage and transfer it to the latch circuit in the previous stage, so that pixel data is shifted between the latch circuits L1 to L8. The second pixel data held in the latch circuit L1 is supplied to the display section. next time T
In step 3, pixel data is shifted by selectors S1 and S2, and third pixel data is supplied to the display section. At the same time, video RAM
section L0 of latch circuit L0.
5th to 8th held in each of 1 to L04
The latch circuit L3, in which the pixel data up to the pixel data passes through the data lines D1 to D4 and the selectors S3 to S6, becomes vacant (or can be overwritten) by shifting.
and L4 are transferred to latch circuit groups L3 to L6. At the next time T4, selectors S1 to S7
The pixel data is shifted by , and the fourth pixel data is supplied to the display section.

At the next time T5, the pixel data is shifted and the fifth pixel data is supplied to the display section. At the same time, the 9th to 12th pixel data read from the video RAM and held in sections L01 to L04 of latch circuit L0 are transferred to data lines D1 to D4 and selectors S5 to S5.
Through S7, the data is transferred to latch circuit groups L5 to L8, including latch circuits L5 and L6, which have become vacant (or overwritable) by the shift. next time T
At 6, pixel data is shifted, and the sixth pixel data is supplied to the display section.

Thereafter, from time T7 to time T12, the seventh to twelfth pixel data are sequentially supplied to the display section by shifting the pixel data.

At the next time T13, at the same time as the pixel data is shifted, the 13th to 16th pixel data read from the video RAM and held in each of sections L01 to L04 of the latch circuit L0 are shifted to an empty state. The signal is transferred to the latch circuits L1 to L4, and the same operation as that from time T1 to T12 is repeated.

The period of 7 display cycles from time T6 to T12 is an intermittent period in which reading for display is not necessary,
This is allocated for random access by the CPU. This intermittent period of 7 display cycles is
This is equivalent to the intermittent time obtained with a conventional buffer circuit that simultaneously reads eight pieces of pixel data from RAM and expands it in series.

Effects of the Invention As explained in detail above, the display buffer circuit of the present invention shifts the adjacent pixel group read from the video RAM by one pixel in synchronization with the display speed and supplies it to the display section. Since the configuration includes a column-arranged register group for arranging the next read-out adjacent pixel group immediately after this shifted adjacent pixel group, a large intermittent period can occur in a relatively small simultaneous read-out pixel group unit. can get.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a display buffer circuit according to an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of the circuit shown in FIG. L1 to L8...Latch circuits (registers) arranged in columns, S1 to S7...Selector, L0...Latch circuit holding four pixel data read simultaneously from video RAM (VR), T...Timing supply circuit.

Claims (1)

[Claims for Utility Model Registration] Intermittent reading for display is performed in units of a predetermined number of adjacent pixel groups during the display period in one line, and the intermittent period of reading for display is subject to random access by the processing device. video assigned
A display buffer circuit for RAM, which shifts adjacent pixel groups simultaneously read out from video RAM by one pixel in synchronization with the display speed and supplies them to the display section, and immediately after the shifted adjacent pixel group. 1. A display buffer circuit for a video RAM, further comprising a register group arranged in columns for arranging adjacent pixel groups read out simultaneously.