JPH035598B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a speech synthesis device capable of synthesizing speech.

As this type of speech synthesis apparatus, digital speech synthesis apparatuses employing the Percoll method are currently the mainstream. In this Percoll method, during voice analysis, the partial autocorrelation coefficient (Percoll coefficient) of the voice waveform and sound source information are derived as parameters for each frame period (10 msec) in which the voice can be considered stationary. This Percoll coefficient is the Percoll coefficient K ₁ between two adjacent sample values of the audio waveform sampled at about 8KHz,
For example, 10 Percoll coefficients K ₁ , K ₂ , to K ₁₀ are used, assuming that the Percoll coefficient K ₂ is between two sample values at a two-sample interval, and the Percoll coefficient Kn is between two sample values at an n-sample interval. On the other hand, the sound source information is the above Percoll coefficients K ₁ , K ₂ ,
It consists of a pitch coefficient P indicating whether the voice is voiced or unvoiced obtained from the residual signal after extracting ~ _K10 , a pitch coefficient P indicating the fundamental period in the case of voice, and an amplitude coefficient A of the sound source. That is, such coefficient groups K ₁ to K ₁₀ , P, A are 1
If the audio consists of frames and is 10 seconds long, a sequence of 1000 frames can be obtained continuously. The frame sequence for each voice thus obtained is stored in a parameter ROM (read-only memory) for a large number of voices.

Figure 1 shows the configuration of a conventional Percall-based speech synthesis device, and the parameters used in this device.
An example of the contents of the ROM is shown in Figure 2. In Fig. 1, 1 is a parameter ROM in which each address consists of 1 byte (8 bits), and according to Fig. 2, the pitch coefficient P has 6 bits, and the amplitude coefficient A has 5 bits.
37 bits are allocated to the percoll coefficients _K1 to _K10 , and each frame occupies 48 bits, that is, a memory area equivalent to 6 addresses. This frame series is stored for each voice. 2 is an address table that stores the starting address of the frame series of each audio stored in the parameter ROM 1 for each audio; 3 is an address counter;
By reading out the starting address of , and specifying this starting address, the frame series of the target audio stored in the parameter ROM 1 is sequentially read out. 4 is a frame unit coefficient group A read out from the parameter ROM 1 every frame period;
This is a synthesis circuit that resynthesizes the speech waveform based on P, K ₁₀ , K ₉ , _. A speech waveform is obtained by creating a sound source consisting of unvoiced noise A and applying it to a digital filter simulating vocal tract characteristics that is controlled by the Percoll coefficients K ₁ to K ₁₀ . Reference numeral 5 denotes an amplifier that amplifies the audio signal from the synthesis circuit 4, and drives the speaker 6. Reference numeral 7 denotes a control section, which has the function of accessing the address counter 3 and sending a start signal to the synthesis circuit 4.

On the other hand, a speech synthesizer having the above-mentioned configuration is usually used to produce sentences lasting from several seconds to several minutes. However, when the user wants to hear the audio starting from the middle of this sentence, the address counter 3 selects the parameter ROM 1 corresponding to this sentence.
This frame series must be read from the middle of the frame series. In this case, the important thing is that the address counter 3 should specify the parameter ROM1 at the time when the operation of the synthesis circuit 4 is started.
The address must be the first address in each frame. That is, the synthesis circuit 4 has 1
Regarding the coefficient group for each frame, as is clear from FIG. 2, the pitch coefficient P, the amplitude coefficient A, and the Percoll coefficients K ₁₀ , K ₉ , . . . , K ₁ are input in this order.
Therefore, if you start from an address other than this first address, it will be completely impossible to synthesize speech.

Therefore, in the conventional device as shown in FIG. 1, if the starting address of each frame series of the parameter ROM 1 is stored in the table 2, the address counter 3 will start the frame series at the starting point according to the table 2. Although only the first address can be specified, this requires increasing the memory capacity of the address table 2, leading to an increase in the size of the entire speech synthesis device, which is disadvantageous in terms of cost.

The present invention has been made in view of these points,
The details are explained below. An embodiment of the speech synthesis device of the present invention is shown in FIG. 3, and the contents of the parameter ROM used in this device are shown in FIG. In FIG. 3, numerals 3 to 7 indicate an address counter to a control section, similar to the conventional device shown in FIG. 1' is a parameter ROM in which each address consists of 1 byte, and as shown in Figure 4, 7 bits from the 2nd bit diagram to the 8th bit diagram of each address are used to store 7 consecutive addresses. A group of coefficients for one frame every time, that is,
6-bit pitch coefficient P and 5-bit amplitude coefficient A
and 37-bit Percoll coefficients K ₁ , ~, K ₁₀ are stored. A logic "1" is written as a special code in the first bit of the first address of each frame unit, and a logic "0" is written in the first bit of other addresses. A gate circuit 8 transmits a start signal obtained from the control section 7 to the synthesis circuit 4 when the first bit of the address of the parameter ROM 1' indicated by the address counter 3 is logic "1".

In a speech synthesizer having such a configuration, a parameter ROM 1' storing a large number of frame sequences as shown in FIG. 4 is used to produce sentences.
If you want to generate audio from the middle of the sentence,
The control unit 7 updates the contents of the address counter 3 for several microseconds.
The contents of each address are successively read out from the parameter ROM 1'. When there is a start command to start voice synthesis at a desired time, the readout control unit 7 generates a start signal,
When this start signal is sent to the gate circuit 8, the gate circuit will then write the parameter ROM.
When a logic "1" is obtained from the first bit of each address of 1', this start signal is transmitted to the synthesis circuit 4. From this point on, the synthesis circuit 4 that has received the start signal in this way starts the parameter ROM.
From the time when the contents of the first address of the frame unit are read from 1', parameter ROM1'
The contents from the 2nd bit to the 8th bit of each address are taken in.

On the other hand, the start signal obtained from the gate circuit 8 is fed back to the control section 7 again, and at the time this signal is obtained, the cycle for incrementing the contents of the address counter 3 is changed. That is, the parameter
The 7th address in each frame of ROM1' is specified in sequence at high speed, and a pause period of approximately 10 msec is provided before the 7th address in the next 1 frame is specified in sequence at high speed. Specify the 7th location of the unit. Depending on this, the synthesis circuit 4 receives the parameter ROM1' for each frame period.
A group of coefficients for each frame are correctly introduced in the order of pitch coefficient P, amplitude coefficient A, and Percoll coefficients K ₁₀ , K ₉ , . . . K ₁ . Then, the synthesis circuit 4 synthesizes a voice waveform based on these coefficient groups, and the synthesized voice is emitted from a desired intermediate point by the amplifier 5 and speaker 6.

In addition, as another embodiment of the speech synthesis device of the present invention, a memory configuration is adopted in which all the first addresses of each frame of the parameter ROM are assigned to special codes, and coefficient groups are stored in six addresses from the second address. You may do so. In this case, for example, an 8-bit "00000000" that does not appear in the 6th address from the 2nd address is used as a special code, and when this special code is read from the parameter ROM, a decoder that decodes it is sent to the synthesis circuit. If the start signal is transmitted, this synthesis circuit will be able to perform the second
It becomes possible to correctly import the coefficient group starting from the address.

As is clear from the above description, the speech synthesis device of the present invention writes a special code to the first address of each parameter group stored in a plurality of addresses in the parameter memory, and issues a start command using the read control circuit. Immediately after the special code is read from this parameter memory, the parameter group is supplied to the synthesis circuit. This means that there is no fear that parts and parts will be introduced as a parameter group, and that they will be accurately introduced in parameter group units.

Therefore, when producing a long synthesized speech, you can simply write the same special code when creating the parameter memory without having to prepare a large address table, and the synthesized speech can be produced from the desired location. can be obtained, and the size and cost of the speech synthesizer can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of a conventional speech synthesis device, Fig. 2 is a schematic diagram showing the contents of a parameter ROM used in the conventional device, and Fig. 3 shows the configuration of the speech synthesis device of the present invention. Block diagram, 4th
The figure is a schematic diagram showing the contents of a parameter ROM used in the device of the present invention. 1, 1'...Parameter ROM, 3...Address counter, 4...Synthesizing circuit, 5...Amplifier, 6
...Speaker, 7...Control unit, 8...Gate circuit.

Claims (1)

[Scope of Claims] 1. A memory in which a group of parameters extracted from a human voice at each of a large number of consecutive frame periods in which human voice can be considered to be in a steady state are stored by assigning addresses, and each parameter group is stored in a plurality of frames. a parameter memory which is stored across addresses and in which a special code marking the beginning of a parameter group is stored at each leading address; a read control circuit for reading out the parameter group by sequentially specifying addresses in the memory; It consists of a synthesis circuit that synthesizes speech using a plurality of parameter groups read out by the readout control circuit, and the readout control circuit reads out a special code after receiving a start command to start speech synthesis. A speech synthesis device characterized in that a parameter group is supplied to the synthesis circuit from the point in time, and the synthesis circuit is operated from this point on.