JPH0355868A - Computing method of interwiring capacitance of electronic circuit - Google Patents

Abstract

PURPOSE:To do without processing for fattening a wiring, restrict a region being an object for interwiring capacitance computation within a region smaller than the total region where the wiring is fattened, and reduce processing time, by extracting approximation part before interwiring capacitance computation processing. CONSTITUTION:A means A2 extracting approximation part of wiring is contained, and interwiring capacitance is computed based on the figure data of the approximation part extracted by the means A2. For example, at a step A1, pattern design data are inputted by application program operating on a processing executing means like a central processor: at a step A2, wiring nearer than the distance (d) wherein interwiring capacitance can not be neglected is found, and figure data corresponding to the region which is surrounded by the above-mentioned wiring and has an interwiring distance smaller than the distance (d) are generated. At a step 3, terminal information exhibiting the wiring, to which interwiring capacitance to be computed attributes, is assigned; at a step A4, interwiring capacitance is computed based on the figure data of the approximity part subjected to terminal information assignment.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to delay verification during pattern design of electronic circuits, and particularly to a method of calculating parasitic capacitance between wirings from pattern design data of electronic circuits.

[Conventional technology]

As electronic circuits become denser and more miniaturized, the effects of signal propagation delays and noise on circuits due to wiring capacitance cannot be ignored. For this reason, when designing electronic circuits, not only do circuit simulations and delay simulations be used to check the circuit operation, but also when designing a button, wiring capacitance and circuit connections are extracted from the button design data, and circuit simulation and delay simulation are performed to delay the delay. Increasingly, the verification of

Conventionally, when calculating wiring capacity from batan design data,
Only the capacitance between the wiring and the board was considered. However, as the density and miniaturization of electronic circuits progress, the capacitance between adjacent wires has become equal to the capacitance between the wire and the board, so it is necessary to find the capacitance between adjacent wires. It came out.

Here, the capacitance between adjacent wiring lines will be explained using a diagram.

FIG. 4 shows a portion of the wiring of an integrated circuit. Fourth
In the figure, 1 and 2 are aluminum wiring. FIG. 5 is a sectional view taken along line AA' in FIG. 4. 4
, 5 is an aluminum wiring, 6 is an insulating film, 7 is a silicon substrate, 8 is a parasitic capacitance formed between the side surfaces of the aluminum wirings 4 and 5, and 9 and 10 are parasitic capacitances formed between the bottom surfaces of the aluminum wirings 4 and 5 and the silicon substrate 70. It represents capacity.

As shown in the figure, when the distance between the aluminum wires 4 and 5 is equal to or smaller than the height of the aluminum wires 4 and 5, the parasitic capacitance formed between the side surfaces of the aluminum wires 4 and 5 cannot be ignored.

The capacitance between the side surfaces of such adjacent wirings can be determined by approximating the parallel plate capacitance. Assuming that the height of the aluminum wires is constant, the value of capacitance between adjacent wires is proportional to the length of adjacent portions of the wires and inversely proportional to the width of the spacing. Inter-wiring capacitance occurs between all wirings, but if we ignore those with small capacitance values, in practice it is only necessary to calculate the wirings that are closer to each other than a certain distance.

Conventionally, to calculate the capacitance between adjacent wires, one sets a region where the wire whose capacitance is to be calculated is thickened by a certain length, the wires that intersect with that region are considered adjacent wires, and the capacitance between those wires is calculated by I was looking for it.

A conventional method for calculating inter-wiring capacitance will be described below with reference to the drawings.

As shown in FIG. 3, the conventional inter-wire capacitance calculation method includes step C1 of inputting pattern design data, step C2 of setting a region in which the wire whose capacitance is to be calculated is thickened by a certain length, and C2. Step C3: Recognize the wiring that intersects the area obtained in Step C3 as a neighboring wiring; Step C4: divide the area while taking into account the positional relationship with the neighboring wiring and the shape of the area; and calculate the inter-wiring capacitance for each divided area. It consists of four steps, step C5.

Next, the specific operation of the conventional inter-wiring capacitance calculation method will be explained using the drawings. In FIG. 6, 11 is a wiring whose capacitance is to be determined, 12 is an adjacent wiring in a different layer from the wiring 11, and 13 is a region where the wiring 11 is thickened by a certain length. In FIG. 7, areas 14 to 23 are designated as areas 1 in FIG.
This is a partial divided area when 3 is divided. Step C2
Then, the wiring 11 (FIG. 6) whose capacitance is to be determined is made thicker by a certain length to obtain a region 13. The amount of thickening is such that, in the manufacturing process of the target electronic circuit, if the wiring spacing becomes narrower, the parasitic capacitance created between the side surfaces of the wiring cannot be ignored compared to the capacitance between the wiring and the substrate.

In step c3, since the wiring 12 intersects the area 13, it is recognized as a neighboring wiring to the wiring 11. Next, in step C4, the region 13 is divided in consideration of the distribution of electric lines of force determined by the positional relationship with adjacent wiring and the shape. Next, in step c4, the inter-wiring capacitance is calculated for each divided region. In the subregion 18.20, the inter-wiring capacitance can be calculated as a parallel plate capacitance. In other partial areas, Laplace is applied in that partial area.
The capacitance value is determined by solving a boundary value problem of the equation using a numerical solution method, or by referring to a numerical table determined in advance by numerical solution.

[Problem to be solved by the invention]

As the scale of electronic circuits, especially integrated circuits, increases, the amount of data that must be handled in inter-wiring capacitance calculation processing also increases. However, in the conventional inter-wire capacitance calculation method described above, recognition of adjacent wires is performed in two graphic processing steps: thickening the data and looking at the overlap between the thickened area and other wires, which requires a large amount of data. The disadvantage is that inputting pattern design data takes a long time to process. In addition, since inter-wire capacitance calculation processing is performed over the entire region thickened to recognize adjacent wires, parts where inter-wire capacitance can be ignored, such as partial regions 16 and 23 in FIG. 7, are also subject to processing. There is a problem in that extra processing time is required to calculate the inter-wiring capacitance.

[Means to solve the problem]

The inter-wire capacitance calculation method of the present invention includes means for extracting adjacent portions between wires as graphic data, means for attaching terminal information to the extracted graphic data of the adjacent portions, and graphic data of the adjacent portions to which terminal information has been attached. and means for calculating inter-wiring capacitance based on the data.

In the present invention, by extracting the adjacent portion of the wiring before the inter-wiring capacitance calculation process, it is possible to avoid the process of thickening the wiring, and the area targeted for inter-wiring capacitance calculation is It becomes possible to limit the area to a smaller area than the entire thickened area.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

As shown in FIG. 2, the information processing system used in one embodiment of the present invention includes data input means Bl such as a magnetic tape device for inputting pattern design data of an electronic circuit, and a central processing unit running an application program. A processing execution means B2 such as, and an auxiliary storage means 3 such as a magnetic disk,
It consists of a data output means B4 such as a line printer that prints the execution results.

As shown in FIG. 1, one embodiment of the present invention is an application program running on the processing execution means B2 in FIG.
a data input step A1, a step A2 of extracting the adjacent portion of the wiring as graphic data, and a step A3 of attaching terminal information to the extracted graphic data of the adjacent portion,
It consists of four steps, including step A4, which calculates the inter-wiring capacitance based on the graphic data of the adjacent portion to which terminal information has been attached.

In step A1, pattern design data is input.

In this input step, circuit connections are also extracted, and an element number is added to the graphic data configuring an element, and a net number is added as attached information to the graphic data configuring the wiring. In step A2, the wirings that are closer than the distance d where the capacitance between the wirings cannot be ignored are looked at, and graphic data corresponding to an area surrounded by these wirings and where the distance between the wirings is smaller than the distance d is generated.

This step corresponds to the wiring spacing check in the design rule check for electronic circuit pattern design. As for the design rule check, the speed-up technology has already been established, so if the design rule check is utilized, the process of this step can be executed at high speed. In particular, note here that checking whether another shape exists within a certain distance around a shape can be executed in the same processing time as checking whether the shapes overlap. From this, it can be seen that the processing time required for the wiring thickening process is shorter than the adjacent wiring recognition process in the conventional wiring capacitance calculation method. Here, the meaning of the graphic data of the adjacent portion extracted in this step will be explained. Consider that the part indicated by the graphic data of the adjacent part extracted in this step is the dielectric part (in the case of integrated circuits, the interlayer insulating film) of the desired inter-wiring capacitance, and the wiring surrounding it is the conductive part. . In other parts, the inter-wiring capacitance is considered negligible.

In step A3, terminal information indicating which wire and which wire the calculated inter-wire capacitance is attached to is attached. Line segment data that coincides with the side where the wiring is in contact with the graphic data of the adjacent portion extracted in step A2 is generated, and this data is used as a terminal graphic. The terminal figure should have the same net number as the wiring that touches the terminal figure. In addition, the same element number is given to terminal figures that are in contact with each other and adjacent partial figures. By attaching terminal information in this manner, it becomes possible to recognize which inter-wiring capacitance is attached between which nets.

In step A4, the inter-wiring capacitance is calculated based on the graphic data of the adjacent portion to which terminal information has been attached. Several methods can be considered for calculating the inter-wiring capacitance depending on the required accuracy and processing speed. The method of solving the boundary value problem of the Laplace equation by numerical solution has the highest accuracy, but it is a method with a very slow processing speed. In this embodiment, it is assumed that a large amount of data after pattern design is completed is processed at high speed. In this case, the requirement for accuracy is not so high, so in this embodiment, a simple method that can be calculated quickly is used. That is, the proximate partial figure is divided into a portion that can be regarded as a parallel plate capacitor and a portion that is not. For portions that cannot be regarded as parallel plate capacitances, the capacitance value is determined by approximating the parallel plate capacitance by distributing it depending on the shape, or by referring to a numerical table prepared in advance using a numerical solution method.

Next, the specific operation of this embodiment will be explained using the example of FIG. 6 used in the explanation of the conventional inter-wiring capacitance calculation method. The shaded area 24 in FIG. 8 is the graphic data of the wiring adjacent portion obtained by executing the wiring adjacent portion extraction of this embodiment using the design rule check for the example shown in FIG. It can be seen that the region 24 is considerably smaller than the region 13 in FIG. 6 where the wiring is thickened. Thick line 25
．． 26 indicates a terminal figure.

Next, a method for determining the value of the inter-wiring capacitance from the graphic data of the adjacent portion of the wiring and the terminal graphic shown in FIG. 8 will be explained.

First, the direction of electric lines of force between adjacent wirings is determined. this is,
Find the direction of the straight line connecting the midpoints of each terminal figure by approximating it to the horizontal or vertical direction. Next, a dividing line parallel to the direction of the electric force lines is drawn from the bent vertex of the terminal to divide the adjacent partial figure. Furthermore, if there is a point of contact 27 between the terminal shapes as shown in Figure 8, it is divided by drawing a dividing line parallel to the lines of electric force from a point shifted in a direction perpendicular to the lines of electric force by a certain distance from the point of contact. .

The partial area obtained in this way is the partial divided figure 28 in FIG.
, 29, 30. While the number of divided figures in the conventional method shown in FIG. 7 is ten, the number of divided figures obtained in this embodiment is reduced to three. Partially divided figure 2
Regarding 8.29, find the value of the inter-wiring capacitance in this part by approximating the parallel plate capacitance. In the partial divided figure 3o, the capacitance value is determined by referring to a numerical table determined in advance by numerical calculation.

〔Effect of the invention〕

As explained above, the present invention extracts the adjacent portion of the wire before the inter-wire capacitance calculation process, thereby eliminating the need for the process of thickening the wire, and also improving the area that is the target of inter-wire capacitance calculation. can be limited to a smaller area than the entire area where the wiring is thickened, which has the effect of shortening the processing time compared to the conventional inter-wiring capacitance calculation method.

[Brief explanation of drawings]

Figure 1 is a process flow diagram for calculating inter-wire capacitance according to an embodiment of the present invention, Fig. 2 is an equipment configuration diagram of an information processing system used in the embodiment shown in Fig. 1, and Fig. 3 is a conventional inter-wiring capacitance calculation process flow diagram. Calculation processing flowchart, FIG. 4 is a plan view showing an example of a part of the wiring of an integrated circuit, FIG. 5 is a cross-sectional view taken along the line AA' in FIG. 4, and FIG. FIG. 7 is a diagram explaining a region in which one wiring is made thicker in the conventional wiring capacitance calculation process, and FIG. 8 is a diagram explaining the state after dividing the region in which one wiring in FIG. 9 is a diagram illustrating graphic data extracted by the wiring adjacent portion extracting step according to an embodiment of the present invention, and FIG. It is. 1-2... Aluminum wiring, 4-5...
...Aluminum wiring, 6...Insulating film, 7...
...Silicon substrate, 8... Parasitic capacitance formed between the sides of aluminum wiring, 9-10... Parasitic capacitance formed between the bottom surface of aluminum wiring and silicon substrate, 11-12・・・・・・Aluminum wiring, l3
・・・・・・Area created by thickening the wiring 1L, 14-2
3...Partial division area after dividing the area l3 by the conventional inter-wire capacitance calculation process, 24...Figure extracted by the wiring adjacent portion extraction step of an embodiment of the present invention Data, 25-26...Terminal figure, 27.
. . . Contact points of terminal figure, 28 to 30 . . . Partially divided figures after dividing adjacent partial figure data in the inter-wiring capacitance calculation step of an embodiment of the present invention.

Claims (1)

[Claims] A method for calculating inter-wiring capacitance from pattern design data of an electronic circuit, comprising means for extracting an adjacent portion of the wiring, and calculating inter-wiring capacitance based on graphic data of the adjacent portion extracted by the means.