JPH0354909A - Amplifier device - Google Patents

Amplifier device

Info

Publication number
JPH0354909A
JPH0354909A JP1191129A JP19112989A JPH0354909A JP H0354909 A JPH0354909 A JP H0354909A JP 1191129 A JP1191129 A JP 1191129A JP 19112989 A JP19112989 A JP 19112989A JP H0354909 A JPH0354909 A JP H0354909A
Authority
JP
Japan
Prior art keywords
amplifier
output
gate
input
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1191129A
Other languages
Japanese (ja)
Inventor
Yasuki Mikamura
御神村 泰樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP1191129A priority Critical patent/JPH0354909A/en
Publication of JPH0354909A publication Critical patent/JPH0354909A/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)
  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)

Abstract

PURPOSE:To reduce the saturation degree of a transformer impedance type amplifier and to obtain an output signal having no distortion from a large input light current by using a gate means as a by-pass route when the potential difference between the input and output of the amplifier is more than a prescribed value to prevent an output voltage from being dropped. CONSTITUTION:An enhancement type FET Q5 to be a gate means having a gate is connected in parallel with a feedback resistor Rf. The source of the FET Q5 is connected to the output terminal 3 of the amplifier 2 and its drain and gate are connected to the input terminal of the amplifier 2. When an input light current iPD is increased and current flowing into the resistor Rf is increased, the potential difference between the input and output of the amplifier 2 is increased. When the value exceeds a threshold voltage, current starts to flow between the drain and source and the by-pass route is formed. Consequently, the saturation of the amplifier 2 can be suppressed without advancing the drop of the output voltage VOUT to a prescribed value or less.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は光通信用前置増幅装置として用いられる増幅装
置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an amplifier device used as a preamplifier for optical communications.

〔従来の技術〕[Conventional technology]

従来、光通信においては第4図に示すようにフォトダイ
オードlで光信号を受信し、これによって得られる信号
を増幅率(一A)の増幅器2に導き、増幅して出力端子
3から信号電圧V  を得out ている。増幅器2は帰還抵抗Rrが外付けあるいは集積
化されたトランスインピーダンス型と称されるもので、
例えば、電子情報通信学会技術報告(1986年OQE
86−68  p.51〜p.56)に示され、第5図
に図示の回路と等価なものである。
Conventionally, in optical communication, as shown in Fig. 4, a photodiode l receives an optical signal, and the resulting signal is guided to an amplifier 2 with an amplification factor (1 A), where it is amplified and output from an output terminal 3 to a signal voltage. I got V out. The amplifier 2 is a so-called transimpedance type amplifier in which a feedback resistor Rr is externally attached or integrated.
For example, the Institute of Electronics, Information and Communication Engineers Technical Report (1986 OQE
86-68 p. 51-p. 56), which is equivalent to the circuit shown in FIG.

この第5図の回路では、FETQ  ,Q,から{ なるインバータ段とFETQ,,Q4からなるレベルシ
フト/バッファ段とが同一電源■DDにより駆動されて
いる。FETQ,Q  はゲート.ソ24 −ス間が短絡された定電流負荷となっている。レベルシ
フト用のダイオードD ,D2は所定のバ1 イアス点を決定する機能を有する。かかる構或の回路に
よれば、入力信号を増幅率(A)で珈幅し反転した出力
信号V  を得ることができる。
In the circuit shown in FIG. 5, an inverter stage consisting of FETs Q, Q, and a level shift/buffer stage consisting of FETs Q, Q4 are driven by the same power supply DD. FETQ, Q are gates. It is a constant current load with short circuit between source 24 and source. The level shifting diodes D1 and D2 have the function of determining a predetermined bias point. According to a circuit having such a structure, an input signal can be amplified by an amplification factor (A) and an inverted output signal V can be obtained.

Out 〔発明が解決しようとする課題〕 しかしながら、上記のような増幅装置によるとフォトダ
イオード1に過大な入力が到来したとき増幅装置の飽和
が生じ実用に適さなくなる。即ち、飽和のためにダイナ
ミックレンジがたかだか25dB程度であり、送信側の
出力の大小、送受間の減衰度の大小など様々な外的条件
の変化を吸収した的確な信号受信を行い得ないという問
題点かあった。
Out [Problem to be Solved by the Invention] However, according to the above-described amplifier device, when an excessive input is applied to the photodiode 1, the amplifier device becomes saturated and becomes unsuitable for practical use. In other words, the dynamic range is approximately 25 dB at most due to saturation, making it impossible to receive signals accurately while absorbing changes in various external conditions, such as the magnitude of the output on the transmitting side and the magnitude of attenuation between the transmitter and the receiver. There was a point.

具体的には、第5図に示す回路に、第6図に示すような
3 0 0 M b p sのrOJ,rlJの繰り返
しからなるNRZ信号を、人力光電流○.  lmAで
加えた場合(c a s e 1)と人力光電流1mA
で加えた場合(case2)には、出力端子3から第7
図に示されるような出力信号が得られる。
Specifically, an NRZ signal consisting of repeating rOJ and rlJ of 300 Mbps as shown in FIG. 6 as shown in FIG. 6 is applied to the circuit shown in FIG. When added at lmA (cas e 1) and human photocurrent 1mA
(case 2), from the output terminal 3 to the 7th
The output signal shown in the figure is obtained.

つまり、第7図に明らかな如く、caselでは出力信
号に大きな歪みはみられないが、Case2では出力信
号が大きく歪み、もはや人力信号を再生するのが不可能
に近いことがわかる。
In other words, as is clear from FIG. 7, there is no significant distortion in the output signal in Case 2, but the output signal in Case 2 is so distorted that it is almost impossible to reproduce the human input signal.

上記現象を詳しく解折するために、第5図の各FETQ
  −04のドレイン・ソース間電圧をモ1 ニタし、FETQ  ,Q3のゲート・ソース間電■ 圧をモニタした結果を第8図(a),(b) 、第9図
(a),(b)に示す。これらの図において、記号Q 
 −Q  は第5図の各FETQ  −Q4に14  
                   t対応する曲
線を示す。これらの図から、入力光電流lPDが所定値
を越え、これに伴って出力電圧値V  が所定値を越え
るようになると、増幅器2out を構成するFET中にはドレイン・ソース間電圧がFE
Tの非飽和領域(この例ではIV以下)に入るものが生
じたり、ゲート・ソース間電圧がFETのスレッショー
ルド電圧(ピンチオフ電圧で、この例では−IV)近く
になるものが生じることから、増幅装置の出力信号が大
きく歪むことがわかる。
In order to analyze the above phenomenon in detail, each FETQ in Fig.
The results of monitoring the drain-source voltage of FET-04 and the gate-source voltage of FETQ and Q3 are shown in Figures 8(a) and (b), and Figures 9(a) and (b). ). In these figures, the symbol Q
-Q is 14 for each FET Q -Q4 in Figure 5.
t shows the corresponding curve. From these figures, when the input photocurrent lPD exceeds a predetermined value and accordingly the output voltage value V exceeds a predetermined value, the drain-source voltage in the FET constituting the amplifier 2out becomes FE.
This is because some cases may fall into the non-saturation region of T (less than IV in this example), or the gate-source voltage may become close to the FET threshold voltage (pinch-off voltage, -IV in this example). , it can be seen that the output signal of the amplifier is greatly distorted.

そこで本発明は、過大入力時の飽和特性が改善され、大
きな人力光電流が到来したときにも歪みのない出力信号
を得ることができ、先通信に用いた場合には送信側の出
力の大小、送受間の減衰度の大小など様々な外的条件の
変化を、光減衰器等を用いることなく吸収し得る増幅装
置を提供することを目的とする。
Therefore, the present invention improves the saturation characteristics at the time of excessive input, makes it possible to obtain an output signal without distortion even when a large human-powered photocurrent arrives, and when used for communication, the magnitude of the output on the transmitting side It is an object of the present invention to provide an amplifying device that can absorb changes in various external conditions, such as the magnitude of attenuation between transmitting and receiving, without using an optical attenuator or the like.

〔課題を解決するための手段〕[Means to solve the problem]

本発明に係る増幅装置は、帰還抵抗が接続されたトラン
スインピーダンス型増幅器ゲート手段とを有し、このゲ
ート手段は上記帰還抵抗に並列接続されるとともに、ゲ
ートを有し、トランスインピーダンス型増幅器の入出力
間の電位差に基づき上記ゲートの制御を行うよう構成さ
れていることを特徴とする。
The amplifier device according to the present invention has a transimpedance amplifier gate means connected to a feedback resistor, the gate means is connected in parallel to the feedback resistor, has a gate, and has an input gate of the transimpedance amplifier. The present invention is characterized in that the gate is controlled based on the potential difference between the outputs.

〔作用〕[Effect]

本発明に係るj!!7幅装置は、以上の通りに構戊され
るので、トランスインピーダンス型増幅器に過大な人力
が到来すると、このi曽幅器の人出力間の電位差が大き
くなるためこれに基づきゲートを制御することができ、
ゲート手段が帰還抵抗に並列に接続されているので、ゲ
ート手段がバイパスルートとなり、出力電圧が所定電圧
以下には低下しなくなり、増幅装置の飽和の度合を弱く
できる。
j! according to the present invention! ! Since the 7-width device is configured as described above, when excessive human power arrives at the transimpedance type amplifier, the potential difference between the human outputs of this i-span amplifier becomes large, so the gate is controlled based on this. is possible,
Since the gate means is connected in parallel to the feedback resistor, the gate means serves as a bypass route, so that the output voltage does not fall below a predetermined voltage, and the degree of saturation of the amplifier device can be reduced.

〔実施例〕〔Example〕

以下、添付図面の第1図ないし第3図を参照して本発明
の一実施例に係る増幅装置を説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An amplifier device according to an embodiment of the present invention will be described below with reference to FIGS. 1 to 3 of the accompanying drawings.

なお、図面の説明において、同一の要素には同一の符号
を付し、重複する説明を省略する。
In addition, in the description of the drawings, the same elements are given the same reference numerals, and redundant description will be omitted.

第1図は本発明の一実施例に係る増幅装置の構成を示す
。この実施例では、帰還抵抗Rrに並列にゲートを有す
るゲート手段であるエンハンスメント型のFETQ5を
接続した。そして、FETQ5のソースが出力端子3に
接続され、ドレイン及びゲートがま曽幅器2の入力端子
に接続される。
FIG. 1 shows the configuration of an amplifier device according to an embodiment of the present invention. In this embodiment, an enhancement type FET Q5 having a gate is connected in parallel to the feedback resistor Rr. The source of the FET Q5 is connected to the output terminal 3, and the drain and gate are connected to the input terminal of the amplifier 2.

このような構成の増幅装置において、入力光電流iPD
が増加し帰還抵抗R,を流れる電流が増加すると、増幅
器2の入出力間の電α差が増大する。
In an amplifier with such a configuration, the input photocurrent iPD
As the current flowing through the feedback resistor R increases, the difference in voltage between the input and output of the amplifier 2 increases.

一方、帰還抵抗Rrに並列に接続されているエンハンス
メント型のFETQ5のゲート・ソース間電圧は、上記
電位差に等しくなっている。従って、人力光電流’ P
Dが1曽加して増幅器2の人出力間電圧(FETQ5の
ゲート・ソース間電圧)がスレッショールド電圧を越え
ると、ドレイン・ソース間に電流が流れはじめる。この
ため、FETQ5が帰還抵抗Rrのバイパスルートとし
て働く。この結果、出力電圧V  の低下が所定以下へ
進むOut ことがな<、1曽幅器2の飽和の度合を抑えることがで
きる。
On the other hand, the gate-source voltage of the enhancement type FET Q5 connected in parallel to the feedback resistor Rr is equal to the above potential difference. Therefore, the human photocurrent 'P
When D is increased by 1 and the voltage between the human outputs of the amplifier 2 (voltage between the gate and source of FET Q5) exceeds the threshold voltage, a current begins to flow between the drain and source. Therefore, FETQ5 functions as a bypass route for feedback resistor Rr. As a result, the output voltage V does not decrease below a predetermined level, and the degree of saturation of the 1-segment divider 2 can be suppressed.

第2図には、第5図の従来例に対応し、IC化できる実
施例が示されている。
FIG. 2 shows an embodiment that corresponds to the conventional example shown in FIG. 5 and can be implemented as an IC.

この実施例において、FETQ  −Q4はデイ1 プレッション型でありスレッショールド電圧はいずれも
ーTVとし、それぞれのFETのゲート幅を順に150
μm,75μm,150μm,150umとした。また
、FETQ5はエン/Xンスメント型であり、スレツシ
ョールド電圧は+0,2Vとし、ゲート幅を20μmと
した。また、帰還抵抗R『の抵抗値は2KΩである。
In this example, FETQ -Q4 is a day 1 compression type, the threshold voltage is set to -TV, and the gate width of each FET is set to 150
μm, 75 μm, 150 μm, and 150 μm. Further, FETQ5 was an enhancement type, had a threshold voltage of +0.2V, and a gate width of 20 μm. Further, the resistance value of the feedback resistor R' is 2KΩ.

このような構成の回路に、第6図に示すような3 0 
0 M b p sのrOJ,rlJの繰り返しからな
るNRZ信号を加えた。ここでも、人力光電流が0.1
mAのときをeaselとし、1mAのときをcase
2とする。この結果、出力端子3からは第3図に示され
るような出力信号を得ることができた。即ち、土曽幅器
2が飽和しない場合(c a s e 1)では従来と
同様に入力信号を太きく歪ませることなく出力信号を得
ることができ、かつ、従来では飽和して入力信号の再生
が不可能となる場合(c a s e 2)でも、この
実施例では人力信号を大きく歪ませることなく出力を得
ることができた。つまり、従来の飽和時の出力波形のパ
ルス幅歪みを大幅に補正できた。この増幅装置を用いる
と、ダイナミックレンジが広いため、光通信の信号の大
小変動を光減衰器等の他の部品を用いることなく吸収で
きる。
In a circuit with such a configuration, 30 as shown in FIG.
An NRZ signal consisting of rOJ, rlJ repetitions of 0 Mbps was applied. Here again, the human photocurrent is 0.1
When it is mA, it is called ease, and when it is 1mA, it is called case.
Set it to 2. As a result, an output signal as shown in FIG. 3 could be obtained from the output terminal 3. That is, when the Dosso width transducer 2 is not saturated (case 1), an output signal can be obtained without heavily distorting the input signal as in the conventional case, and in the case where the input signal is not saturated in the conventional case Even in the case where reproduction becomes impossible (case 2), in this example, an output could be obtained without greatly distorting the human input signal. In other words, it was possible to significantly correct the conventional pulse width distortion of the output waveform at saturation. When this amplifier device is used, since it has a wide dynamic range, it is possible to absorb fluctuations in the magnitude of optical communication signals without using other components such as an optical attenuator.

〔発明の効果〕〔Effect of the invention〕

以上、詳細に説明したように本発明によれば、トランス
インピーダンス型増幅器の人出力間の電位差が所定以上
となったとき、ゲートが制御されてゲート手段がバイパ
スルートとなって出力電圧の低下を防止するように働く
ので、増幅器の飽和度が弱められ、大きな人力光電流が
到来しても歪みのない出力信号を得ることができる。従
って、本発明の装置を光通信に用いた場合には、送信側
の出力の大小、送受間の減衰度の大小など様々な外的条
件の変化を、他の構成を用いることなしに吸収できる。
As described above in detail, according to the present invention, when the potential difference between the human outputs of the transimpedance amplifier exceeds a predetermined value, the gate is controlled and the gate means becomes a bypass route to prevent the output voltage from decreasing. Since the saturation of the amplifier is weakened, it is possible to obtain an output signal without distortion even when a large manual photocurrent arrives. Therefore, when the device of the present invention is used for optical communication, it is possible to absorb changes in various external conditions, such as the magnitude of the output on the transmitting side and the magnitude of the attenuation between the transmitter and the receiver, without using any other configuration. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例に係る増幅装置の構成図、第
2図はFETを用いて構成した他の実施例に係る増幅装
置の回路図、第3図は第2図の装置の出力信号を示す図
、第4図および第5図は従来の増幅装置の構成図、第6
図は入力光信号の例を示す図、第7図は第5図の従来例
による出力信号を示す図、第8図は第5図の従来例にお
けるFETのドレイン・ソース間電圧の変化を示す図、
第9図は第5図の従来例におけるゲート・ソース間電圧
を示す図である。 1・・・フォトダイオード、2・・・増幅器、3・・・
出力端子、Q ・・・ゲート手段、R,・・・帰還抵抗
、5 Q −Q5・・・FET,DI−D2・・・レベルシフ
ト1 用のダイオード。
FIG. 1 is a block diagram of an amplifier according to an embodiment of the present invention, FIG. 2 is a circuit diagram of an amplifier according to another embodiment configured using FETs, and FIG. 3 is a circuit diagram of an amplifier according to another embodiment of the invention. Figures 4 and 5 are diagrams showing output signals, and Figures 4 and 5 are configuration diagrams of conventional amplifier devices.
Figure 7 shows an example of an input optical signal, Figure 7 shows an output signal according to the conventional example shown in Figure 5, and Figure 8 shows changes in the drain-source voltage of the FET in the conventional example shown in Figure 5. figure,
FIG. 9 is a diagram showing the gate-source voltage in the conventional example shown in FIG. 1...Photodiode, 2...Amplifier, 3...
Output terminal, Q...gate means, R,...feedback resistor, 5Q-Q5...FET, DI-D2...diode for level shift 1.

Claims (1)

【特許請求の範囲】 帰還抵抗が接続されたトランスインピーダンス型増幅器
と、 前記帰還抵抗に並列に接続されるとともに、ゲートを有
し、前記トランスインピーダス型増幅器の入力間の電位
差に基づき前記ゲートの制御を行うゲート手段とを備え
たことを特徴とする増幅装置。
[Scope of Claims] A transimpedance type amplifier connected to a feedback resistor; and a gate connected in parallel to the feedback resistor, the gate being connected to the feedback resistor based on the potential difference between the inputs of the transimpedance type amplifier. An amplifying device characterized by comprising: gate means for performing control.
JP1191129A 1989-07-24 1989-07-24 Amplifier device Pending JPH0354909A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1191129A JPH0354909A (en) 1989-07-24 1989-07-24 Amplifier device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1191129A JPH0354909A (en) 1989-07-24 1989-07-24 Amplifier device

Publications (1)

Publication Number Publication Date
JPH0354909A true JPH0354909A (en) 1991-03-08

Family

ID=16269358

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1191129A Pending JPH0354909A (en) 1989-07-24 1989-07-24 Amplifier device

Country Status (1)

Country Link
JP (1) JPH0354909A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016167703A (en) * 2015-03-09 2016-09-15 株式会社東芝 Transimpedance circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016167703A (en) * 2015-03-09 2016-09-15 株式会社東芝 Transimpedance circuit

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