JPH0354831A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

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Publication number
JPH0354831A
JPH0354831A JP19076589A JP19076589A JPH0354831A JP H0354831 A JPH0354831 A JP H0354831A JP 19076589 A JP19076589 A JP 19076589A JP 19076589 A JP19076589 A JP 19076589A JP H0354831 A JPH0354831 A JP H0354831A
Authority
JP
Japan
Prior art keywords
region
film
base
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19076589A
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Japanese (ja)
Inventor
Masabumi Kunii
正文 国井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
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Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP19076589A priority Critical patent/JPH0354831A/en
Publication of JPH0354831A publication Critical patent/JPH0354831A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To manufacture a heterojunction bipolar transistor in high performances by a method wherein, within a semiconductor device having an emitter region in wider forbidden band width than that of a region, the semiconductor layer in the base region is composed of recrystallized thin film semiconductor. CONSTITUTION:An SiO2 film 101 is formed on an n/n<+> type Si substrate 100. Next, an opening corresponding to a base region is made in the SiO2 101 to form a film of p<+> type amorphous silicon (alpha-Si) 102 and successively n<+> amorphous SiC(alpha-SiC)103 to be a wide gap emitter is formed into a film. Next, the amorphous SiC 103 is patterned after an emitter region 105 to form a p-type recrystallized Si region 104 by annealing process. This region becomes a base region whose film thickness specifies a base width. Next, another SiO2 film 106 is made on the whole surface while contact holes are made by etching process finally to form pick-up electrodes 107-109.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、半導体装置及びその製造方法に関する. [従来の技術] ヘテロ接合バイボーラトランジスタ(以下、HBT)は
、エミッタ領域の禁制帯幅をベース領域の禁制帯幅より
も大きくとることにより、ベースからエミッタへキャリ
アの注入を阻止すると同時にベースのドーピング漬度を
高くしてベース抵抗を低減できるため、トランジスタの
増幅率と動作速度を増大させることができる.このため
近年HBTの開発が盛んになってきた.例えば、 「電
子材料J1987年1月号pp.71に示すようなA 
I G a A s / G a A s系H B T
SAppliedPhysics Letters v
ol.52 (10), pp.822 (1988)
に示すような GaAs/Si系HBT、   I E
KEElectron Device Letters
   vol. 9 (4),  165(1988)
,Applied Physics  Letters
  vol.52  (11),pp.895 (19
8B)等に示すような S i / G e S i系
H B T,  IEEE Electron Dev
ice Letters vol.9 (2), 87
 (1988)に示すようなβ−S i C / S 
i系HBT等様々なHBTの試作が行われている.[発
明が解決しようとする課題] A I G a A S/ G a A E3系等の化
合物半導体HBTでは、ワイドバンドギャップエミッタ
の作製に、分子線気相成長法(MBE)、有機金属化学
気相成長法(MOCVD)等を用いて結晶性の高いエミ
ツタを作製しているので高性能のHBTを作製可能な反
面、既存のSi半導体プロセスとは馴染み難く、作製装
置も高価であるという問題点を有していた.  一方、
  19B? 1EDM TechnicalDige
st pp.186−193、   1984 IED
M TechnicalDigest pp.746等
に示すように、ワイドバンドギャップエミッタを、非晶
買Si、非晶質SiCや微結晶Siで作製する試みもあ
る.この試みでは非晶買Si、非晶買SiCや微結晶S
iの作製をプラズマCVD法を用いているので比較的安
価にHBTを作製できる.しかし、以上のSi系HBT
では、ベース層をイオン打ち込み法で作製しているので
、高不純物漬度のベース層を浅い接合で作製することが
難しく、高性能化への障害となっていた。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same. [Prior Art] A heterojunction bibolar transistor (hereinafter referred to as HBT) has a forbidden band width in an emitter region larger than a forbidden band width in a base region, thereby preventing carrier injection from the base to the emitter and at the same time Since the base resistance can be reduced by increasing the doping degree, the amplification factor and operating speed of the transistor can be increased. For this reason, the development of HBT has become active in recent years. For example, A as shown in "Electronic Materials J January 1987 issue pp.71
I G a As / G a As system H B T
SAPlied Physics Letters v
ol. 52 (10), pp. 822 (1988)
GaAs/Si HBT as shown in IE
KE Electron Device Letters
vol. 9 (4), 165 (1988)
, Applied Physics Letters
vol. 52 (11), pp. 895 (19
8B) etc., Si/Ge Si-based HBT, IEEE Electron Dev
ice Letters vol. 9 (2), 87
(1988) as shown in β-S i C/S
Prototypes of various HBTs such as i-type HBTs are being produced. [Problems to be Solved by the Invention] In compound semiconductor HBTs such as the AI G a A S/ G a A E3 type, molecular beam vapor deposition (MBE) and organometallic chemical vapor deposition are used to fabricate wide bandgap emitters. Since emitters with high crystallinity are fabricated using phase epitaxy (MOCVD), etc., it is possible to fabricate high-performance HBTs, but on the other hand, there are problems in that it is difficult to adapt to existing Si semiconductor processes and the fabrication equipment is expensive. It had on the other hand,
19B? 1EDM Technical Dige
st pp. 186-193, 1984 IED
M Technical Digest pp. There are also attempts to fabricate wide bandgap emitters using amorphous Si, amorphous SiC, or microcrystalline Si, as shown in No. 746 and others. In this trial, amorphous Si, amorphous SiC and microcrystalline S were used.
Since the plasma CVD method is used to manufacture the HBT, it is possible to manufacture the HBT at a relatively low cost. However, the above Si-based HBT
Since the base layer is fabricated by ion implantation, it is difficult to fabricate a highly doped base layer with shallow junctions, which has been an obstacle to achieving higher performance.

本発明は以上の問題点を解決するもので、その目的は低
コストで高性能のHBTを提供することにある. [課題を解決するための手段コ 本発明の半導体装置は、 エミッタ領域、ベース領域、コレクタ領域を有し、エミ
ッタ領域の禁制帯幅がベース領域の禁制帯幅よりも大き
い半導体装置において、ベース領域の半導体層を再結晶
化した薄膜半導体で構成することを特徴とする. 本発明の半導体装置の製造方法は、 (1)前記薄膜半導体はアニールによる固相成長で再結
晶化することを特徴とする. (2〉前記薄膜半導体は、薄膜形或時に不純物が導入さ
れていることを特徴とする (3〉前記エミッタ領域と前記ベース領域が積層された
状態で前記固相成長アニールを行うことを特徴とする. (4)前記薄膜半導体は、プラズマ化学気相成長法また
は減圧化学気相成長法で成膜することを特徴とする. [実施例] 以下、第1図に基き本発明の半導体装置の製造方法を説
明する。本発明ではnpn型HBTの製造方法を例にと
り説明する. まず7Ω・cm(111)n/n”型Si基板100の
表面を熱酸化し、SiO2膜101を形成する(第1図
−(a)).  ベース領域に対応する場所のSiO2
膜をフォトエッチングで除き開口部を形成する(第1図
−(b)).  この上にプラズマ化学気相成長法(P
CVD)p”型非晶買シリコン(a−Si)102を約
500〜700人成膜し、続いて成膜ガスを切り換えワ
イドバンドギャップエミッタとなるn゛型非晶質SiC
 (a−SiC)103を約500〜IOOOA成膜す
る(第1図−(c)).p−型a−Si  102の成
膜ガスにはSiHaとB2H6の混合ガスを用い、n″
型a−SiC  103の成膜ガスにはSiH4、CH
J、PH3の混合ガスを用いた.B及びP原子のドーピ
ング漬度はいずれも1×10111以上の高漬度ドーピ
ングとなるようにガス流量比を調整した,  a −S
i,a−SiC層とも、周波数13.56MHzの高周
波を印加し、高周波電力は3 0 m W / cm2
、基板温度は180〜250゜Cである。基板温度が4
50℃以上でa−Siを成膜した場合は、膜中の水素含
有量が減るので、以下に述べるブリアニールの必要はな
くなるが、膜の緻密化を促進させるためにはブリアニー
ルを行った方が望ましい.ワイドバンドギャップエミッ
タには  a −SiC以外に、非晶質窒化シリコン(
a−SiN)、微結晶Si(μc−Si)等を用いるこ
ともできる,a−SiNの成膜にはSiHa、N20 
(またはN2、N H 3等)の混合ガスを用いる。ド
ーピングガスにはP H 3を使う。μc−Siの成膜
は、SiH4ガスをH2ガステ希釈し、  300mW
/cm’の高周波電力をかけて作製する。ドーピングガ
スはこの場合もPH3を用いる,PCVDの場合はa−
Si成膜直前にH2プラズマまたはArプラズマ処理を
行えば、基板表面の清浄化と成膜とを連続的に行うこと
ができる,a−Siの成膜には減圧化学気相成長法(L
PGVD)を用いることも可能である,LPCVDの場
合は基板温度がなるべく低く成膜速度がなるべく速い条
件が適している。a−Siの原料ガスにS i H 4
を用いる場合は500〜560℃、Si2Hsを用いる
場合は300〜500℃が望ましい.基板温度がこれ以
上高くなると、堆積した膜が多結晶となり固相成長を妨
げるので望ましくない.ドーピングガスにはPCVDと
同様B2H6を用いる. 次いでp″a−Siをベース領域の形にバタニング後、
n″a−SiCをエミッタ領域105の形にバタニング
する(第1図−(d)).  この状態で基板をN2中
450℃で3 0 m i n.  ブリアニールし、
膜中の水素を脱離させると同時に膜の緻密化を図る。ブ
リアニール後、 500〜600℃のN2中で8〜72
時間アニールしてa−Si膜を固相成長させて再結晶化
させる(第1図一(e)).アニール装置には石英管に
よる炉アニールがよい。
The present invention solves the above problems, and its purpose is to provide a low-cost, high-performance HBT. [Means for Solving the Problems] The semiconductor device of the present invention has an emitter region, a base region, and a collector region, and the emitter region has a larger forbidden band width than the base region. The semiconductor layer is composed of a recrystallized thin film semiconductor. The method for manufacturing a semiconductor device of the present invention is characterized in that: (1) the thin film semiconductor is recrystallized by solid phase growth using annealing; (2) The thin film semiconductor is characterized in that it is a thin film and impurities are sometimes introduced. (3) The solid phase growth annealing is performed in a state where the emitter region and the base region are laminated. (4) The thin film semiconductor is characterized in that it is formed by a plasma chemical vapor deposition method or a low pressure chemical vapor deposition method. [Example] Hereinafter, based on FIG. 1, the semiconductor device of the present invention will be described. The manufacturing method will be explained. In the present invention, the manufacturing method of an npn type HBT will be explained as an example. First, the surface of a 7 Ω cm (111) n/n'' type Si substrate 100 is thermally oxidized to form a SiO2 film 101 ( Figure 1-(a)). SiO2 at the location corresponding to the base region
The film is removed by photo-etching to form an opening (Figure 1-(b)). On top of this, plasma chemical vapor deposition (P
CVD) p" type amorphous silicon (a-Si) 102 is deposited by approximately 500 to 700 people, and then the deposition gas is changed to deposit n" type amorphous SiC, which will become a wide bandgap emitter.
(a-SiC) 103 is deposited to a thickness of about 500 to IOOOA (Fig. 1-(c)). A mixed gas of SiHa and B2H6 was used as the film forming gas for p-type a-Si 102, and n″
The film forming gas for type a-SiC 103 contains SiH4, CH
A mixed gas of J and PH3 was used. The gas flow rate ratio was adjusted so that the doping degree of B and P atoms was high doping of 1 × 10111 or more, a-S.
A high frequency of 13.56 MHz was applied to both the i and a-SiC layers, and the high frequency power was 30 mW/cm2.
, the substrate temperature is 180-250°C. The board temperature is 4
If the a-Si film is formed at 50°C or higher, the hydrogen content in the film decreases, so there is no need for the briane annealing described below, but it is better to perform the briane annealing to promote film densification. desirable. In addition to a-SiC, amorphous silicon nitride (
a-SiN), microcrystalline Si (μc-Si), etc. can also be used. For a-SiN film formation, SiHa, N20
(or N2, NH3, etc.) mixed gas is used. P H 3 is used as the doping gas. To form a μc-Si film, SiH4 gas was diluted with H2 gas and the power was 300mW.
/cm' high frequency power is applied. PH3 is used as the doping gas in this case as well, and in the case of PCVD, a-
If H2 plasma or Ar plasma treatment is performed immediately before Si film formation, cleaning of the substrate surface and film formation can be performed continuously.
It is also possible to use PGVD. In the case of LPCVD, conditions are suitable where the substrate temperature is as low as possible and the film formation rate is as fast as possible. S i H 4 in the raw material gas of a-Si
When using Si2Hs, the temperature is preferably 500 to 560°C, and when using Si2Hs, the temperature is preferably 300 to 500°C. If the substrate temperature becomes higher than this, the deposited film will become polycrystalline, which will impede solid-phase growth, which is undesirable. B2H6 is used as the doping gas as in PCVD. Then, after batting the p″a-Si into the shape of the base region,
The n″a-SiC is battened into the shape of the emitter region 105 (FIG. 1-(d)). In this state, the substrate is annealed in N2 at 450° C. for 30 min.
The hydrogen in the film is removed and at the same time the film is made denser. 8-72 in N2 at 500-600℃ after Briannealing
The a-Si film is grown in solid phase by time annealing and recrystallized (Fig. 1(e)). A suitable annealing device is a furnace annealing using a quartz tube.

アニール雰囲気にはN2以外には、 H2、 Ar,H
e等が望ましいが、1xlO−’〜lxlo一目Tor
r程度の高真空中でアニールしてもよい.固相成長の初
期はSi基板をシードとして、ベース領域開口部上のa
−Si膜の垂直方向に進むが、再結晶化領域がSiO2
膜上に到達すると横方向の固相成長が進む. このよう
にしてp型再結晶化Si領域104ができる,この領域
がベース領域となり、その膜厚はベース幅となる.この
上にLPCVDでSiO2膜を成膜し、ついでコンタク
トホールをエッチングして作製する.最後に取り出し電
極107〜109を形成し、パタニングして完成となる
(第1図−(f)). 電極材料にはA1、Al−Si
−Cu.Au,’ri等の金属を用いる. 以上述べたように本発明の半導体装置の製造方法によれ
ば、ドーブトa−Siを500〜600゜Cという低温
で固相成長させるので、700A程度という薄いベース
幅ながらきわめて急峻な不純物漬度分布を持つたベース
ーコレクタ接合を実現することが可能になる.ベース層
の接合深さは、p型a−Si薄膜の膜厚で決まり、しか
もベース中の不純物濃度は成膜時のドーピングガス流量
で決まるので、イオン打ち込み法と比較するとはるかに
簡単かつM密なベース漬度、ベース接合深さの制御が可
能である。不純物原子の活性化率は、固相成長が完了し
ている場合はほぼ100%になる.更に、PCVD,L
PCVD法は共に大面積に均一にa−Si膜を成膜する
ことが可能なので、スルーブットも飛躍的に増大する。
In addition to N2, the annealing atmosphere contains H2, Ar, H
e etc. are desirable, but 1xlO-'~lxlo Ichimoku Tor
Annealing may be performed in a high vacuum of about r. At the initial stage of solid phase growth, the Si substrate is used as a seed, and a
- Proceeds in the vertical direction of the Si film, but the recrystallized region is SiO2
Once it reaches the membrane, lateral solid-phase growth progresses. In this way, a p-type recrystallized Si region 104 is formed. This region becomes a base region, and its film thickness becomes the base width. A SiO2 film is formed on this by LPCVD, and then a contact hole is formed by etching. Finally, extraction electrodes 107 to 109 are formed and patterned to complete the process (FIG. 1-(f)). Electrode materials include A1, Al-Si
-Cu. Metals such as Au and 'ri are used. As described above, according to the method for manufacturing a semiconductor device of the present invention, since doped a-Si is grown in solid phase at a low temperature of 500 to 600°C, an extremely steep impurity concentration distribution can be achieved despite the thin base width of about 700A. It becomes possible to realize a base-collector junction with a The junction depth of the base layer is determined by the thickness of the p-type a-Si thin film, and the impurity concentration in the base is determined by the doping gas flow rate during film formation, so it is much simpler and M denser than the ion implantation method. It is possible to control the degree of soaking in the base and the depth of base bonding. The activation rate of impurity atoms is almost 100% when solid phase growth is completed. Furthermore, PCVD,L
Since both PCVD methods can uniformly form an a-Si film over a large area, the throughput can also be dramatically increased.

またPCVD法を用いる場合はa−Siと、a−SiC
(a−SiN,  μc−Si)膜を連続して形成でき
るので、良好なベースーエミッタ間へテロ界面を容易に
実現できる. 本実施例ではnpnトランジスタを例にとって説明した
が、Si基板にp/p”型ウェ八 あるいはpウェル構
造を用いれば、pnp型トランジス夕も同様に作製でき
るのはもちろんである.また本プロセスは、Si系半導
体に限らすGe.Si−Ge等や、GaAs、InAs
等の化合物半導体プロセスにも適用可能である. [発明の効果] 本発明によれば、浅いベース厚ながらきわめて急峻なベ
ース漬度分布を持つたベースーコレクタ接合を容易に実
現できる.このため、理想的な薄ベース厚、高ベース温
度をもったHBTを作製でき、HBTの高性能化、低コ
スト化に絶大な寄与を果たす.本プロセスは、従来のS
i半導体プロセスとの適合性が高いので、HBTだけで
はなく、MOS型トランシスタ、Bi−CMOSIC、
フォ・トトランジスタ、サイリスタ等の半導体素子全般
への応用が可能である.
In addition, when using the PCVD method, a-Si and a-SiC
Since the (a-SiN, μc-Si) films can be formed continuously, a good base-emitter heterointerface can be easily achieved. Although this example has been explained using an npn transistor as an example, it goes without saying that a pnp type transistor can also be manufactured in the same way by using a p/p'' type wafer or p well structure on the Si substrate. , limited to Si-based semiconductors such as Ge.Si-Ge, GaAs, InAs
It can also be applied to compound semiconductor processes such as [Effects of the Invention] According to the present invention, it is possible to easily realize a base-collector junction that has a very steep base immersion distribution even though the base thickness is shallow. Therefore, it is possible to fabricate an HBT with an ideal thin base thickness and high base temperature, making a tremendous contribution to improving the performance and lowering the cost of HBTs. This process is similar to the conventional S
It is highly compatible with the i-semiconductor process, so it can be used not only for HBTs but also for MOS type transistors, Bi-CMOSICs,
It can be applied to general semiconductor devices such as phototransistors and thyristors.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の半導体装置の製造工程を示す図.10
0・・・・・・・・・n / r1″ Si基板101
・・・・・・・・・熱酸化Sio2膜102・・・・・
・・・・p″a−Si膜O3・・・・・・・・・n”a
−SiC膜04・・・・・・・・・p゛再結晶化SiO
5・・・・・・・・・エミッタ領域 0 6・・・・・・・・・LPCVD O7・・・・・・・・・ベース電極 08・・・・・・・・・エミッタ電極 09・・・・・・・・・コレクタ電極 SiO2膜 以上
FIG. 1 is a diagram showing the manufacturing process of the semiconductor device of the present invention. 10
0......n/r1'' Si substrate 101
......Thermal oxidation Sio2 film 102...
・・・・p″a-Si film O3・・・・・・・・・n”a
-SiC film 04・・・・・・・・・p゛Recrystallized SiO
5......Emitter region 0 6......LPCVD O7...Base electrode 08...Emitter electrode 09.・・・・・・Collector electrode SiO2 film or more

Claims (5)

【特許請求の範囲】[Claims] (1)エミッタ領域、ベース領域、コレクタ領域を有し
、エミッタ領域の禁制帯幅がベース領域の禁制帯幅より
も大きい半導体装置において、ベース領域の半導体層を
再結晶化した薄膜半導体で構成することを特徴とする半
導体装置。
(1) In a semiconductor device that has an emitter region, a base region, and a collector region, and the forbidden band width of the emitter region is larger than the forbidden band width of the base region, the semiconductor layer in the base region is composed of a recrystallized thin film semiconductor. A semiconductor device characterized by:
(2)前記薄膜半導体はアニールによる固相成長で再結
晶化することを特徴とする請求項1記載の半導体装置の
製造方法。
(2) The method of manufacturing a semiconductor device according to claim 1, wherein the thin film semiconductor is recrystallized by solid phase growth using annealing.
(3)前記薄膜半導体は、薄膜形成時に不純物が導入さ
れていることを特徴とする請求項1記載の半導体装置の
製造方法。
(3) The method of manufacturing a semiconductor device according to claim 1, wherein impurities are introduced into the thin film semiconductor during formation of the thin film.
(4)前記エミッタ領域と前記ベース領域が積層された
状態で前記固相成長アニールを行うことを特徴とする請
求項1記載の半導体装置の製造方法。
(4) The method of manufacturing a semiconductor device according to claim 1, wherein the solid phase growth annealing is performed in a state where the emitter region and the base region are stacked.
(5)前記薄膜半導体は、プラズマ化学気相成長法また
は減圧化学気相成長法で成膜することを特徴とする請求
項1記載の半導体装置の製造方法。
(5) The method for manufacturing a semiconductor device according to claim 1, wherein the thin film semiconductor is formed by plasma chemical vapor deposition or low pressure chemical vapor deposition.
JP19076589A 1989-07-24 1989-07-24 Semiconductor device and manufacture thereof Pending JPH0354831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19076589A JPH0354831A (en) 1989-07-24 1989-07-24 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19076589A JPH0354831A (en) 1989-07-24 1989-07-24 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0354831A true JPH0354831A (en) 1991-03-08

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Family Applications (1)

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JP19076589A Pending JPH0354831A (en) 1989-07-24 1989-07-24 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH0354831A (en)

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