JPH0354481B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a pulse width modulation amplifier having an output stage pulse amplifier having a BTL configuration.
In particular, the present invention relates to a pulse width modulation amplifier in which feedback is applied in a novel manner.

A pulse width modulation amplifier converts an input signal, such as an audio signal, into a pulse signal with a duty ratio according to its amplitude, efficiently amplifies it in the form of a pulse signal, and then demodulates it to obtain an amplified output. This is what I did. In such a pulse width modulation amplifier, it is usually essential to apply negative feedback to reduce distortion.

By the way, if it is desired to further improve the power usage efficiency in this type of pulse width modulation amplifier, it is conceivable to configure the output stage pulse amplifier to have a BTL configuration. However, when a BTL configuration is adopted, the output becomes balanced (that is, the output becomes symmetrical with respect to the ground potential), so negative feedback cannot be applied to a normal unbalanced input stage. is not possible. In this case, BTL
It is conceivable to provide an input stage for each pulse amplifier in the configured output stage and apply negative feedback between each output stage and the input stage, but this configuration has the problem that the circuit becomes extremely complex. There is.

This invention has been made in view of the above circumstances, and its purpose is to provide a simple circuit configuration when the pulse amplifier in the output stage is configured as a BTL configuration, while still allowing the output signal to remain in the form of a pulse signal. An object of the present invention is to provide a pulse width modulation amplifier that can provide stable feedback. The feature of this invention is to add the integrated signal of the output of the second pulse amplifier in the BTL output stage to the input signal to be amplified, and to supply this addition result to the non-inverting input terminal of the amplifier that constitutes the Miller integration circuit. On the other hand, the first
The output of the pulse amplifier is supplied to the inverting input terminal of this amplifier and integrated, and the output of this amplifier is compared with the carrier signal by a comparator, and the comparison output is used to control the first and second pulse amplifiers. It is designed to be driven.

Hereinafter, one embodiment of a pulse width modulation amplifier according to the present invention will be described in detail with reference to the drawings.

First, to describe the schematic configuration of the pulse width modulation amplifier shown in FIG. This is an operational amplifier (amplifier) that constitutes an integrating circuit.
Reference numeral 4 is a comparator that compares the output of the operational amplifier 2 with the carrier signal ec, numeral 5 is a first pulse amplifier that amplifies the output of the comparator 4 in the same phase, and numeral 6 is the comparator. This is a second pulse amplifier that amplifies the output of No. 4 in reverse phase. The first and second pulse amplifiers 5 and 6 are BTL connected to drive both ends of the load 7 with output signals having opposite phases to each other. Furthermore, the output of the pulse amplifier 5 is negatively fed back to the inverting input terminal of the operational amplifier 2 via the resistor 8, and the output of the pulse amplifier 6 is fed back to the non-inverting input terminal of the operational amplifier 2 via the resistor 9. It's getting old.

The configuration of this pulse width modulation amplifier will be described in detail below. Reference numeral 10 is a signal input terminal to which an input signal ei is supplied. This signal input terminal 10 is connected to the non-inverting input side of an operational amplifier 11 constituting the buffer amplifier 1, and is also grounded via a resistor 12. The inverting input terminal and output terminal of the operational amplifier 11 are directly connected, and the output terminal is connected to the resistor 13.
(first impedance element, value R ₁ ) to the non-inverting input terminal of the operational amplifier 2 (amplifier). The inverting input terminal of this operational amplifier 2 is grounded via the capacitor 14 (first capacitive element, value C ₁ ), and the inverting input terminal of the operational amplifier 2 is
Resistor 15 (second impedance element, value R′ ₁ )
It is connected to the output terminal of the operational amplifier 2 via the capacitor 3 (second capacitive element, value C ₂ ), and the output terminal is connected to the input terminal of the comparator 4. A triangular wave carrier signal ec is supplied to the input terminal of the comparator 4 from a carrier signal source 16. In this case, the frequency of the carrier signal ec is set to a constant value that is sufficiently higher than the upper limit frequency of the input signal ei. The output of this comparator 4 is sent to a non-inverting pulse amplifier 5.
(the first pulse amplifier), and is also supplied to the input terminal of the inverted pulse amplifier 6 (the second pulse amplifier). and,
The output terminal of the pulse amplifier 5 is connected to one end of the load 7 via one winding 18a of the transformer 18 and the signal output terminal 19a, and the output terminal of the pulse amplifier 6 is connected to the other winding 18b of the transformer 18. It is connected to the other end of the load 7 via the signal output terminal 19b in sequence. Also, signal output terminals 19a, 19b
A capacitor 20 is inserted between them. In this case, a portion consisting of the transformer 18 and the capacitor 20 constitutes a filter circuit 21 that blocks carrier signal components in the output signals of the pulse amplifiers 5 and 6. On the other hand, the output terminal of the pulse amplifier 5 is connected to the inverting input terminal of the operational amplifier 2 via a resistor 8 (third impedance element, value R' ₂ ), and the output terminal of the pulse amplifier 6 is connected to the inverting input terminal of the operational amplifier 2.
(fourth impedance element, value _R2 ) to the non-inverting input terminal of the operational amplifier 2.
Note that in this embodiment, the pulse amplifiers 5 and 6
are supplied with power supply voltages +E and -E, respectively, and have a time constant determined by resistor 9 and capacitor 14.
The time constant C ₂ ·R' 2 determined by C ₁ ·R ₂ and the resistor 8 and capacitor ₃ is set to a value sufficiently large with respect to the period of the carrier signal ec.

Next, the operation of this embodiment with the above configuration will be explained with reference to the time chart shown in FIG.

First, the voltage of the output signal of the operational amplifier 11 is equal to the voltage of the input signal ei. The output signal of the operational amplifier 11 is supplied to the non-inverting input terminal of the operational amplifier 2 via the resistor 13, but in this case, the time constant C1· _R1 determined by the resistor ₁₃ and the capacitor 14 is the input signal ei. Since the period of the upper limit frequency is sufficiently small, the voltage of the signal e ₁ obtained at the non-inverting input terminal is approximately equal to the voltage of the input signal ei.

Now, suppose that the input signal ei is a positive voltage as shown in FIG. 2A. In this case, the voltage of the signal _e1 is approximately equal to the voltage of the input signal ei, as described above. Here, at time _{t 0} shown in FIG _. > ec. In this case, since the output signal e ₃ of the comparator 4 is at a high level, the output signal e ₄ of the pulse amplifier 5
is approximately a voltage E as shown in FIG. 2D, and the output signal ₄ of the pulse amplifier 6 is approximately a voltage -E as shown in FIG. 2E. In this case, since signal ₄ is integrated by resistor 9 and capacitor 14,
The voltage of signal e ₁ has a time constant as shown in Figure 2 (b).
It descends at a slope determined by C ₁ and R ₂ . However, the amount of change in this signal _e1 is extremely small (the voltage axis of the waveform in FIG. 2B is enlarged). On the other hand, the voltage of the signal e' ₁ at the inverting input terminal of the operational amplifier 2 is always equal to the voltage of the signal e' 1 due to the nature of the operational amplifier with negative feedback, and the voltage of the signal e' ₁ at the inverting input terminal of the operational amplifier 2 is always equal to the voltage of the signal e' ₁ . A current i determined by Therefore,
In this case, the voltage E of the signal e ₄ and the signal e' ₁ are applied to the resistor 8.
voltage (i.e. approximately equal to the voltage of signal ei)
A current flows due to the difference between the two, and a current obtained by subtracting the current i from this current flows into the output terminal of the operational amplifier 2 via the capacitor 3. As a result, the signal e ₂
The voltage decreases at a constant slope as shown in FIG. 2C.

Next, assume that at time _t1 , the voltage relationship between the signal _e2 and the signal ec is reversed to _e2 <ec. In this case, signal e ₃ goes from high level to low level, so signal e ₄ changes from voltage +E to voltage -E and again
e ₄ respectively transition from voltage -E to voltage +E. As a result, a current flows through the resistor 8 due to the difference between the voltage of the signal e' ₁ and the voltage -E of the signal _e4 , and a current obtained by adding the current i to this current flows through the capacitor 3 to the output of the operational amplifier 2. The current flows from the terminal toward the connection point between the resistors 8 and 15. As a result, the voltage of signal e ₂ is
As shown in period _T1 in Figure C, it rises at a constant slope.
On the other hand, during this period _T1 , signal ₄ is at voltage +E
Therefore, as shown in Figure 2 (b), the signal e ₁
also rises with a slope determined by the time constant C ₁ .R ₂ .

Next, assume that the period T ₁ has elapsed and the voltage relationship between the signal e ₂ and the signal e _c has reversed to e ₂ >ec. In this case, signal e ₃ goes from low level to high level, so signal e ₄ changes from voltage -E to voltage +E and again.
e ₄ respectively transition from voltage +E to voltage -E. As a result, a current flows through the resistor 8 due to the difference between the voltage +E of the signal _e4 and the voltage of the signal _e'1 , and the current obtained by subtracting the current i from this current flows through the capacitor 3 to the output terminal of the operational amplifier 2. flows into. As a result, the voltage of the signal _e2 falls at a constant slope as shown in period _T2 in FIG. 2C. On the other hand, during this period _T2 , since the signal ₄ is at the voltage -E, the signal _e1 also falls at a slope determined by the time constant _C1.R2 , as shown in FIG. _2B .

Then, after this period T ₂ has elapsed, the voltage relationship between the signal e ₂ and the signal e _c is reversed again, and the above-described operation is repeated in the same manner.

That is, according to this embodiment, the signal _e2 is a triangular wave whose rising slope and falling slope change according to the voltage of the input signal ei, and whose frequency is equal to the frequency of the carrier signal ec, so that the output signal
As e ₄ and ₄ , it is possible to obtain a pulse signal whose frequency is equal to the frequency of the carrier signal ec and whose duty ratio is proportional to the amplitude of the input signal ei, and distortion is significantly reduced by the negative feedback effect of the resistor 8. Ru. Further, according to this embodiment, by providing the resistor 9 and the capacitor 14, the signal e ₁ at the non-inverting input terminal of the operational amplifier 2 is an integral signal of the signal e ₄ in the input signal ei, that is, the inverse of the input signal ei. Since the signal is a sum of analog signals having a phase relationship (that is, negative feedback has been applied), distortion is further reduced by this negative feedback effect.

The signals e ₄ and ₄ obtained in the above manner are demodulated via the filter circuit 21 and output as an output signal.
e ₀ , ₀ , and is supplied to both ends of the load 7. In this case, the signal e ₀ and the signal ₀ are in an antiphase relationship with each other. Note that, according to the present invention, the carrier signal
It consists of a loop in which the comparison output of ec and the integral signal _e2 is negatively fed back to the operational amplifier 2. Therefore, when the waveform of the carrier signal ec is distorted, depending on the change in the pulse width of the signal _e3 output from the comparator 4,
The slope of the signal e ₂ of the operational amplifier 2 changes. Then, in comparator 4, a signal whose slope has changed is
By comparing e ₂ and the distorted carrier signal ec, the loop is stabilized when the pulse width of the signal e ₃ corresponds to the input signal ei. Therefore, the output signal eo does not depend on the waveform of the carrier signal ec,
It is sufficient that the carrier signal ec has periodicity at the point of zeroxing. Therefore, in the above explanation, the carrier signal ec has been explained as a triangular wave, but a sine wave or the like can also be used as the carrier signal ec.

Next, the gain between the signal input terminal 10 and the signal output terminals 19a and 19b in this embodiment
Consider G _V. Also, the time constants C ₁ R ₂ , C ₂ R′ ₂
is sufficiently large with respect to the period of the carrier signal ec, so considering only the analog signal, since the signal e ₁ and the signal e' ₁ are equal, R ₁ e ₀ + R ₂ ei/R ₁ + R ₂ = R′ ₁ e ₀ /R′ ₁ +R′ ₂ ...(1) The following relationship holds true. Here, since the signal ₀ is the opposite phase signal of the signal e ₀ , the above equation (1) is: −R ₁ e ₀ +R ₂ ei/R ₁ +R ₂ =R′ ₁ e ₀ /R ₁ ′+R′ ₂ ...(2) becomes. Also, if the resistance values of resistors 8, 9, 13, and 15 are set so that R ₁ = R' ₁ and R ₂ = R' ₂ , equation (2) becomes 2R ₁ e ₀ = R It can be transformed as ₂ ei e ₀ /ei=R ₂ /2R ₁ ...(3). and signal output terminal 1
Since the voltage between 9a and 19b is 2e ₀ , the gain G _V
is G _V =2e ₀ /ei=R ₂ /R ₁ (4), and can be determined by the ratio of R ₁ and R ₂ .

Next, FIG. 3 shows a specific circuit of the portion consisting of the inverting amplifier 17 and the pulse amplifiers 5 and 6 in this embodiment.

In FIG. 3, the output signal e ₃ of the comparator 4 in FIG. 1 constitutes an inverted pulse amplifier 6.
MOS power type field effect transistor (hereinafter referred to as MOS
(abbreviated as power FET) 6a and 6b, and a non-inverting pulse amplifier 5.
The inverting amplifier 17 and the following
It is supplied to the input terminals of MOS FETs 5a and 5b. Both sources of MOS power FETs 5a and 6a,
A voltage 2E is supplied from a DC power supply 22 between the sources of the MOS power FETs 5b and 6b.
In this case, resistors 23a and 23b having the same resistance value (both values are r) are connected between the positive and negative power supply terminals of the DC power supply 22.
are successively connected in series, and these two resistors 2
The connection point between 3a and 23b is grounded via the voltage follower circuit 24, thereby applying voltage to both sources of the MOS power FETs 5a and 6a.
The voltages applied to both sources of the MOS power FETs 5b and 6b are maintained at voltages +E and -E, respectively. And MOS power FET5a, 5b
Both drains of are commonly connected, and the output signal _e4 is taken out from this connection point, and the MOS power FET6
The drains of a and 6b are commonly connected, and the output signal ₄ is taken out from this connection point.

As is clear from the above explanation, according to the pulse width modulation amplifier according to the present invention, the input signal
The integrated signal of the output signal of the second pulse amplifier in the BTL output stage is added and supplied to the non-inverting input terminal of the amplifier, while the output signal of the first pulse amplifier in the BTL output stage is added to the inverting input terminal of the amplifier. Then, the output of this amplifier is compared with the carrier signal, and the first and second pulse amplifiers are driven by this comparison output, so when the output stage pulse amplifier is configured as BTL. , it is possible to stably provide negative feedback to the output signal in the form of a pulse signal with an extremely simple circuit configuration without using active elements, thereby realizing a low-cost, low-distortion pulse width modulation amplifier. can do.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing the configuration of an embodiment of a pulse width modulation amplifier according to the present invention, Fig. 2 is a time chart for explaining the operation of the embodiment, and Fig. 3 is an output stage pulse in the embodiment. FIG. 2 is a circuit diagram showing a specific circuit of an amplifier. 2... Amplifier (operational amplifier), 3... Second capacitive element (capacitor), 4... Comparator, 5... First pulse amplifier, 6... Second pulse amplifier,
7... Load, 8... Third impedance element (resistance), 9... Fourth impedance element (resistance), 10... Signal input terminal, 13... First impedance element (resistance), 14... ...First capacitive element (capacitor), 15... Second impedance element (resistance), 16... Carrier signal source, 2
1... Filter circuit.

Claims (1)

[Claims] 1. A non-inverting input terminal is grounded via a first capacitive element and connected to a signal input terminal via a first impedance element, and a non-inverting input terminal is connected between the inverting input terminal and the output terminal. a comparator that compares the output of the amplifier with a carrier signal; and a comparator that compares the output of the amplifier with a carrier signal; first and second pulse amplifiers, which are driven by the filter circuit and drive both ends of the load with signals having opposite phases to each other through a filter circuit; and a feedback circuit that provides negative feedback to the inverting input terminal of the amplifier and also provides negative feedback of the output of the second pulse amplifier to the non-inverting input terminal of the amplifier via a fourth impedance element. Characteristic pulse width modulation amplifier.