JPH0353634A - Integrated circuit for communication - Google Patents

Abstract

PURPOSE:To eliminate the need for the provision of an exclusive reset terminal by setting a level different from an intermediate level used normally at communication to at least one of 1st and 2nd terminals connected to a 2-wire communication bus and initializing an internal circuit. CONSTITUTION:When the potential of an least either of a BUS +terminal 13 and a BUS -terminal 14, e.g., the potential of the BUS +terminal 13 is forcibly dropped to 0 level externally, an N-channel MOS transistor(TR) 19 is turned off and the output of an inverter 20 goes to a low level, then a reset signal is inputted to a signal processing section 11, which is initialized. Since it is detected and a reset signal is outputted when the level of at least 1st and 2nd terminals connected to a 2-wire communication bus reaches a level different from an intermediate potential used normally at communication, no exclusive reset terminal is required and the wiring for the purpose is not required and then the wiring is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a communication integrated circuit having a two-wire communication function, and more particularly to a communication integrated circuit whose internal circuit is reset by a reset signal.

[Prior Art] Conventionally, two-wire bit-synchronized communication bus systems have been used as a means of transmitting and receiving information between devices operating asynchronously in audio system sets and in-vehicle systems. It is used. In this bus system, in order to synchronize communication between the sending side and the receiving side, the sending side must
By transmitting 0.1 data at a timing determined by the bus system, the transmitter and receiver are synchronized bit by bit.

FIG. 5 is a timing chart of the bit synchronization described above. Before T1, the sending side outputs 1, but
, the transmitting side outputs O, and after a certain period of time has elapsed since outputting 0, that is, from T2 to T3, it transmits O or 1 data. The receiving side can synchronize with the transmitting side by detecting the timing of T.

The 6th communication integrated circuit used in this bus system
As shown in the figure.

Based on the O,1 data output from the SO terminal of the signal processing section 61, the driver 62 drives a two-wire external bus via the BUS+ terminal 63 and the BUS-terminal 64. On the other hand, the data received via the BUS 10 terminal 63 and the BUS 1 terminal 64 are output by the comparator 65 to 0.
1 and is input to the SI terminal of the signal processing section 61.

Furthermore, when a reset signal is input through the reset terminal 66, for example when the power is turned on, the signal processing section 61 inputs this signal through the inverters 67 and 88, and initializes the inside thereof.

[Problems to be Solved by the Invention] However, in the conventional communication integrated circuit described above, a dedicated reset terminal is required to initialize the internal circuit, and for this reason, a large number of integrated circuits are required in the same system. In a system in which circuits are connected via a common bus, the reset signal line must also be shared, resulting in an increase in the number of lines.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a communication integrated circuit that enables resetting of an internal circuit without providing a dedicated reset terminal, thereby simplifying wiring.

[Means for Solving the Problems] A communication integrated circuit according to the present invention has first and second terminals connected to a two-wire communication bus, and the first and second terminals during communication. a communication drive circuit that provides an intermediate potential between a first power supply potential and a second power supply potential; and at least one of the first and second terminals having a potential different from the intermediate potential. It is characterized by having a detection circuit that performs detection and a reset circuit that initializes an internal circuit using the output of this detection circuit.

[Function] According to the present invention, at least one of the first and second terminals connected to the two-wire communication bus is at a voltage level normally used during communication (the voltage level of the first and second power supply potentials). When the potential becomes different from the intermediate potential between them, this is detected and a reset signal is output. Therefore, in the present invention, there is no need for a dedicated glue set terminal, and no wiring for that purpose is required, and the wiring can be simplified.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram of a communication integrated circuit according to a first embodiment of the present invention.

In FIG. 1, the signal processing unit 11 is initialized by a reset signal input to the RESET terminal, and during communication, outputs transmission data from the SO terminal and inputs reception data to the SI terminal.

Data output from the SO terminal of the signal processing section 11 is given to the driver 12.

The driver 12 drives a two-wire bus connected to the outside via a BUS terminal 13 and a BUS terminal 14 based on data output from the SO terminal.

On the other hand, data received via the BUS 10 terminal 13 and the BUS 1 terminal 14 is input to the comparator 15. This comparator 15 compares the potentials of both terminals 13 and 14, determines the received data, and outputs the determination result to the SI terminal of the signal processing section 11.

Additionally, a resistor 18 is connected between the power supply terminal 16 and the ground terminal 17.
and an N-channel MOS transistor 17 whose gate is connected to the BUS+ terminal 13 are connected in series to form a detection circuit. The output of this detection circuit is supplied to a reset terminal of the signal processing section 11 via an inverter 20 serving as a reset circuit.

Now, assuming that the power supply VDD is 5V and the GND is O■, the driver 12 is configured such that the data output from the SO terminal is "
1″, BUS 10 terminal 13 and BUS 1 terminal 14
is set to 2.5■ through a high resistance, and when the data output from the SO terminal is "O'", the BUS terminal 13
is driven at a constant current of -5 mA, and the BUS terminal 14 is driven at a constant current of +5 mA.

Such a driver 12 can be configured by a circuit as shown in FIG. 2, for example.

That is, resistors 21, 22, 23, and 24 are connected in series between the electric K+ terminal 16 and the ground terminal 17. The resistance values of these resistors are 230KΩ, 20KΩ, 20KΩ, respectively.
It is 230KΩ. Since the potential of the power supply VDD is 5V, the connection point A. of these resistors 21 to 24 is connected. B. C(
7) The potential is 2.7V. 2.5V. Biased to 2.3V. These points A, B, and C are connected to operational amplifiers 25 and 25, respectively.
It is input to the inverting input terminal of the operational amplifier 26 and the normal input terminal of the operational amplifier 26 and 27.

On the other hand, the data output from the SO terminal of the signal processing section 11 is transmitted through the inverters 28 and 29 to the P
channel MOS} transistor 30 and N channel MOS
}A P-channel MOS transistor 32 and an N-channel MOS are input to the commonly connected gates of the transistor 31 and are connected in a complementary pair via the inverter 28.
} is input to the commonly connected gates of the transistors 33. The common connected drains of the transistors 30.31 are connected to the non-inverting input terminal of the operational amplifier 25, and the common connected drains of the transistors 32.33 are connected to the normal input terminal of the operational amplifier 25.
It is connected to the inverting input terminal of operational amplifier 27.

Furthermore, between the power supply terminal 16 and the ground terminal 17, there is a
Ω resistor 34, N channel MOS} transistor 35, t
A resistor 38, 37 of ooKΩ, an N-channel MOS transistor 38, and a resistor 39 of 500Ω are connected in series. The connection point between the transistor 35 and the resistor 36 is connected to the BUS+ terminal 13, and the connection point between the resistor 37 and the transistor 38 is connected to the BUS-terminal 14.

Here, the connection point between the resistor 34 and the transistor 35 is set to D1.
The connection point between resistor 36 and resistor 37 is E1 } transistor 38
Assuming that the connection point between the resistor 39 and the resistor 39 is F, the sources of the transistors 30 and 31 described above are connected to the D point and the ground point, respectively, and the outputs of the operational amplifiers 25, 26, and 27 are connected to the gate of the transistor 35, the E point, and the ground point, respectively. It is connected to the gate of transistor 38, and the sources of transistors 32 and 33 are connected to power supply terminal 16 and point F, respectively.

Next, the operation of the circuit according to this embodiment configured as described above will be explained.

When the digital data output from the SO terminal of the signal processing section 11 is "1", the N-channel MOS transistor 31 is turned on, the P-channel MOS transistor 30 is turned off, and the non-inverting input terminal of the operational amplifier 25 is at the ground level. Therefore, the output of the operational amplifier 25 becomes low level. Therefore, the N-channel MOS transistor 35 is turned off.

Also, at this time, the P channel MOS} transistor 32
is on, N-channel MOS} transistor 33 is off,
Since the VDD level is input to the inverting input terminal of the operational amplifier 27, the output of the operational amplifier 27 becomes low level. Therefore, N-channel MOS transistor 39 is also turned off. On the other hand, since the operational amplifier 26 is a voltage follower, its output point, E point, has the potential of B point,
That is, 2.5V is output. Therefore, BUS terminal 13
2.5V is also applied to the BUS terminal 14 through resistors 36 and 37, respectively.

Next, when the digital data output from the SO terminal of the signal processing unit 11 becomes "O", the N-channel MOS transistor 31 turns off, and the P-channel MOS transistor 30 turns off.
is turned on, and the same potential as point D is input to the normal input terminal of the operational amplifier 25.

As a result, the output potential of the operational amplifier 25 is
OS} The current flowing through the transistor 35 is increased or decreased, but it is balanced when the potentials at point A and point D become equal. Further, at this time, the P-channel MOS transistor 32 is turned off, the N-channel MOS transistor 33 is turned on, and the same potential as the point F is input to the inverting input terminal of the operational amplifier 27. As a result, the output potential of the operational amplifier 27 increases or decreases the current flowing through the N-channel MOS transistor 38.
Balance is complete when point C and point F become equal. Accordingly, 2. “2.3V is output to the t.rsBUS-terminal l4.

1, the potential of the BUS terminal 13 is set at a constant voltage, for example, 10
If it is higher than 0mV, “O II”, if it is lower than “
1". The signal processing unit 11 outputs data to be transmitted to the driver 12 based on a certain timing,
The input data from the comparator 15 is processed based on fixed timing. Under normal communication conditions, BU
The S+ terminal 13 and the BUS-terminal 14 are connected to each other externally through a resistor of a certain size (for example, 100Ω).

Therefore, if the BUS terminal 13 becomes 2.5V or less,
The BUS terminal 14 is never set to 2.5V or higher, and both terminals are always kept at an intermediate potential. Therefore,
The N-channel MOS transistor 19 is always on, and if the resistance value of the resistor 18 is sufficiently larger than the on-resistance value of the N-channel MOS transistor 19, the output of the inverter 20 becomes a noise level.

On the other hand, the potential of BUS terminal 13 is forced to OV from the outside.
When the voltage is lowered to the potential, N-channel MOS transistor 19 is turned off, and the output of inverter 20 becomes a halo level. As a result, a reset signal is input to the signal processing section 11, and the signal processing section 11 is initialized.

FIG. 3 shows this situation. The thick line in the figure is BU
The potential of the S terminal 13 and the dotted line are the potential of the BUS terminal 14. During the period from t to t2, the BUS terminal 13 is forcibly lowered to OV from the outside, indicating that initialization is being performed from the outside via the bus line.

The bus is “1” from t2 to t3 and from t4 to t5.
communication status. Furthermore, during the period from t3 to t4, the bus is in the communication state of "0", and the BUS terminal 13 and the BU
External resistance (100Ω) connected between S-terminal 14
A constant current (5mA) is flowing through.

FIG. 4 is a circuit diagram of a communication integrated circuit according to a second embodiment of the present invention.

In the embodiment shown in FIG. 1, the reset is applied when the BUS terminal 13 is pulled down to OV, but in this embodiment, when the BUS terminal 14 is forcibly pulled up to the VDn potential. It looks like it will take a reset.

That is, a P-channel MOS transistor 4 is connected between the power supply terminal 16 and the ground terminal 17 as a reset detection circuit.
1 and an N-channel MOS} transistor 42 are connected in series. The gate of the P-channel MOS transistor 41 is connected to the BUS terminal 14, and the gate of the P-channel MOS transistor 41 is
}The gate of a transistor is connected to its drain. The connection ends of both transistors 41 and 42 are connected to the inverter 43.
, 44 to the reset terminal of the signal processing section 11.

In this circuit as well, in a normal communication state, the BUS-terminal 14 is only 2.5V or less, so the P-channel MOS transistor 41 is always on. On the other hand, N
Since the resistance value of the channel MOS transistor 42 is very high, the potential of its drain becomes high level, and the output of the inverter 44 also becomes high level. Therefore,
Initialization of the signal processing section 11 is not performed.

On the other hand, BUS-terminal 14 is at V. When the voltage is raised to the D level, the P channel MOS} transistor 41 is turned off.
The input level of inverter 43 becomes low level, and the output of inverter 44 also becomes low level. As a result, the signal processing section 11 is initialized.

[Effects of the Invention] As explained above, according to the present invention, at least one of the first and second terminals to which a two-wire communication bus is connected is connected to the intermediate level normally used during communication. Since the internal circuit can be initialized by setting different levels, there is no need to provide a dedicated reset terminal. Therefore, even when a large number of communication integrated circuits are used in the same system, there is no need to provide wiring for sharing the reset signal, and the number of wiring can be significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a communication integrated circuit according to a first embodiment of the present invention, FIG. 2 is a detailed circuit diagram of a driver in the same circuit, and FIG. 3 is a timing diagram showing a communication operation by the same integrated circuit. FIG. 4 is a circuit diagram of a communication integrated circuit according to the second embodiment of the present invention, FIG. 5 is a timing diagram showing communication operation using a two-wire communication bus, and FIG. 6 is a conventional communication integrated circuit. It is a circuit diagram of a circuit. 11, 61; Signal processing section, 12, 82; Driver, 13
．． 63rBUS+ terminal, 14, 64; BUS-terminal, 1
5.65; Funnel array, 16: Power supply terminal, 17; Ground terminal, 25 to 27; Operational amplifier, 66: Reset terminal

Claims (1)

[Claims] (1) First and second terminals connected to a two-wire communication bus, and a first terminal connected to the first and second terminals during communication.
a communication drive circuit that provides an intermediate potential between a power supply potential and a second power supply potential; and a detection circuit that detects that at least one of the first and second terminals has a potential different from the intermediate potential. 1. A communication integrated circuit comprising: a circuit; and a reset circuit that initializes an internal circuit using the output of the detection circuit.