JPH0352251B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a frequency synthesizer receiver having a storage means for storing a plurality of reception frequencies.

(Prior Art) A conventional frequency synthesizer receiver of this type has a switch indicating the channel for each preset channel number, and by turning on each switch, the contents of the storage device can be recalled. Furthermore, by turning on another "key switch that enables storage" and then turning on a switch indicating a channel, the contents of the preset channel can be stored in the storage device. was.

As another example, in addition to having the function of sequentially recalling multiple preset channels with one switch, there is also a separate "key switch that enables memory", and the channel to be written can be recalled with a sequential switch. Thereafter, the storage device is set to a writable state, and when the forward switch is turned on once in this state, writing to the storage device is performed.

(Problems to be Solved by the Invention) In the former case of the above-mentioned prior art, in addition to requiring a switch for each preset channel,
There were problems with the large number of switches, such as the need for a "key switch that enables memorization." This problem becomes especially serious when the number of preset channels is large.

In addition, when using the latter technique of the prior art, two switches are required, which reduces the number of switches compared to the above case, but the channel to be stored must be selected before the storage device can be written to. However, there was a problem that the operation was cumbersome.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and provide a frequency synthesizer receiver that can read and write multiple contents of a storage device with a single switch.

(Means for Solving the Problems) In order to solve the above problems, the present invention is constructed as shown in FIG. 1.

In a frequency synthesizer receiver that is capable of receiving broadcasts at a reception frequency set by a reception frequency setting means 2, a switch means 1, a storage means 3 for storing a plurality of actual reception frequencies, and an on/off switch of the switch means 1 are provided. a timer means 5 for counting a set period from the state; a control means 6 for setting the write permission state when it is determined that the on state period of the switch means 1 has continued for a set time or more; a first determining means 7 for determining whether the on-state period of the switch means 1 has continued for a set period or more; and a second determining means 8 for determining that the on-state period of the switch means 1 is shorter than the set period in the write permission state. A third device for determining that the on-state period of the switch means 1 is less than a set period when the switch means 1 is not in the write permission state.
a discriminating means 9; an instruction address changing stage 10 for sequentially changing the memory address each time the output of the second discriminating means 8 is generated; The device is equipped with a call control means 4 for setting the receiver to the reception frequency, and writes the actual reception frequency being received into the memory address designated at the time of generation of the output of the first determination means.

(Function) Therefore, when the switch means 1 is turned on, the timer means 5 starts counting time, and when the on-state period of the switch means 1 is longer than the set time of the timer means 5, the control means 6 enters the write permission state. be made into Switch means 1 in write permission state
is turned on for less than a set time, this is determined by the second determining means 8, and each time the second determining means 8 generates an output, the designated memory address is changed to the designated address changing means 10 without changing the stored content. Changed by When the designated storage address becomes the desired storage address due to this change and the switch means 1 is turned on for a period longer than the set period, this fact is determined by the first determination means 7, and the actual reception received at this time is The frequency is written into the desired storage address of the storage means 3.

Further, if the switch means 1 is turned on for a period less than the set period in a state where the write permission state is not enabled, the third determination means 9 determines this fact, and the data is stored from the storage means 3 each time the switch means 1 is turned on. The receiving frequencies are sequentially read out by the call control means 4, and broadcasts on those frequencies are received.

Therefore, writing the actual receiving frequency into the storage means 3, reading the actual receiving frequency from the storing means 3, and instructing reception at the receiving frequency can be performed by one switch means 1.

(Example) The present invention will be explained below with reference to Examples.

FIG. 2 is a block diagram showing the configuration of one embodiment of the present invention.

The output from the antenna 11 is sent to the high frequency amplifier circuit 12.
The output of the high frequency amplifier 12 is mixed with the output frequency from the frequency synthesizer 14 in a mixing circuit 13 and converted into an intermediate frequency. The output from the mixing circuit 13 is amplified in an intermediate frequency amplification stage 15 and then demodulated in a demodulation circuit 16. The demodulated output from the demodulation circuit 16 is supplied to a low frequency amplifier circuit 17 for amplification, and then applied to a speaker 18 to be reproduced as audio.

As is well known, the frequency synthesizer 14 includes, for example, a reference frequency oscillator 14 ₁ , a phase comparator 14 ₂ , a low-pass filter 14 ₃ , a voltage controlled oscillator 14 ₄ , and a programmable divider 14 ₅ . Furthermore, it is provided with a microcomputer 14 ₆ that provides a frequency division ratio to the programmable dibiter 14 ₅ and generates a receiving frequency instruction output.

Microcomputer 14 ₆ is a CPU, ROM that stores programs, and RAM that stores data.
26, a timer, and an input/output device, as well as an up instruction switch 2 as in the conventional case.
2. By turning on the down instruction switch 23, the frequency division ratio of the programmable counter ₁₄₅ is changed, and in accordance with this change, the frequency division ratio of the voltage controlled oscillator 1 is changed.
By changing the ₄₄ oscillation frequency, it is possible to receive broadcasts at the desired frequency. Furthermore, the reception frequency is displayed on the display 24.

In one embodiment of the present invention, in addition to the above,
The output of the switch 21 is transferred to the microcomputer 14.
₆ , and a display signal indicating the channel number and memory enable (ME) is output from the microcomputer ₁₄₆ to the display 24. Here, the channel number does not necessarily match the preset channel number because only the channel number can be changed as described later, and after the division ratio corresponding to the current receiving frequency is written in the RAM 26, The next time the same channel number is specified, that channel number becomes the preset number.

Hereinafter, the operation of one embodiment of the present invention will be explained with reference to FIG. 3 along with a program stored in the ROM.

The A flag, which will be described later, is a flag for checking whether writing to the RAM 26 is permitted, and the B flag is a flag for checking whether the ON period of the switch 21 is a continuous ON valid period.

When switch 21 is turned on, switch 2
A continuous on valid period of 1 is set in the timer, and the timer starts counting (step a). When the switch 21 is continuously turned on for the continuous ON effective time, it is checked whether writing to the RAM 26 is permitted (step b). This check is determined by whether the A flag is set or reset. The A flag is initially reset in an initial setting step (not shown), and in this state it is not writeable. Therefore, initially following step b, the RAM 26 is enabled for writing, and the A flag is set (step d). In this state, the switch 21 is maintained in the on state, and the routine is entered again through the main routine. In this state, writing to the RAM 26 is enabled, and the frequency currently being received is displayed on the display 24.
Corresponds to the channel number displayed in
It is written to the storage area of RAM26, and then
The write permission state to RAM26 is canceled and A
The flag is reset (step c). In addition,
When writing to the RAM 26 is enabled in steps b and d (also in step f, which will be described later), that is, when the A flag is set, a display signal indicating "ME" is output to the display 24. “ME” is displayed on the display 24.

Further, when the switch 21 is once turned on for a period exceeding the timer setting period (step d), the switch 21 is turned off, and the switch 21 is turned on again for a period shorter than the timer setting period, Since the A flag has already been set as described above, writing to the RAM 26 is permitted (step e), and following step e, there is no change in the division ratio data for the current reception frequency, and only the channel number is updated. (Step f).
That is, after enabling writing to the RAM 26, the switch 21 is turned on for a short period of time, so that the channel number is incremented each time the switch 21 is turned on.

Furthermore, when the switch 21 is turned on for a period shorter than the timer setting period, it is determined that writing to the RAM 26 is disabled (step e).
Every time the switch 21 is turned on, the frequency division ratio data for the next channel number is read from the RAM 26, and the frequency division ratio data is set in the programmable divider ₁₄₅ (step g). . The state of step g corresponds to channel calling.

The operation of the receiver in one embodiment of the present invention will now be described.

(i) The desired frequency for reception can be set using the up instruction switch 22 and the down instruction switch 23.

Further, when storing a desired frequency for reception with respect to a channel number, the following operation is performed.

(ii) By turning on the switch 21 for a period exceeding the period set by the timer in (step a), writing to the RAM 26 is enabled (step d). In this state, "ME" is displayed on the display 24. Once the switch 21 is set to the write-enabled state as described above (step d), by turning on the switch 21 for a short period of time less than the set period of the timer, only the channel number is incremented by "+1" each time the switch is turned on. The number is shown on the display 24 following "CH". When the channel number reaches the desired number, the switch 21 is turned on again for a period exceeding the timer setting period.
The frequency division ratio corresponding to the reception frequency set in (i) is written in the position of the desired channel number.

(iii) When the switch 21 is not kept on for a period exceeding the timer setting period in step a, that is, when writing to the RAM 26 is disabled, by turning the switch 21 on for a period less than the timer setting period, the display is displayed. 14
You can receive the reception frequency for the channel next to the channel displayed in .

(Effects of the Invention) As explained above, it is determined whether the period in which the switch means is in the on state is longer or shorter than the timer setting period, and based on the result of this determination, writing to the storage means is enabled, and the writing is enabled. When determining the long-term ON state of the switch means, the receiving frequency is stored in a storage area corresponding to the designated channel, and the channel number is made to correspond to the storage area for each short-term ON state of the switch means during the write permission state. Since the reception frequency can be changed in accordance with the desired channel number using only the switch means, no other switch means is required. Further, by turning on the switch means for a short period of time when the writing is not permitted, the channel number and the receiving frequency corresponding to the channel number can be called up. This call can also be made using only the switch means and does not require any other switch means.

[Brief explanation of drawings]

FIG. 1 is a functional configuration diagram of the present invention. FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 3 is a flow chart for explaining the operation of one embodiment of the present invention. 1... Switch means, 2... Reception frequency setting means,
3...Storage means, 4...Reading control means, 5...Timer means, 6...Control means, 7...First discrimination means, 8...
Second determining means, 9... Third determining means, 10... Indicated address changing means.

Claims (1)

[Claims] 1. In a frequency synthesizer receiver that is capable of receiving broadcasts at a reception frequency set by a reception frequency setting means, a switch means, a storage means for storing a plurality of actual reception frequencies, and a timer means for timing a set period; a control means for setting the write permission state when it is determined that the on state period of the switch means has continued for the set period or more; a first determining means for determining whether the on-state period of the switch means is shorter than a set period while in the write permission state; a third determining means for determining whether the on-state period is less than a set period; an instruction address changing means for sequentially changing a storage address each time an output of the second determining means is generated; call control means for sequentially reading the actual receiving frequency from the means and setting the receiver to the received frequency; A frequency synthesizer receiver characterized in that a frequency can be written.