JPH0352020Y2 - - Google Patents

Description

[Detailed description of the invention] [Field of industrial application] The present invention relates to a frequency multiplication circuit, and is designed to obtain a good multiplied output especially when the input frequency to be multiplied is variable over a wide band, for example, 500 MHz. Regarding the multiplier circuit.

[Summary of the idea]

When the frequency to be multiplied is variable within a predetermined range, a series circuit consisting of a resistor R, a coil L, and a capacitor C is provided in front of the multiplier using a nonlinear element, and the series resonance of the LC is damped by R. In addition, a capacitor is connected in parallel to the above resistor to provide a bandpass characteristic that passes the above specified frequency range, and peaking is applied to the high range of the bandpass characteristic. Stable and highly efficient frequency multiplication becomes possible.

[Conventional technology]

Conventional frequency multiplier circuits include those that utilize non-linear resistance due to diode characteristics between the base and emitter of a transistor;
There are known types that utilize non-linear capacitance due to varactor action between collectors, those that utilize the parametric effect of transistors, and those that use varactors. Also known is a multiplier circuit that selectively amplifies the n-th harmonic of the oscillator output to obtain an n-multiplied output.

FIG. 7 shows an example of a conventional multiplier circuit that utilizes the nonlinearity of transistors (varactor action between collector and base). The input frequency ₀ signal is multiplied to n ₀ by the nonlinear amplification of the transistor 3. Matching circuit 1 on the input side is matched to the fundamental wave ₀ ,
The matching circuit 5 on the output side matches the multiplied frequency n ₀ . At this time, a trap circuit 2 of n ₀ is connected to the input side,
A _zero trap circuit 4 is provided on the output side, and each is adjusted so that the multiplied output is maximized.

[Problems to be solved by the invention] The multiplier circuit using non-linear elements, an example of which is shown in Fig. 7, assumes that the input frequency is fixed at ₀ , so the input frequency is If it is variable, it is difficult to operate in accordance with it.

In the method of selectively amplifying the n-th harmonic of the oscillator output, the input frequency may be variable over a wide band. However, since the multiplied output level depends on the level of the n-th harmonic, it is necessary to obtain an oscillation output with a high harmonic level, which causes problems with the stability of the oscillator (drift, parasitic oscillation, etc.).

In view of the above-mentioned problems, the present invention aims to make it possible to stably extract a multiplied output that follows the input frequency even if the input frequency is variable over a wide band.

[Means for solving problems]

The present invention is a frequency multiplier circuit that multiplies the oscillation output of an oscillator whose oscillation frequency is varied within a predetermined frequency range, and as shown in FIG. and a coupling portion 11a that couples the multiplier and the multiplier.

The coupling section 11a includes a series coupling circuit of a resistor R, a coil L1, and a capacitor C1, and has a bandpass characteristic that allows the oscillation output in the predetermined frequency range to pass through by damping the series resonance of the coil and capacitor with the resistor. is giving.

Furthermore, a capacitor C2 connected in parallel with the resistor R
The frequency characteristics are modified by applying peaking to the high range of the above bandpass characteristics.

[Effect]

The resistor is also used for impedance matching with the next stage multiplier, and the series capacitor is also used for coupling with the next stage. Due to the bandpass characteristic of the coupling section, only signals in the frequency range to be multiplied are sent to the multiplication section, and unnecessary bands are removed, thereby increasing multiplication efficiency. Furthermore, the frequency characteristics become flatter due to peaking, and a stable multiplied output level can be obtained even if the input varies over a wide band.

〔Example〕

FIG. 1 is a basic block diagram of the frequency multiplier circuit of the present invention, and FIG. 2 is a block diagram of the main parts of a satellite broadcasting receiver using this multiplier circuit. The frequency f ₀ of the oscillation output of the local oscillator 10, which is the signal source, varies from 675 to 675 depending on the tuning voltage from the tuning circuit.
Variable in the range of 925MHz. The multiplier circuit 11 is a well-known multiplier section 11 that utilizes transistor nonlinearity.
b, and obtains a multiplied output of twice the frequency _2f0 . A coupling section 11a is provided before the multiplier section 11b. This coupling section 11a has the following functions: firstly, the function of impedance matching between the output of the local oscillator 10 and the input of the multiplier section 11b; secondly, the function of a bandpass filter to limit unnecessary bands and increase multiplication efficiency;
It has a peaking function that corrects the frequency characteristics of the multiplied output.

The output of the multiplier circuit 11 is passed through a bandpass filter 12 that passes the band from 1350 to 1850MHz.
It is derived as a multiplied output (frequency 2 ₀ ).

In the satellite broadcasting receiver shown in Figure 2, first, the SHF of about 12GHz received by the parabolic receiving antenna.
The radio waves in the band are converted into UHF signals of about 1 GHz by an S-U converter in an outdoor unit (not shown), and then introduced into the outdoor unit as a first IF signal. The first IF signal is mixed with the second local oscillation signal by the mixer 13 in FIG. 2, and converted into the second IF signal of 400MHz. The second local oscillation signal is changed in a band of 1350 to 1850 MHz corresponding to the reception frequency.

The local oscillator 10 can be replaced with a lower frequency, lower cost
In order to control the PLL circuit, the output frequency of the local oscillator 10 is set to 1/2 of the second local oscillation frequency (675~
925MHz), and doubles it using the multiplier circuit 11. This makes it possible to use an inexpensive prescaler unit for TVs in the PLL circuit.

The frequency of the output of the local oscillator 10 is lowered by a prescaler 14, and then further divided by a programmable divider 15 to 1.5625 KHz according to data from a tuning controller. The phase comparison circuit 16 compares the phase of the frequency-divided output with a reference signal obtained by crystal oscillation, and uses the error output to control the oscillation frequency of the local oscillator 10.

FIG. 3 shows a concrete circuit corresponding to the blocks in FIG. 1. The local oscillator 10 is composed of a Colpitts circuit including a transistor Q1, and by applying a tuning voltage to a variable capacitance diode D,
The frequency is varied in the range of 675 to 925 MHz depending on the selected channel frequency.

A part of the oscillation output obtained from the emitter of the transistor Q1 is led out to a coupling section 11a including a resistor R, a coil L1, and a capacitor C1. The resistor R is about 47Ω and is inserted to match the input impedance of the next-stage multiplier 11b. Further, the resistance value is set to correspond to the oscillator 10 so as not to cause overload. Note that since the output is taken out from the emitter of the transistor Q1, the burden on the oscillator is small.

A series resonant circuit of a coil L1 and a capacitor C1 coupled to the tip of the resistor R constitutes a high Q narrow band bandpass filter as shown by the dotted line in FIG. The aforementioned resistor R inserted in series with this series resonant circuit acts as a damper for the resonant circuit, thereby creating a wide band that attenuates frequencies other than the band 675 to 925 MHz where the bandpass characteristic is _0, as shown by the solid line in Figure 4. It becomes a bandpass filter. Note that the capacitor C1 also serves as a coupling capacitor with the next stage.

The capacitor C2 connected in parallel with the resistor R is for peaking, and as shown by the dashed-dotted arrow A in Fig. 4, the high-frequency shoulder of the bandpass characteristic is lifted.
The passband is made flatter and the frequency characteristics are modified. Furthermore, by applying peaking as indicated by arrow B, the tail characteristics become steeper, and the attenuation characteristics for unnecessary bands, especially the ₂₀ component, are strengthened.

The output of the coupling section 11a is supplied to a multiplier section 11b including a transistor Q2.
The fundamental wave is doubled by the varactor action between the two collector bases, and is amplified and extracted.

Coil L2 is connected to the collector of transistor Q2.
A power supply voltage is applied through the (patterned coil), from which a multiplied output is derived to the bandpass filter 20 through the capacitor C3. The bandpass filter 20 passes a frequency band of _1,350 to 1,850 MHz and cuts out the fundamental wave, particularly the fundamental wave ₀ . This bandpass filter 20 can be constructed from a well-known stripline as shown in FIG. A stripline 21 having a length of λ/ ₄ that resonates with such an interdigital filter 20 is provided.

The output of the bandpass filter 20 is mixed with the first IF signal in a mixer 13 equipped with a transformer T.
It passes through the low-pass filter 22 and is derived as a second IF signal.

FIG. 6 is an actual measurement graph of the frequency characteristics of the circuit shown in FIG. 3, and it can be seen from the graph that almost constant multiplied output can be obtained over a wide band of 1350 to 1850 MHz.

[Effect of idea]

In the present invention, as described above, since the coupling section is provided before the multiplication section, stable and highly efficient frequency multiplication operation can be obtained for a wide band input.

[Brief explanation of the drawing]

Fig. 1 is a basic block diagram of the frequency multiplier circuit of the present invention, Fig. 2 is a block diagram of an embodiment when used in a satellite broadcasting receiver, and Fig. 3 is a detailed circuit corresponding to the block in Fig. 1. 4 is a frequency characteristic diagram of the coupling circuit of FIG. 3, FIG. 5 is a line pattern diagram when the bandpass filter 20 of FIG. 3 is configured with strip lines, and FIG. FIG. 7 is a block diagram of a conventional multiplier circuit. In addition, in the symbols used in the drawings, 10...local oscillator, 11...multiplier circuit, 11a...multiplier section,
11b...a coupling portion, 12...a band pass filter.

Claims (1)

[Scope of Claim for Utility Model Registration] A frequency multiplier circuit for multiplying the oscillation output of an oscillator whose oscillation frequency is varied within a predetermined frequency range, comprising a multiplier section using a nonlinear element, and a combination of the oscillator and multiplier section. and a coupling section for coupling between the two, the coupling section includes a series coupling circuit of a resistor, a coil, and a capacitor, and the series resonance of the coil and the capacitor is damped by the resistor, thereby producing an oscillation output in the predetermined frequency range. In addition to providing a bandpass characteristic that allows the passage of
A frequency multiplier circuit characterized in that the frequency characteristics are modified by applying peaking to the high range of the above bandpass characteristics.