JPH0351026B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image processing device that binarizes an image signal obtained by horizontally and vertically scanning an imaging screen, converts it into pixels, and performs predetermined processing. The present invention relates to an image processing device having a function of removing isolated pixels (also referred to as isolated points) such as.

[Conventional technology]

Conventionally, as a method for removing isolated points such as noise in such devices, an image observation area of, for example, 3 x 3 pixels, or a window, is set for the captured image, and surrounding pixels are white (for example, logic "0"). ) or black (for example, logic "1"), one pixel in the middle (the pixel of interest) is made to match the surrounding pixels depending on whether the pixel is black (for example, logic "1"). However, with this method, only one pixel can be removed in one screen scan. This is because, in principle, the states of surrounding pixels match one pixel of interest only once, and if the pixel of interest changes, the states of the surrounding pixels usually change as well. For example, when considering a window W1 on the image capture screen A as shown in FIG. 3, and setting the pixel of interest in this window W1 to _P22 ,
Even if the surrounding pixels P ₁₁ to _{P 13} , P ₂₁ , P ₂₃ , P ₃₁ to P ₃₃ match “0” or “1”, the pixel of interest is changed from P ₂₂ to P ₁₂ , P ₂₁ , P ₂₃ or P ₃₂ , it is clear that there is no guarantee that all surrounding pixels will be "0" or "1". Therefore, when attempting to remove isolated points of two or more pixels, for example, one entire imaged screen is imported into a predetermined memory, and the isolated points are removed through software processing by a processing device such as a microcomputer. I try to do that.

[Problem to be solved by the invention]

The above-mentioned isolated point removal method relies on software processing, which takes time, and has the problem that high-speed image processing is not possible.

[Means and actions for solving problems]

This invention provides (m+
2) Set a window of ×(n+2) pixels, and when a condition matching signal is obtained that all surrounding pixels of this window are “1” or “0”, this matching signal is delayed and stored. In this way, at least one of the m×n pixels is made to match the state of a surrounding pixel, and isolated points of two or more pixels are removed in real time.

〔Example〕

Fig. 1 is a circuit diagram showing an embodiment of this invention, Fig. 2 is a circuit diagram showing an embodiment of the present invention;
The figure is a timing chart for explaining its operation. In Figure 1, 1 is a window, 2
is a NAND gate, 3 is a one-pixel width delay circuit, 4,
6 is an OR gate, 5 is a 1-line width delay circuit, 7
is an inverter gate, and 8 is an AND gate.

Now, consider the case where a maximum of 2×2 pixels are to be removed from window 1 of 4×4 pixels. NAND gate 2 contains each peripheral pixel P ₁₁ of window 1.
-P ₁₄ , P ₂₁ , P ₂₄ , P ₃₁ , P ₃₄ , P ₄₁ -P ₄₄ are input, and when all of them match, a condition matching signal S2 as shown in FIG. 2A is output. Note that here, surrounding pixels are considered to be logic "0". This condition match signal S2 is delayed by a time corresponding to one pixel in the delay circuit 3, and is led to the OR gate 4 together with the condition match signal S2. Therefore, orgate 4
From this, a signal S3 having a width of two pixels is obtained as shown in FIG. 2B. This signal S3 is the OR gate 6
It becomes one input of the 1-line delay circuit 5. Therefore, the one-line delay circuit 5 obtains a signal S4 as shown in FIG. As a result, a signal S5 as shown in FIG. 2D is obtained from the OR gate 6.
The signal S5 is inverted by the inverter gate 7, and the target pixel P ₂₂ , P ₂₃ , P ₃₂ , P ₃₃ is detected by the AND gate 8.
The logical product is taken.

Therefore, for example, as shown in FIG. 3, there is an isolated point N1 where three pixels are "1", unlike the "0" of the surrounding pixels.
In this case, since all the surrounding pixels are "0", the condition matching signal S2 is "1", the signal S3 delayed by one pixel, and the signal S4 delayed by one line from this signal S3 are "1". 1”, the output of inverter gate 7 becomes “0”,
As a result, the signal S6 derived from the four pixels of interest (P ₂₂ , P ₂₃ , P ₃₂ , P ₃₃ ) including the isolated point N1 is "1" or "0" by the AND gate 8. 0”. In other words, the condition matching signal S2
is obtained, and when the pixel of interest is different from the surrounding pixels, that pixel is made to match the same logic state as the surrounding pixels.

In addition, although the example in which a 4 x 4 pixel window is set and isolated points of maximum 2 x 2 pixels are removed is described above, this invention generally applies to (m+2)
m using a window consisting of ×(n+2) pixels
It is clear that this method can be applied to the case of removing an isolated point consisting of ×n pixels. In this case, it goes without saying that the number of pixels or lines to be delayed by the delay circuits 3 and 5 must be selected in accordance with the number.

〔Effect of the invention〕

According to this invention, the isolated signal,
In other words, by simply providing a means to delay and store (enlarge) the condition matching signal, it is possible to remove isolated points consisting of not only one pixel but multiple pixels online at high speed, and as a result, the image This provides the advantage of further improving the reliability of inspection, recognition, etc.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of this invention, Fig. 2 is a circuit diagram showing an embodiment of the present invention;
The figure is a timing waveform diagram for explaining the operation, and FIG. 3 is a reference diagram for explaining the isolated point removal method. Explanation of symbols: 1... window, 2... NAND gate, 3, 5... delay circuit, 4, 6... OR gate, 7... inverter gate, 8... AND gate.

Claims (1)

[Claims] 1 After binarizing and pixelizing the image signal obtained by scanning the image screen horizontally and vertically, (m+2)×(n+
2) An image processing device that sets an image observation area (window) of pixels and performs predetermined operations, and from which the binarization state of each surrounding pixel among (m+2)×(n+2) pixels is determined. a condition determining means for extracting and outputting a condition matching signal when all of them match; a horizontal enlarging means and a vertical enlarging means for delaying and enlarging the condition matching signal in the horizontal and vertical directions; and the horizontal enlarging means. When a condition matching signal is outputted through the means or vertical enlarging means, at least one of the m×n pixels is expanded by two of the surrounding pixels.
An image processing device comprising an assimilation means for matching a value state.