JPH0350977A - Television signal processing unit - Google Patents

Abstract

PURPOSE:To receive a TV signal of MUSE and NTSC systems by providing a changeover circuit selecting and outputting an output signal of a MUSE signal processing circuit and an NTSC signal processing circuit. CONSTITUTION:A MUSE signal processing circuit 1 converts a TV signal fed to a MUSE signal input terminal 7 into R, G, B video signals. Moreover, an NTSC signal processing circuit 2 converts a TV signal of jump scanning NTSC fed to an NTSC signal input terminal 8 into R, G, B video signals of jump scanning. When a 1st changeover circuit 3 selects an output signal of the circuit 1 in the R, G, B signal processing circuits 4, 5, 6, time axis conversion processing is applied to the output signal of the circuit 3. On the other hand, when the circuit 3 selects the output signal of the circuit 2, the jump scanning NTSC video signal of the output signal of the circuit 3 is subjected to sequential scanning conversion and the result is outputted to R, G, B output terminals.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a television signal processing device capable of receiving at least MUSE type television signals and interlaced scanning type NTSC television signals.

Conventional technology The specifications of the conventional MUSE method are based on an aspect ratio of 5:3, and when attempting to transmit BTA standard S-001 studio standard video (aspect ratio 16:9) using the MUSE method without any loss. Time axis compression is required in advance.

Therefore, a method has been considered in which time axis compression is performed on the transmitting side and time axis expansion is performed on the receiving side.

As a MUSE type television signal processing apparatus having such a time axis conversion function, a television signal processing apparatus having a configuration as shown in FIG. 2 can be considered.

In the television signal processing device shown in FIG.
The USE signal processing circuit 1 converts the television signal arriving at the MUSE signal input terminal 7 into R and G signals.

The signal is converted into a B video signal and supplied via conductors 24, 25 and 26 to an R signal time axis expansion circuit 21, a G signal time axis expansion circuit 22, and a B signal time axis expansion circuit 23, respectively.

The R signal time axis expansion circuit 21 is the MUSE signal processing circuit 1
A time axis expansion process is performed on the R signal supplied from the terminal via the conductor 24, and the R signal is supplied to the R signal output terminal 9 via the conductor 27. Similarly, the G signal time axis expansion circuit 22 and the B signal time axis expansion circuit 23 are connected to the MUSE signal processing circuit 1, respectively.
Time axis expansion processing is performed on the G signal and B signal supplied via conductors 25 and 26 from the G signal output terminal 10 through conductors 28 and 29. The B signal is supplied to the B signal output terminal 11, respectively.

R signal time axis expansion circuit 21, G signal time axis expansion circuit 22
, the B signal time axis expansion circuit 23 has the same configuration and operation, so here the operation of the R signal time axis expansion circuit 21 will be explained using FIG. 3 for the case where 12/11 time axis expansion processing is performed. I will explain.

The signal supplied from the MUSE signal processing circuit 1 is approximately 48
(Mbl)s). When performing signal processing on such high bit rate signals,
N-phase parallel processing is generally performed in view of the operating speed of the element and the stability of processing. Here, a case will be described in which two-phase parallel processing is performed when N=2.

In FIG. 3, signals 24.212.213.218.
217.27 is the conductor 24.212.213 shown in Figure 2
．． 21θ, 217.27 signal is shown. Further, one square in FIG. 3 corresponds to one clock period of video processing data.

The signal 24 is an R signal with a hit rate of 48.8 (Mbl)s) supplied from the MUSE signal processing circuit 1;
A line is composed of 1440 pieces of video data.

That is, one horizontal period (corresponding to IH in FIG. 3) is approximately 29.8 (μS).

The serial-to-parallel conversion circuit 211 converts this 48.8 (MbpS)
The signals are converted into two-phase parallel signals of 48.8/2 (Mbps) and supplied to line memories 214 and 215 via conductors 212 and 213, respectively.

Therefore, as shown in FIG.
The video data string is the odd-numbered clock such as the first clock, third clock, . . . Φ, 1437th clock, 11439th clock of The video data string is an even-numbered clock such as the 1438th clock and the 1440th clock. At this time, the signal 212.21
The bit rate for all 3 is 48.8/2 (Mbps), 1
The number of line video data is 720.

In line memories 214 and 215, signals 212 and 213 supplied via conductors 212 and 213 are respectively 48.8/2 (
Write to memory with a clock of 44.55 Mbps)
/2 (Mbps) clock. Then, they are supplied to the SW 218 via conductive wires 21B and 217, respectively. Therefore, as shown in FIG.
7, the bit rate is 44.55/2 (Mbps)
Also, one horizontal period is approximately 29.6 (μS), so 1
The number of line video data is 860.

SW218 receives a signal 218.21 supplied from line memory 214.215 via conductor 216 and conductor 217.
7 is sequentially switched in clockwise increments as shown in the signal 27 shown in FIG.
(Mbps), 1 line of video data 1320 R
The signal is supplied to the R signal output terminal 9.

In this way, the R signal time axis expansion circuit 21
Bit rate supplied from E signal processing circuit 1: 48.8
(Mbps), 12/11 time axis expansion processing is applied to the R signal with 1440 pieces of video data per line, and the R signal has a bit rate of 44.55 (Mbps) and 1320 pieces of video data per line. The signal is supplied to the R signal output terminal 9 as a signal. The G signal time axis expansion circuit 22 and the B signal time axis expansion circuit 23 also receive the G signals supplied from the MUSE signal processing circuit 1.
Exactly the same processing is performed on the signal and B signal, and the number of video data per line is 1.
The 440 video signals are subjected to 12/11 time axis expansion processing, resulting in a video signal with a bit rate of 44°55 (Mbps) and 1 line of video data of 1320 pieces.

On the other hand, as a television signal processing apparatus capable of receiving an interlaced NTSC television signal, a television signal processing apparatus having a configuration as shown in FIG. 4 can be considered.

In the television signal processing device shown in FIG.
The TSC signal processing circuit 2 converts the interlaced NTSC television signal supplied to the NTSG signal input terminal 8 into RlG.
, B into interlaced scanning type NTSC video signals and supply them to an R signal scan conversion circuit 31, a G signal scan conversion circuit 32, and a B signal scan conversion circuit 33 via conductors 34, 35 and 36, respectively.

The R signal scan conversion circuit 31, the G signal scan conversion circuit 32, and the B signal scan conversion circuit 33 are the NTSC signal processing circuit 2.
R supplied via conductors 34, 35 and 36 from
The GlB interlaced scanning signals are sequentially scan-converted and output to an R signal output terminal 9, a G signal output terminal 10, respectively.
and is supplied to the B signal output terminal 11. Since the R signal scan conversion circuit 31, the G signal scan conversion circuit 32, and the B signal scan conversion circuit 33 have the same configuration and operation, the operation of the R signal scan conversion circuit 31 will be explained in the fifth section.
This will be explained using figures.

In FIG. 5, signals 34.312.313.316.
317.37 is the conductor 34.312.313 shown in Figure 4.
．． 316.317.37 signal is shown. Further, one square in FIG. 5 corresponds to one horizontal period (LH in FIG. 5).

The signal 34 is an R signal with a bit rate of 4fsc(bl)s) (fsc is the frequency of the color subcarrier) supplied from the NTSC signal processing circuit 2.

The SW311 is connected to the n-1st scanning line (n-I in FIG.
In H), the NTSC signal processing circuit 2 and the line memory 31
4 and supplies a signal 34 to a line memory 314 via a conductor 312. In the next n-th scanning line (nH in FIG. 5), the NTSC signal processing circuit 2 and the line memory 315 are coupled, and the signal 34 is supplied to the line memory 315 via the conducting wire 313. This operation is repeated sequentially for each scanning line. Therefore, signal 312 is equal to e of signal 34.
as, n-IH1n+IHs IS @ video data every other scanning line, signal 313 is signal 34 see,
This is video data of every other scanning line of n2H1nHs n+2H1·φ·.

The line memory 314 converts the signal 312 supplied via the conducting wire 312 to 4 fsc (b
ps), and in the next n-th scanning line, the video data written to the memory in the (n-1)th scanning line is read out with a clock of 8 fsc (bps). Then, SW
318. Therefore, in the signal 316, the video data of the n-1st scanning line is transmitted twice in the nth scanning line, and
In the (n+2)th scanning line, the video data of the (n+1)th scanning line is entered twice, so that the video data of the previous scanning line is entered twice every other scanning line.

The line memory 315 operates in exactly the same way as the line memory 314, and the video data of the n-2th scanning line is stored twice in the n-1st scanning line, and the video data of the nth scanning line is stored in the n+1th scanning line twice. 1 every other scan line, such as 2 times.
The signal 317 containing the video data before the scanning line twice is sent to SW3.
18.

The SW 318 switches the signals 316 and 317 supplied via the conducting wires 316 and 317 for each scanning line, and supplies the R signal output terminal 9 with a signal 37 containing the video data of the previous scanning line twice.

In this way, the R signal scan conversion circuit 31 converts the NTSC
The interlaced scanning R signal supplied from the signal processing circuit 2 is sequentially scan-converted. The G signal scanning conversion circuit 32 and the B signal scanning conversion circuit 33 also perform exactly the same processing on the interlaced scanning type G signal and B signal supplied from the NTSC signal processing circuit 2,
Converts an interlaced signal to progressive scan.

Problems to be Solved by the Invention However, with the above configuration, there is no mutual compatibility between a MUSE type television signal processing apparatus and a television signal processing apparatus capable of receiving an interlaced scanning type NTSC television signal. If broadcasting of MUSE television signals begins in the near future, a television signal processing device that can receive both types of television signals will be required. In such a television signal processing device, simply arranging the television signal processing device shown in FIG. 2 and the television signal processing device shown in FIG. 4 independently will increase the circuit scale and increase the cost. It also had the problem of becoming very high.

In view of the above, the present invention provides scanning replacement between a line memory used for time axis conversion processing in a television signal processing device capable of receiving MUSE television signals and a television signal processing device capable of receiving interlaced scanning NTSC television signals. The purpose of the present invention is to provide a television signal processing device capable of receiving MUSE television signals and interlaced scanning NTSC television signals on a smaller scale than conventional devices by sharing a line memory used for processing. shall be.

Means for Solving the Problems The present invention provides a MUSE signal processing means for decoding a MUSE type television signal arriving at a MUSE signal input terminal, and an interlaced scanning N type television signal arriving at an NTSC signal input terminal.
An NTSC signal processing means for decoding a TSC television signal, an output signal of the MUSE signal processing means, and an NTSC
The first switching means switches and outputs the output signal of the signal processing means, and the signal converting means is supplied with the output signal of the first switching means.

Effect of the Invention With the above-described configuration, the MUSE signal processing means converts the television signal supplied to the MUSE signal input terminal into R, G, and B video signals.

The NTSC signal processing means converts the interlaced scanning NTSC television signal supplied to the NTSC signal input terminal into RlG,
Converts to B interlaced scanning NTSC video signal.

The signal conversion means performs time axis conversion processing on the output signal of the first switching means when the first switching means selects the output signal of the MUSE signal processing means.

On the other hand, when the first switching means selects the output signal of the NTSC signal processing means, the interlaced scanning type NTSC video signal of the output signal of the first switching means is sequentially scan-converted.

Embodiments Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings. Components having the same purpose and operation as those in FIGS. Explanation will be omitted.

FIG. 1 shows a block diagram of a television signal processing apparatus in an embodiment of the present invention.

In FIG. 1, when receiving a MUSE system television signal, the first switching circuit 3 selects the RlG and B video signals of the MUSE signal processing circuit 1, and connects the conductor 12.1.
3. R signal conversion circuit 4, G signal conversion circuit 5 via 14
, B signal conversion circuit 6, respectively.

The R signal conversion circuit 4 includes a second switching circuit 401, a line memory 404, a line memory 405, and a third switching circuit 4.
08, and the first
The second switching circuit 401 performs time axis expansion processing on the R signal supplied from the switching circuit 3. The second switching circuit 401 processes the 48.8 (Mbps) R signal (third Video data similar to signal 24 shown in the figure) is 48.8/2
(Mbps) 2-phase parallel signal, conductor 402.4
03 to line memories 404 and 405, respectively. Therefore, signal 402 is equal to signal 21 shown in FIG.
The video data string is the same as 2, and the signal 403 is the same as the signal 213.
This is the same video data string as .

Line memories 404, 405 respectively receive signals 402, 403 supplied via conductors 402, 403, 48.
6/2 (Mbps) Write to memory with glue,
It operates to read with a clock of 44.55/2 (Mbis), and performs time axis expansion processing of 12/11. Therefore, signals 406.407 correspond to signals 218.407 in FIG.
This is the same video data string as 217. Then, they are supplied to a third switching circuit 408 via conductive wires 40El and 407, respectively.

The third switching circuit 408 receives a signal 40 supplied from the line memory 404, 405 via a conductor 406 and a conductor 407.
Similarly to the signal 27 shown in FIG.
supply to.

In this way, the R signal conversion circuit 4 performs the same time axis expansion process as the R signal time axis expansion circuit 21 through the first switching circuit 3.
This is applied to the R signal supplied from.

The configuration and operation of the G signal conversion circuit 5 and the B signal conversion circuit 6 are the same as those of the R signal conversion circuit 4, and the time axis expansion processing is similar to that of the G signal time axis expansion circuit 22 and the B signal time axis expansion circuit 23, respectively. is applied to the G signal and B signal supplied from the first switching circuit 1.

On the other hand, when receiving NTSC television signals,
The first switching circuit 3 selects the R, G1B interlaced scanning signal from the NTS, C signal processing circuit 2, and connects the conductor 12.13.
．． 14, the R signal conversion circuit 4, the G signal conversion circuit 5,
The signals are respectively supplied to the B signal conversion circuit 6.

In the R signal conversion circuit 4, the second switching circuit 401
- In the first scanning line, the first switching circuit 3 and the line memory 404 are coupled, and the R signal (video data similar to the signal 34 shown in FIG. 5) is sent to the line memory 404 via the conductor 402.
Supply on 04. In the next nth scan line, NTSC
The signal processing circuit 2 and the line memory 405 are coupled, and the R signal is supplied to the line memory 405 via the conductive wire 403.

This operation is repeated sequentially for each scanning line. Therefore, the signal 402 becomes video data for every other scanning line, similar to the signal 312, and the signal 403 becomes video data for every other scanning line, similar to the signal 313.

The line memory 404 converts the signal 402 supplied via the conducting wire 402 into 4 fsc (bp) in the n-1th scanning line.
s), and in the next nth scanning line, the video data written in the memory in the n-1st scanning line is read out with a clock of 8 fsc (bps). Then, it is supplied to a third switching circuit 408 via a conducting wire 406. Therefore, signal 406 is n
In the th scanning line, the video data of the n-1th scanning line is 2
In the (n+2)th scanning line, the video data of the (n+1)th scanning line is transmitted twice, and thus becomes a signal similar to the signal 318.

The line memory 405 operates in exactly the same way as the line memory 404, and the video data of the n-2 scan line is stored twice in the n-1 scan line, and the video data of the n scan line is stored in the n+1 scan line twice. The signal is similar to signal 317, such as twice.

A third switching circuit 408 switches signals 406 and 407 supplied via conductive wires 406 and 407 for each scanning line, and outputs an R signal similar to the signal 37 shown in FIG. 5 to an R signal output terminal via a conductive wire 15. Supply to 9.

In this way, the R signal conversion circuit 4 performs the same scan conversion process as the R signal scan conversion circuit 31 on the R signal supplied from the first switching circuit 3.

The configurations and operations of the G signal conversion circuit 5 and the B signal conversion circuit 6 are the same as those of the R signal conversion circuit 4, and in the same manner as described above, the G signal scan conversion circuit 32 and the B signal scan conversion circuit 33 are respectively configured. Similar scan conversion processing is applied to the G signal and B signal supplied from the first switching circuit 3, respectively.

As described above, according to this embodiment, the first switching circuit 3,
By providing the second switching circuit 401 and the third switching circuit 408, the line memory 404 and the line memory 405
can be used both when receiving MUSE television signals and interlaced scanning NTSC television signals, and with a smaller device size than before, it is possible to receive both MUSE television signals and interlaced scanning NTSC television signals. and can receive.

In addition, in the time axis conversion process, in this example, 12/1
Although the case of the time axis expansion processing in No. 1 has been described, it goes without saying that the configuration of this embodiment is valid as is for other conversion ratios, regardless of time axis expansion or time axis/compression.

Also, although not mentioned in the main text, the first switching circuit 3
, second switching circuit 401, line memory 404, 405,
It goes without saying that a control means is required to control the third switching circuit 408 and the like as described above.

As described in detail, according to the present invention, it is possible to configure a television signal processing device capable of receiving MUSE television signals and interlaced scanning NTSC television signals on a smaller scale than conventional devices. It can be done, and its practical effects are great.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a television signal processing device according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional MUSE type television signal processing device having a time axis expansion function, and FIG. R signal time axis expansion circuit 21 in Figure 2
4 is a block diagram of a television signal processing device capable of receiving an interlaced NTSC television signal, and FIG. 5 is a timing chart for explaining the operation of the R signal scan conversion circuit 31 in FIG. 4. It is a timing chart for explanation. DESCRIPTION OF SYMBOLS 1...MUSE signal processing circuit, 2...NTSC signal processing circuit, 3...1st switching circuit, 4...R signal conversion circuit, 5...G signal conversion circuit, 6...B Signal conversion circuit, 401... Second switching circuit, 404.405...
Line memo 1c 408...Third switching circuit.

Claims (2)

[Claims] (1) MUSE signal processing means for decoding the MUSE television signal arriving at the MUSE signal input terminal, and interlaced scanning NTS arriving at the NTSC signal input terminal.
NTSC signal processing means for decoding a C television signal; first switching means for switching and outputting an output signal of the MUSE signal processing means and an output signal of the NTSC signal processing means; and an output signal of the first switching means is supplied. and a signal converting means, when the first switching means selects the output signal of the MUSE signal processing means, the signal converting means:
Performing time axis conversion processing on the output signal of the first switching means,
When the first switching means selects the output signal of the NTSC signal processing means, the interlaced scanning NTSC video signal, which is the output signal of the first switching means, is subjected to scan conversion processing of sequentially scanning converting the video signal. television signal processing equipment. (2) The signal conversion means includes a second switching means for switching the output signal of the first switching means, a plurality of line memories for storing the output signals of the second switching means, and a second switching means for switching the output signals of the plurality of line memories. 3 switching means, the second
The switching means switches coupling between the first switching means and the plurality of line memories on a clock basis when the first switching means selects the output signal of the MUSE signal processing means;
2. The apparatus according to claim 1, wherein when the first switching means selects the output signal of the NTSC signal processing means, the connection between the first switching means and the plurality of line memories is sequentially switched on a scanning line basis. Television signal processing equipment.