JPH0350785A - Formation of pattern of hybrid integrated circuit device - Google Patents
Formation of pattern of hybrid integrated circuit deviceInfo
- Publication number
- JPH0350785A JPH0350785A JP18552689A JP18552689A JPH0350785A JP H0350785 A JPH0350785 A JP H0350785A JP 18552689 A JP18552689 A JP 18552689A JP 18552689 A JP18552689 A JP 18552689A JP H0350785 A JPH0350785 A JP H0350785A
- Authority
- JP
- Japan
- Prior art keywords
- thick
- film electrode
- insulating layer
- printing
- thick film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title 1
- 238000000034 method Methods 0.000 claims description 2
- 239000011521 glass Substances 0.000 abstract description 8
- 230000001681 protective effect Effects 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 7
- 229910000679 solder Inorganic materials 0.000 abstract description 7
- 238000005476 soldering Methods 0.000 abstract 1
- 238000010304 firing Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、混成集積回路装置のパターン形成方法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of patterning a hybrid integrated circuit device.
従来の技術
従来、混成集積回路装置は、第２図ａ、ｂに示す様な構
成であった。第２図ａ、ｂに於いて、１０はアルミナ基
板、１１は印刷焼成により形成した厚膜電極である。１
３は保護ガラスで、はんだ付は部分を除く厚膜電極１１
及び印刷抵抗体１２を覆っている。又、リード端子１５
及びチップ部品１４を付けるために、はんだ１６が用い
られている。2. Description of the Related Art Conventionally, hybrid integrated circuit devices have had configurations as shown in FIGS. 2a and 2b. In FIGS. 2a and 2b, 10 is an alumina substrate, and 11 is a thick film electrode formed by printing and baking. 1
3 is the protective glass, and the thick film electrode 11 except for the soldered part
and covers the printed resistor 12. Also, the lead terminal 15
and solder 16 is used to attach the chip components 14.
発明が解決しようとする課題
この様な従来の構造では、セラミック基板１０に所定の
パターンになるような厚膜電極１１と印刷抵抗体１２及
びチップ部品１４を実装する密度が低下し、厚膜電極本
数及び印刷抵抗体とチップ部品の形状により混成集積回
路装置の形状が決定され、しかも印刷抵抗体の抵抗値安
定化のために保護ガラスを必要としていた。本発明は、
この様な課題を解決することを目的とするものである。Problems to be Solved by the Invention In such a conventional structure, the density of mounting the thick film electrode 11, the printed resistor 12, and the chip component 14 in a predetermined pattern on the ceramic substrate 10 is reduced, and the thick film electrode The shape of the hybrid integrated circuit device is determined by the number of resistors and the shapes of the printed resistors and chip components, and a protective glass is required to stabilize the resistance value of the printed resistors. The present invention
The purpose of this project is to solve such problems.
課題を解決するための手段
この目的を達成するために本発明は、印刷抵抗体上に絶
縁層を印刷することにより、さらに厚膜電極を重ねて印
刷焼成するように形成したものである。Means for Solving the Problems In order to achieve this object, the present invention is formed by printing an insulating layer on a printed resistor, and then overlaying a thick film electrode and printing and firing the layer.
作用
この構成により、抵抗値の安定化ができ、しかも実装密
度を大幅に向上させることができる。Effect: With this configuration, the resistance value can be stabilized and the packaging density can be greatly improved.
実施例
第１図ａ、ｂは本発明の一実施例による混成集積回路装
置の要部を示す図で、図に於いて１はアルミナ基板、２
はこのアルミナ基板１の上に所定のパターンとなるよう
に印刷焼成で構成した厚膜電極である。３は両端部が厚
膜電極２と重なり合うように印刷焼成によりアルミナ基
板１上に形成した抵抗体である。４は絶縁層で、厚膜電
極２及び抵抗体３を覆うように形成されている。５は上
部厚膜電極であり、絶縁層４の端部にて厚膜電極２と重
なり接続されている。６は保護ガラスで、はんだ付は部
分を除いて厚膜電極２、絶縁層４及び上゛部厚膜電極５
を覆うようにされている。７は電極部を厚膜電極２には
んだ９により接続することにより実装したチップ部品、
８は外部へのリード引出し部としてのリード端子で所定
の厚膜電極２にはんだ９により接続されている。Embodiment FIGS. 1a and 1b are diagrams showing the main parts of a hybrid integrated circuit device according to an embodiment of the present invention, in which 1 is an alumina substrate, 2 is
is a thick film electrode formed by printing and firing on this alumina substrate 1 so as to form a predetermined pattern. 3 is a resistor formed on the alumina substrate 1 by printing and firing so that both ends overlap the thick film electrode 2. Reference numeral 4 denotes an insulating layer, which is formed to cover the thick film electrode 2 and the resistor 3. Reference numeral 5 denotes an upper thick film electrode, which overlaps and is connected to the thick film electrode 2 at the end of the insulating layer 4. 6 is a protective glass, except for the soldered parts, the thick film electrode 2, the insulating layer 4 and the upper thick film electrode 5.
It is designed to cover the 7 is a chip component mounted by connecting the electrode part to the thick film electrode 2 with solder 9;
A lead terminal 8 serves as a lead lead-out portion to the outside, and is connected to a predetermined thick film electrode 2 by solder 9.
このように本実施例に於いては抵抗体３上に絶縁層４を
重ねさらに５の上部厚膜電極印刷焼成の構造としたが、
厚膜電極２を覆うように、４の絶縁層を重ねてさらに５
の上部厚膜電極を印刷焼成し、上部厚膜電極５の上を所
定パターンの保護ガラス６で覆うことにより、上部厚膜
電極５にチップ部品７の電極部をはんだ９により接続、
実装できることは言うまでもない。In this example, the insulating layer 4 is layered on the resistor 3, and the upper thick film electrode 5 is printed and fired.
4 insulating layers are stacked to cover the thick film electrode 2, and then 5
By printing and firing the upper thick film electrode, and covering the upper thick film electrode 5 with a protective glass 6 of a predetermined pattern, the electrode part of the chip component 7 is connected to the upper thick film electrode 5 with solder 9,
Needless to say, it can be implemented.
発明の効果
以上のように本発明によれば、混成集積回路装置に於け
る厚膜電極及び抵抗体の上に絶縁層を設けることにより
さらに厚膜電極を重ねることができ実装密度が大幅に向
上され、又、抵抗体は絶縁層及び保護ガラスにより保護
されるため、抵抗値の安定性が確保できる。Effects of the Invention As described above, according to the present invention, by providing an insulating layer on the thick film electrode and resistor in a hybrid integrated circuit device, the thick film electrode can be further stacked, and the packaging density can be greatly improved. Furthermore, since the resistor is protected by an insulating layer and protective glass, stability of the resistance value can be ensured.
第１図ａは本発明の一実施例による混成集積回路装置の
要部を示す平面図、第１図すは第１図ａのＡ−Ａ’で切
断した断面図、第２図ａは従来の混成集積回路の要部を
示す平面図、第〉図すは第２図ａのＢ−Ｂ ’で切断し
た断面図である。
１・・・・・・アルミナ基板、２・・・・・・厚膜電極
、３・・・・・・抵抗体、４・・・・・・絶縁層、５・
・・・・・上部厚膜電極、６・・・・・・保護ガラス、
７・・・・・・チップ部品、８・・・・・・リード端子
、９・・・・・・はんだ。FIG. 1a is a plan view showing the main parts of a hybrid integrated circuit device according to an embodiment of the present invention, FIG. 1 is a sectional view taken along line A-A' in FIG. 1a, and FIG. FIG. 2 is a plan view showing a main part of the hybrid integrated circuit shown in FIG. DESCRIPTION OF SYMBOLS 1...Alumina substrate, 2...Thick film electrode, 3...Resistor, 4...Insulating layer, 5...
... Upper thick film electrode, 6 ... Protective glass,
7... Chip parts, 8... Lead terminals, 9... Solder.
Claims (1)
上に厚膜電極を形成した混成集積回路装置のパターン形
成方法。A pattern forming method for a hybrid integrated circuit device in which an insulating layer is printed and fired on a thick film printed resistor and a thick film electrode is formed on the insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18552689A JPH0350785A (en) | 1989-07-18 | 1989-07-18 | Formation of pattern of hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18552689A JPH0350785A (en) | 1989-07-18 | 1989-07-18 | Formation of pattern of hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0350785A true JPH0350785A (en) | 1991-03-05 |
Family
ID=16172343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18552689A Pending JPH0350785A (en) | 1989-07-18 | 1989-07-18 | Formation of pattern of hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0350785A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5499863A (en) * | 1993-05-17 | 1996-03-19 | Toyota Shatai Kabushiki Kaisha | Seat back frame |
| CN112067931A (en) * | 2020-09-16 | 2020-12-11 | 中国电子科技集团公司第二十四研究所 | Thick film resistor reliability test structure and test method |
-
1989
- 1989-07-18 JP JP18552689A patent/JPH0350785A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5499863A (en) * | 1993-05-17 | 1996-03-19 | Toyota Shatai Kabushiki Kaisha | Seat back frame |
| CN112067931A (en) * | 2020-09-16 | 2020-12-11 | 中国电子科技集团公司第二十四研究所 | Thick film resistor reliability test structure and test method |
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