JPH0350662A - Processing control system for parallel computer - Google Patents

Abstract

PURPOSE:To simultaneously execute plural task processing in conformity to an unoperating PE state by starting one task processing in assigning a necessary and minimum PE group to it, and deciding the end of processing. CONSTITUTION:In order to execute plural task processing, a host processor 1 sends a corresponding command classified by a task to each PE group assigned for each task processing through a bus 3 on the basis of a PE starting flag register 8 classified by the task, and starting the move corresponding to each task individually to each PE, and waits a command acknowledge signal individually from each PE classified by the task processing through a signal line 6. A PE command acknowledge flag register 9 classified by the task is monitored, and when all the PEs to constitute the PE group assigned for one task processing return the command acknowledge signals, it is decided that that task processing is started normally, and hereafter, a PE processing end flag register 10 classified by the task is monitored. The register 10 receives a signal to show whether the processing in each PE for each task is finished or not through the signal line 7.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a processing control method for a parallel computer, and in particular, in a parallel computer in which a plurality of processing elements are arranged in a lattice shape, the present invention relates to a method for controlling processing of a plurality of tasks by dividing the This invention relates to a control method for activating a group of processing elements to simultaneously process multiple tasks.

[Conventional technology]

Conventional parallel computers include, for example, Japanese Patent Application Laid-Open No. 60-118968.
As described in the publication, the host processing device starts all the processing elements, confirms that all the processing elements have finished processing one task, and then restarts all the processing elements again. It is started and all processing elements process the following one task.

FIG. 5 shows an example of the configuration of this type of parallel computer.

In FIG. 5, 1 is a host processing device (hereinafter abbreviated as host), and 2 is a plurality of processing elements (PE) arranged in a grid. Here, each processing element is PE
1j (i = 1 to m, j = 1 to n), 3 is information (commands, data) sent from host 1 to all PEs 2
4 is a signal line for communication between adjacent PEs; 2 is a signal line for communication between adjacent PEs;
6 is a signal line that sends a signal from each PE2 to host 1 indicating whether or not its own PE is in operation; 27 is a command that indicates that information sent from host 1 has been received from each PE2 to host 1; This is a signal line that sends an acknowledge signal. 2
8 is PE-Run indicating whether at least one PE is in operation among all PE2 or there is no PE in operation.
flag, and when the flag 28 is 1, at least 1
1 PE is in operation, and when it is 0, it indicates that there is no PE in operation.

Reference numeral 29 is a Run flag indicating whether or not the own PE is in operation; when the flag 29 is 1, it is in operation, and when it is 0, it is not in operation.

The overall operation of the parallel computer shown in FIG. 5 is as follows.

First, in order to execute one task process, host 1
A command is sent to all PE2 via path 3, all PE2 are activated, and a command acknowledge signal is waited for via signal line 27.

When all PEs 2 return command acknowledge signals via the signal line 27, it is determined that the process has started normally, and the host 1 thereafter monitors the Run flag 27*
The Run flag 28 receives an in-operation signal sent from each PE via the signal line 26, and remains at 1 when any PE 2 is in operation, and becomes 0 when all PEs are inactive. Become. When the Run flag 28 becomes 0, the host 1 determines that one task process has been completed in all PEs 2, and executes the next task process.
Send a command to E2 via path 23 and all PE2
Activate.

[Problem to be solved by the invention]

In the above conventional technology, a host processing device activates all processing elements for processing one task, identifies a state in which not one processing element among all processing elements is operating, and Since the end of one task processing is determined at the time of detection, even if the number of processing elements required for one task processing is small, PEs that do not need to be started are activated, and multiple task processing can be executed at the same time. However, there were problems with the utilization rate of processing elements and the amount of tasks processed.

An object of the present invention is to enable simultaneous execution of multiple task processes by activating divided processing element groups for multiple task processes in a parallel computer in which multiple processing elements are arranged in a grid. be.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a parallel computer comprising a plurality of processing elements arranged in a lattice shape and coupled to each other, and a host processing device coupled to each of the plurality of processing elements. The apparatus includes a means for dividing the plurality of processing elements into a plurality of groups and allocating and activating different processing element groups for each task, and a means for dividing the plurality of processing elements into a plurality of groups, and for each processing element group, processing elements in operation within the processing element group. Means is provided for detecting the absence of the task and determining the end of task processing assigned to the processing element group, and each of the plurality of processing elements is provided with means for transmitting the operating state of its own processing element to the host processing device. , multiple processing elements are divided and controlled to execute multiple tasks in parallel.

[For production]

The host processing device displays the number of processing elements required for processing the own task for each task to be processed.
Based on this, a processing element group with the minimum necessary number of processing elements is allocated and activated for each task. A processing element that has been activated returns an acknowledge signal to the host processing device when it operates normally, and returns a processing end signal to the host processing device when processing is completed. When processing completion signals are received from all processing elements, it is determined that processing of the task has been completed. Then, the inactive processing elements, including the group of processing elements for which task processing has been completed, are redivided, and the next task to be processed is assigned. This makes it possible to divide and combine processing element groups as needed, and to execute multiple task processes in parallel.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an overall configuration diagram of an embodiment of the present invention. In FIG. 1, 1 is a host processing unit (hereinafter abbreviated as host), 2 is a processing element (PE), and the processing elements 2 are arranged in a grid pattern, with adjacent ones connected to each other via signal lines 4. are combined. Here, each processing element 2 is PE1j (i=1 to m, j=1 to n
).

5 is a signal line from the host 1 to each PE to activate PE1j, and 6 is a command acknowledge signal from each PE to host 1 indicating that PE1j has received the information/activation signal sent from host 1. Sending signal line, 7 is each P
Sends a signal from the individual E to the host 1 indicating whether or not processing in the PE 1j has ended. 8 is a task-specific PE activation flag register that stores a PE activation flag for each task that instructs the PE 1j to be activated. 9 is a PE activation flag register that has activated the PE 1j. A PE command acknowledge flag register for each task stores a PE command acknowledge flag indicating that PE1j has started operating normally, and 10 stores a PE processing end flag for each task that indicates whether processing in PE1j has finished or not. This is a PE processing end flag register for each task. Since all PEs are divided into multiple groups to process multiple tasks at the same time, these registers 8, 9, and 10 each have multiple (
2 to total number of PEs). The bit length of each register corresponds to the total number of PEs. In each task-specific PE activation flag register 8, when PEjj is activated, the bit corresponding to PEjj is 1, and when it is not activated, it is O. Similarly, the PE command acknowledge flag register 9 for each task also registers the PE command acknowledge flag register 9 when the PE 1j starts operating normally.
The bit corresponding to is 1, and is O when not in operation. Furthermore, the PE processing end flag register 10 for each task also
When the process ends at PE1j, the bit corresponding to PE1j becomes 1. It is 0 when the process is not completed.

Reference numeral 11 denotes a PE processing end flag indicating whether or not the processing in the own PE has ended, and is 1 when the processing is completed, and 0 when the processing is not completed.

The overall operation of FIG. 1 is as follows. First, in order to execute multiple task processes, the host 1 sends commands corresponding to each task via the path 3 to each PE group assigned to each task process based on the task PE activation flag register 8. Each PE in the PE group is activated corresponding to each task, and a command acknowledge signal from each PE is waited for each task processing via the signal line 6. P by task
E command acknowledge flag register 9 is monitored and 1
When all the PEs constituting the PE group assigned to one task processing return a command acknowledge signal, the task processing is determined to have started normally, and thereafter the task-specific PE processing end flag register 10 is monitored. . PE processing by task The receiver receives a signal indicating whether or not processing in each PE has been completed for each task. When it is determined by this task-specific PE processing completion flag register 10 that the processing in the PE group assigned to one task processing has been completed, this PE group and the inactive PE group are re-divided into primary Assign task processing.

FIG. 2 is a detailed configuration diagram of the host processing device 1. As shown in FIG.

In the figure, the same parts as in FIG. 1 are given the same numbers.

Reference numeral 12 denotes an unused PE flag register for displaying unused PEs, and has a bit length corresponding to the total number of PEs. 13 is a main task memory that stores all tasks to be processed;
14 is the P required for task processing among the tasks to be processed.
This is a subtask memory that stores tasks whose number of E is equal to or less than a preset reference number. 15 is main memory 1
This circuit checks whether the number of PEs required for the task processing of the task in step 3 is less than or equal to a set reference number, and selects the task to be stored in the subtask memory 14. 16 is a main task execution flag register that indicates whether or not there is a task that is being processed without going through the subtask memory 14 among the tasks that are being processed by the PE group. If 1
Reference numeral 17 denotes an inactive processing element check circuit that identifies an inactive PE from the inactive PE flag register 12 and re-divides the block into a group of activatable PEs. 18 is based on the main task execution flag register 16.

This is a task selection circuit that selects either a task read from the main task memory 13 side or a task read from the subtask memory 14 side. Reference numeral 19 denotes an activated PE check circuit that compares the PE group requiring task processing with the activated PE group and checks whether the task processing can be executed. 20 is a PE activation flag generation circuit that generates an activation flag instructing PE 1j to be activated. 21 checks whether the PE 1j activated for each task has been activated normally for each task. PE by task
This is a startup check circuit. Reference numeral 22 denotes a task processing completion check circuit that checks the processing completion state of the PE 1j operating for each task and determines whether task processing has ended.

23 is PE1j command acknowledge flag data and P
This is an inactive PE flag generation circuit that generates inactive PE1j flag data from E1j processing end flag data.

The operation of the host processing device shown in FIG. 2 is as follows.

The main task memory 13 stores all the tasks to be processed with the processing order and required PE number data attached, and the subtask memory 14 stores the data specified in each task in the required PE number check circuit 15. Need to be
The E number data is compared with the predetermined reference PE number data, and tasks whose number is equal to or less than the reference number are selected, read out from the main task memory 13, and stored. The task to be processed is one read out from each of the main task memory 13 and subtask memory 14, and in the selection circuit 18, if the main task execution flag register 16 is O, the task on the main task memory side is selected, and the main task execution flag is set. If the register 16 is 1, it is determined by selecting the task on the subtask memory side. The main task execution flag register 16 indicates the task being processed by the PE group.

1. When the task is selected from the main task memory 13. At other times, it is 0.

The non-active PE flag register 12 indicates non-active PEs among all the PEs, and the non-active PE check circuit 17 re-blocks them into a group of activatable PEs. The activation PE check circuit 19 compares the required number of PEs for the task selected by the selection circuit 18 with the activation possible PE group, and if the task can be processed, the PE activation flag generation circuit 20 selects the selected task. A PE activation flag corresponding to a PE group that can be activated for processing is generated and set in one of the PE activation flag registers 8, and the corresponding PE group is activated via the signal line 5 to start task processing.

On the other hand, if task processing is impossible, the activation PE check circuit 1
In step 9, it is checked whether the selected task is on the main task memory side or on the subtask memory side, and if it is a task on the main task memory side, it waits until the activatable PE group that can process the task is divided, and then the task is transferred to the subtask memory side. If it is a task, the task is returned to the submemory and the selection circuit 18
The next task is read from the subtask memory 14 via the subtask memory 14, and a comparison check with the activatable PE group is performed.

A command acknowledge signal from the activated PE group is sent via the signal line 6, and is stored as a command acknowledge flag in each PE command acknowledge flag register 9 for each task.

The PE start check circuit 21 checks the start of task processing by comparing the PE start flag register 8 and PE command acknowledge flag register 9 of each task. When it is confirmed that all the PEs in the PE group activated to process one task have been activated normally, the activated PE flag in the unactivated PE flag register 12 is sent to The inactive PE flag corresponding to each PE in the PE group is reset (corresponding bit = 0).

A processing end signal from a PE group that has started task processing is sent via the signal line 7, and is stored as a processing end flag in each PE processing end flag register 1o for each task. The task processing completion check circuit 1o determines the completion of task processing for each task by comparing the PE command acknowledge flag register 9 and the PE processing completion flag register 10, and when it is confirmed that the processing is completed, the inactive PE flag is set. Via the generation circuit 23, set the non-active PE flag corresponding to each PE in the PE group that has completed task processing in the non-active PE flag register 12 (corresponding bit =
1) At the same time, if the task whose processing has been completed is on the main task memory side, the main task execution flag register 16 is reset.

FIG. 3 shows an example of the configuration of a task data storage area in the main task memory 13, and FIG. 4 shows a configuration example of a task data storage area in the subtask memory 14. Each task data storage area has a number indicating the execution order of the task. 24, and task processing PE data 25 indicating the number of PEs required for processing the task and the PE configuration contents are stored.

〔Effect of the invention〕

As explained above, according to the present invention, by allocating the minimum necessary PE group to one task process, activating it, and determining completion, multiple task processes can be executed simultaneously according to the state of the inactive PEs. Can be implemented. As a result, unused P
Since the rate at which E becomes an idle PE can be reduced, a decrease in the PE operating rate can be prevented. Also, among tasks, tasks that require fewer PEs for task processing are stored in the subtask memory and are executed early regardless of the execution order assigned to the task, so task processing is faster. It can also be expected to have the effect of shortening turn-run land.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention, and FIG.
3 is a detailed configuration diagram of the host processing device in the figure, FIG. 3 is a configuration diagram of the main task memory in the host processing device, FIG. 4 is a configuration diagram of the subtask memory in the host processing device, and FIG. 5 is a configuration diagram of the conventional parallel computer. It is an overall configuration diagram. 1...Host processing device, 2...Processing element (
P E), 3...Data bus, 4...Signal line between processing elements, 5...Processing element start signal line, 6...Processing element command acknowledge signal line, 8...Task-specific processing element Startup flag register, 9...Task-specific processing element command acknowledge flag register, 1o...Task-specific processing element processing end flag register, 11...Self-processing element processing end flag, 12...Inactive processing element flag Register, 13... Main task memory, 14... Subtask memory, 15...
・Required processing element number check circuit, 16...
Main task execution flag register, 17... Inactive processing element check circuit, 18... Task selection circuit, 19... Activated processing element check circuit. 2o... Processing element activation flag generation circuit, 21.
. . . Processing element start check circuit for each task, 22 . . . Task processing end check circuit, 23 . . . Inactive processing element flag generation circuit. Figure 2 FEfJL' Imperial Reihiki Figure 3 Figure 4

Claims (1)

[Claims] (1) In a parallel computer comprising a plurality of processing elements arranged in a grid and coupled to each other, and a host processing device coupled to each of the plurality of processing elements, the host processing device performs the processing of the plurality of processing elements. A means for dividing elements into a plurality of groups, allocating and activating different processing element groups for each task, and for each processing element group,
The processing element has means for detecting that there is no processing element in operation in the processing element group and determining the end of the task processing assigned to the processing element group, and each of the plurality of processing elements 1. A processing control method for a parallel computer, comprising means for transmitting an operating state of a computer to the host processing device, and dividing and controlling the plurality of processing elements to execute a plurality of tasks in parallel.