JPH03501192A - Analog-digital data storage system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Analog-Digital Data Storage System Field of Invention The present invention relates to a communication system, and more particularly to the transmission of analog signals at speeds comprising; Converts and transmits analog signals to digital for digital storage Search and use such Relating to a system for reconverting signals to analog format.

Background of the invention The prior art is replete with a wide variety of paging systems and radio-operated systems. where the message cannot be directly contacted for any reason. can be left for individuals who cannot afford it. For example, many paging systems It operates on a large, complex central processing facility where messages are queued and sent to The message is transmitted to the subscriber in digital form together with the subscriber's address code. sir Subscribers to the service are preceded by an address code for the paging unit. A base that is pre-programmed to be activated by receiving a message. It has a managing unit. A pager is a pager that allows a subscriber to receive a message and It emits an audible tone to let you know that it is being stored. The message is Messages are stored in the controller memory and are usually displayed on an LED or LCD display. It is pulled out in the form of a display message on the screen. Such a system is effective It takes very little transmission time (air time) to send a digital message. ), but the messages transmitted always have a limited duration and are A type that generally requires the subscriber to go to the nearest telephone and call the message sender. be. Furthermore, the messages being transmitted are strictly numeric, i.e. telephone numbers and An alphanumeric message must be transmitted using this alphanumeric character, unless it is of the same type. This type of paging system requires a special terminal to enter the message. The system requires an expensive computerized central messaging facility.

An audio message preceded by an address code received by a pre-programmed receiver. Other paging systems using transmitters that transmit the page in analog form can be used. Available for use. Messages are played as soon as they are received, and some units , the message can be recorded on a tape cassette for replay. this type pagers are usually relatively cumbersome and require no mechanical parts of the tape recorder. Requires substantially higher power requirements to drive.

In the field of telephone communications, a message is sent to the caller and the called party answers the phone. Let me know that you are unable to respond and send me a message to play back later. A response device equipped with one or more tape cassettes is used to record the Available for use. Transponders are readily available in single wire use and their prices are gradually decreasing. Although increasingly expensive, such devices are commonly used as part of the telephone circuit itself. is not available, and most of the existing response devices are bulky and require a substantial amount of desktop Requires space. In addition, answering equipment can be used for multiline business calls and combined line records. not readily available in the record.

Another form of message service is the so-called voice storage and retrieval system (VMS). , a voice message is left in a central message storage facility and the subscriber enters a specific code. can be used to access central computer memory and retrieve messages. Wear. These systems rely on a central system to process and store messages. It is expensive to operate in that it requires powerful computers in system equipment, and Furthermore, subscribers have to search for their phones to receive messages, so It is also inconvenient to move around. Moreover, the recipient may inadvertently tick the message. The message may not be received in a timely manner due to

two-way communications such as police and fire communications, emergency communications and the like; -way) In the field of wireless communications, the receiver is sometimes separated from the mobile unit. If the This allows the operator to receive incoming messages while away from the unit. be applied to a mobile receiver so that it can be used. Such equipment is expensive; Reliable and inexpensive message storage systems are often available on mobile units. If it were possible, it would be completely unnecessary.

The operator also sends a message to the mobile unit to transmit a prerecorded message. A system similar to a telephone answering machine to record incoming messages when you are not Also available. These systems are bulky, unreliable, and lack wireless communication. It was found that there was no flexibility in connecting with the network.

A more advanced system is described in U.S. Pat. No. 4.468.81 by Burke et al. No. 3, and US Pat. No. 4,495,647 to Park et al.

This system requires a base unit and a command program in digital form. sends the packet to the mobile unit, which receives the message in analog form. is programmed to respond to command programs. command prog In response to the ram, the mobile unit converts the message into digital form for storage. and in response to a termination command sent in digital form by the base unit. The mobile unit recording system is deactivated. Operators on mobile units: digital messages can be played back in analog form. The aforementioned U.S. patent The system disclosed in requires a sophisticated coding system in the base transmitter. and can generate command program packets and exit code signals. There must be. Additionally, the base transmitter transmits command packets as described in the aforementioned patent. It must be possible to transmit the information in a clear manner. The mobile unit is Command Pro. Receives and decodes the program packet and generates its own command program packet. must be able to be transmitted reversely to the base unit. This kind of system The mobile unit used in the system requires two separate power supplies, which making them unsuitable for portable hand-held receivers such as .

Furthermore, in the field of communications, especially wireless communications, transmission times are preferably kept to a minimum. It will be done. In wireless communication, the available channels are busy, so the transmission time There is considerable competition for it. For this reason, most paging systems are The digital format requires less time to transmit. It is involved in the transmission of messages in the form of However, the received message is a small LE D and limited to short written messages displayed on the LCD display screen; Message also requires the subscriber to go to the telephone and call the message sender. It is usually limited to the types of The limited message of such systems In addition to the digital functionality, transmission components are expensive and cannot be used to transmit digital data. A centralized computer to store analog messages for subscribers. Tametsu-ji equipment is usually required.

Therefore, you can transmit analog messages directly to a remote unit and The messages are transmitted at a high speed rate to save transmission time and are received by the remote unit. is recorded and recorded at a slower rate to restore the message to its audible state. It is highly desirable to provide a system that allows playback. As a natural result, certain To transmit analog data at a slow rate and back to its audible format It is also desirable to play messages at higher speed rates. Such a transmission procedure is Useful in transmitting music and other high fidelity analog data over telephone lines This usually adversely affects the fidelity of the transmitted data.

In such cases, in order to maintain fidelity and play at normal speed without loss of fidelity, Therefore, it is desirable to transmit data at a slow rate.

Summary of the invention In accordance with the present invention, a digital voice storage and communication system is provided, in which voice messages are selectively addressing and transmitting communication packets containing subsequent address codes; at least one transmission station and each corresponding predetermined store; at least two receiving stations, each having (1 ) a receiving circuit responsive to said communication packet; (2) a receiving circuit connected to said receiving circuit and connected to said receiving circuit; a decoder for generating a recording active signal in response to the recording communication packet; and (3) a first the audio of the communication packet in response to the recording active signal at a data rate of It includes a digital memory for storing messages, and its improvements include digital memory for storing messages. a signal conversion circuit for converting the data into analog data; and the first data rate. the stored data rate from the digital memory at a second data rate different from and a timing circuit for clocking data representing a voice message. It is characterized by

In accordance with the present invention, paging systems, telephones, multiline telephones, cellular telephones, extension telephones, etc. communications systems, telemetry systems, two-way radios and the like. Provided is an analog-to-digital data storage system that is easy to use. , an analog signal containing a voice message is transmitted at a first rate, is received, and a digital signal is transmitted at a first rate. digital format, stored in memory in digital format, and scanned. converted back to analog format and played back at a second speed. .

Data storage systems are easily installed into existing telephone and radio equipment at low cost. , operate with very low power requirements.

Data storage systems are e.g. digital codes, signal tones, dual tone multi-frequency (DTMF) to any conventional analog or digital address encoder such as It is also applied to be activated by voice activation (VOX). can. No specially modified transmitter is required for use with the system of the present invention. difference Additionally, means for deactivating the circuit after receipt of a message are provided in the data storage system. Contained in the stem itself, except for the (preferred but unimportant) address code. command data to control message reception and recording on the receiving unit. end of the message to deactivate the receiving unit. There is no need to transmit the code.

In accordance with the invention, an analog-digital data storage system is accessed from a suitable transmitter. Receiver means are included for receiving an incoming signal carrying an analog component. analog signal to a specified address code that is specific to a particular data memory system. Therefore, it is preferably preceded. The system is active, activated by incoming signals. further comprising a stage and emitting an active signal (logic high) as described and illustrated hereinafter. to activate the system circuits. The active means is the specific receiver or programmed to recognize address codes that are unique to the group It may also include a decoder. The active means, as in the case of vOX circuits, It can be activated by an incoming signal without a code to issue an active signal. system The system includes a conversion means for converting incoming analog data into digital format; and memory means for storing the converted digital data. The conversion means It also includes circuitry for converting the digital signal back to analog format. system The control means is responsive to the active signal from the decoder means to convert the conversion means and the digital memory. It is provided for activating the storage means. In a preferred embodiment, the control means Upon completion of the message or after a predetermined period of time, the conversion means and memory It also works to deactivate the means. The switching means conversion means and memory hand to play back the video in analog format. Included to activate the stage. The system handles record and playback modes. Switching means for dynamically activating and listening to incoming analog signals and and amplifier means for playing back the recorded messages.

The system of the present invention includes single line and multiline telephone systems, internal communication systems and wireless It can be easily used in wire communication systems such as line communication. therefore , the system of the present invention can be used in paging systems, two-way radio communications, cellular telephones, conventional is useful for internal telephone communication systems and telemetry systems. This issue In a preferred form, the system receives analog messages transmitted at high speed. and so that the message can be understood by the mobile operator. If you want to play back such messages at a slower speed after pulling them from memory, Applies to In this manner, the air transmission time is substantially reduced, which is The system is also used in paging systems where the specified frequencies are limited. In areas where radio frequencies are crowded, where there are many subscribers important.

According to one embodiment of the invention, the system includes a control terminal for inputting data. Contains a transmission buffer that communicates with a transmitter for sending analog and analog messages. comprising transmitter means. The system is compatible with the transmitter to receive the transmitted signal further comprising a receiver group including a receiver having a Store and extract the signal from memory and convert it to a usable format. Contains circuitry for Signal speed conversion is performed before the signal is stored in memory or After signal retrieval from the harpoon but before playback, what can happen is be understood. Further, the signal is transmitted at a second rate, recorded at a second rate, and can be played back at a third speed. Preferably the transmitter buffer The encoding means in so that the message can be sent to a specific receiver Encode an address code that can be recognized by a receiver group .

The system of the present invention is suitable for use in single line and multiline telephone systems, as well as extension communication systems. Applicable for use in wire communication systems as well as wireless communication. Sith The system is particularly useful for paging and telemetry systems, and for systems that transmit music and other data where high fidelity is required. It is also useful. The system of this invention uses commercially available paging devices. Using circuits that are easily installed with conventional transmitting and receiving equipment such as

The invention will be better understood by the following description when taken in conjunction with the accompanying drawings. It will be.

FIG. 1 is a block diagram of a digital audio storage system according to the present invention.

FIG. 2 is a schematic diagram of the audio conversion, switching and control circuit of FIG.

FIG. 3 is a schematic diagram showing the switching circuit in more detail.

Figure 4 is a schematic diagram of a portion of the switching section of Figure 2 showing the message speed control circuit. It is a diagram.

FIG. 5 is a block diagram of an extension communication system using the voice storage memory system of the present invention. This is a diagram.

Figure 6 shows the switching circuit of Figure 2 showing the circuit for manual activation of the recording function. It is a schematic diagram.

Figure 7 is similar to Figure 2 showing increased random access memory (RAM). FIG. 2 is a schematic diagram of a circuit.

FIG. 8 shows an analog system incorporating the variable speed transmission and playback functions of the present invention. 1 is a block diagram of a page paging system.

FIG. 9 is a block diagram of a transmission group according to the invention.

FIG. 10 is a block diagram of a receiver group according to the invention.

Figure 11 shows the modulation used by both transmitter and receiver groups. FIG. 2 is a block diagram of a processor circuit.

FIG. 12 is a schematic diagram of the modulation processor circuit.

FIG. 13 is a schematic diagram of a receiver group decoder circuit.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Referring to FIG. 1, an analog-to-digital data memory indicated collectively as 10 A system is shown and includes a power source 12 and receiver means 14 for receiving an incoming signal. and is constructed in accordance with the present invention. The receiver means 14 is an audible paging system or Can include a wireless communication receiver such as used in two-way wireless communication systems , or a telephone or similar type of device. As it is, the transmitter (not shown) are included in system 10. Inputs received by receiving means The next signal is transmitted from a compatible transmission device (not shown), which will be explained later. As will be seen, it has been specifically modified for use in the receiver means 14 of the audio storage system 10. There's no need to correct it. The transmission medium can be hardwired or e.g. wireless, infrared or may be wireless such as a fiber optic. The active means 16 is deco is provided in the decoder circuit to compare the incoming signal with the decoder address and determine the incoming message. A signal is sent to the system 10 to determine whether the signal is present or not. The active means 16 is For example, digital codes, signal tone codes, or dual-tone multifrequency (DT) MF) can be applied to monitor various types of coded addresses such as can be When the received signal code matches the decoder address, the decoder The coder 16 emits an active signal (pulse or continuous signal) that is used by the audio storage system. Activate the record/store function of system 10. Address code accompanying incoming message The use of audio messages is not critical and, if desired, It may also be a voice activation device that issues an active signal. In one embodiment of this invention The decoder 16 is configured to provide a continuous active signal for the duration of the incoming analog signal. The signal is terminated at the end of the analog signal. Active from decoder 16 Termination of the signal deactivates the circuitry of system 10 and returns it to standby mode. for use in other parts of the circuit in a manner described in more detail below. this invention In another embodiment, decoder 16 receives incoming messages addressed to system 10. A single pulse is issued upon detection of an active pulse, and timer means are provided to After a predetermined period of time has elapsed, the system returns to standby mode from 'C'.

Control means 18 for switching, resetting and controlling circuits of system 10 is responsive to active signals from decoder 16 and is responsive to various signals in audio storage system 10. control and activate circuits. The incoming signal is passed to the signal converting means 2C, The log is converted into a digital format and passed to the memory means 22 for digital storage. stored in memory in file format. The control means 18 also includes a switching circuit. , activates the audio storage system 10 independently of the active signal to store data from memory. Recall messages that have been recorded and transfer messages from digital to analog format for playback. - reconvert to matte.

Audible amplifier means 24 are provided to detect incoming and memory-derived audio signals. monitor the page. Input means 17 are provided to allow conversion and input by the receiver operator. Messages can be sent directly to the control means 18 for reading and storage.

Referring to FIG. 2, the control means 18, the signal conversion means 20 and the A schematic diagram of a circuit used in memory means 22 of data memory system 10 is shown. Ru. As shown in FIG. 2, certain optional features of system 10 are shown in phantom. system 10 is capable of operating without any functionality and with no specific features incorporated into the circuit. The selection of any feature will depend on the nature of the receiver in which the system will be installed, and the It should be understood that it is a matter of choice depending on the operating parameters selected. It is possible.

Power supply 12 includes any suitable source of electrical power, preferably at least 3 volts. Exists in rank. The control means 18 includes an input logic buffer 26 and a logic blocking circuit. It is in electrical communication with decoder 16 (not shown) via 56.

Logic blocking circuit 56, which is a conventional diode design, accepts active signals (logic high). ) to the microprocessor via the start line 30 and the record/play line 31. It is distributed in 32.

of the kind in which the active means 16 issues a continuous logic high for the duration of the analog signal. on completion of the analog signal, as indicated by a logic high termination. Therefore, it is strongly preferred that system No. 10 include a circuit to automatically return to standby mode. be caught. To this end, trailing edge detector 42 is connected to logic inverter 46, which is connected to the microprocessor 32 via a stop line 48 and is is explained in more detail below. The output analog signal is a conventionally designed analog output Output from microprocessor 32 via connection 95. audio switch 66 is connected to the microprocessor 32 by line 98 and is connected to the microprocessor 32 during the recording mode. Monitor incoming analog signals. of a message that the sender already has in memory. To automatically reset the system 10 so that it can record on An edge detector 36 may be included where a logic high indicates whether a logic blocking circuit 56 It is conveyed by a line 34. Leading edge detector 36 is of conventional design and is resettable. microcontroller via reset switch 38, capacitor 39 and reset line 40. The processor 32 is connected to the processor 32 .

Playback switch 58 is connected to switching controller 60. Third The switching controller 60, shown more clearly in the figure, is of a conventional design. coupled by resistors 116 and 118 in a stable (two steady state) circuit. The line 102 and the inverter 114 are connected to each other. The outputs at 160 and 160 activate switch 58 to initiate playback mode. Normally low until reversed by sexualization. switching controller 60 output remains high until it is reversed to its normal low level by reset switch 108. It remains as is.

Digital-to-analog conversion and analog-to-digital reconversion are performed by a microprocessor This is achieved by 32. Microprocessor 32 is of a commercially available design; For example, one manufactured by Toshiba with model number T6668. , provided in the circuit for analog-to-digital conversion and digital-to-analog reconversion. It is being Such conversion circuits are well known in the art and are based on internal time bases. the analog signal input at predetermined points in each time-based segment. sample and then respond to the sample level obtained during the sampling period. It operates by generating a digital output. The microprocessor 32 Applied to communicate with up to four 256 bit chips 78, totaling 102 It has 4 bit memory.

In the embodiment of the invention shown in FIG. Chip 78 allows you to record up to 128 seconds of audio data at a bit rate of 8K bps. You can store sage. Especially when receiver operators record a large number of messages. for example, the system 10 is used as a dictation unit. In some cases, additional memory banks can be added as desired or needed.

In operation, analog messages, audio or data are sent to the transmitter (as shown). (not shown) to receiver means 14 (as shown in FIG. 1). message may be transmitted by any suitable means such as wire or wireless possible, preferably such as signal tone, DTMF, digital or other similar Preferably preceded by a specified address code of the type commonly used. will be carried out. The analog signal received by receiver means 14 is transmitted to active means 16. the active means 16 is a VOX circuit. , the active signal (logic high) is passed through the input logic buffer 26 to the logic blocking circuit. It originates on Road 56. In the embodiments of the invention described so far, the decoder 16 It is of the type that emits a continuous logic high for the duration of the log signal. logic A high is passed through logic blocking circuit 56 to start line 30 and record/play It is transferred from the back line 31 to the microprocessor 32. In addition, logical block The tracking circuit 56 conveys a logic high via line 34 to the leading edge detector 36 and and closes the reset switch 38. In the closed position, reset switch 38 completes the circuit, discharging capacitor 39 and momentarily disconnecting reset line 40. microprocessor by pulling it to logic low to receive new messages. 32 and reset the memory. As a voice message for illustration purposes. The incoming analog signal, described as The signal is transmitted to the analog-to-digital conversion circuit of the processor 32.

After the analog signal is converted to digital format, the converted signal is then converted to R The data is transferred to the AM chip 78 and stored in memory. Analog signal reception stops The active then terminates a logic high, activating the trailing edge detector 42 and forcing it to a logic low. Make it. A logic low is indicated via line 44 to logic inverter 46, which The converter 46 inverts the low to a logic high which is connected to the microphone via the stop line 48. The data is then conveyed to processor 32 to complete the conversion and recording process. The end of logic high The end returns the start line 30 and record/play line 31 to their original standby logic low state. , and puts the system 10 into standby mode, which requires very little power.

Pull out and play back digital messages stored in RA M78 , the receiver operator activates the playback switch 58 to The blocking controller 60 outputs a logic high to the line 160 and the logic blocking circuit 100. , to microprocessor 32 via line 104 and start line 30. to activate the playback reproduction function.

At the same time, system controller 60 outputs a logic high via line 102. Switches 62 and 66 are closed at the same time. reconverted to analog format The signal is sent from the microprocessor 32 by line 98 to the audio switch. 66 and output audio coupling 95 to amplifier means 24 (shown in FIG. ). After the message reproduction and playback are completed, the micro Processor 32 sends a logic signal to reset switch 108 via line 110. send. Reset switch 108 returns switching controller 60 to its original state. , returning its output to a logic low and opening switches 66 and 62. Return to state. At this point, system 10 is in standby mode for conversion and storage. new incoming signals can be received.

In the embodiments of the invention described so far, messages in memory are protected. It is understood that there is no means for receiving properly addressed incoming signals. the system will automatically reset and the incoming signal will be converted to the one already in memory. stored on top of the message or data.

However, after the memory is full of messages or data that will not be played back, Selections that must be activated to initiate message recording and conversion mode. A selective reset circuit or a manual reset circuit allows the memory address selection circuit to be By adding and by expanding memory, system 10 increases Easily adapted for recording follow-up messages and protecting stored messages. It will be done.

As shown in FIG. 2, the positive edge detector 36 is removed from the system 1O and the recess The Tosui Sochi 38 uses a memory to record on top of material already stored in memory. Restart microprocessor 32 in the manner previously described to reset the memory. Manually activated to initialize. Up to 3 additional RAM chips 7g Expanded memory (labeled as RAM 2, RAJi3, and RAM 4) can be added to. As shown most clearly in Figure 3, the standard 4-bit The memory address selector 50, which is a code counter circuit, is a microprocessor. 32, allowing selection of 16 different 4-bit address combinations .

However, as is well known in the art, a two-bit counter circuit or manual I understand that other address selector circuits such as dynamic selectors can be used. be done. The message address selector 50 is connected to the start timer 30 and is a logic block. Receives a logic high from locking circuit 56. System 10 has each memory Requires further resets to record multiple messages until the link is full If the buffer is not full, a stop active is generated within the microprocessor 32 and the buffer is filled. memory for the link is protected until reset. Memories stored in memory For tsage's bure ibatsuku, set the mesohi diaddress to its initial address setting. A manual reset switch 75 is provided for constant reset. message's Playback occurs in the manner previously described, but without leading edge detector 36 in the circuit. Receives new incoming analog signals and records them on top of messages already in RAM To reset the microprocessor 32, use the reset method described above to reset the microprocessor 32. Set switch 38 must be manually activated to discharge reset line 40. Must be.

In an alternative form of the invention (shown in FIG. 3), system 10 includes trailing edge detector 42. A timer 52 may optionally be used instead. To use the timer, decoder 16 is of the type that emits a single pulse in response to an appropriately addressed incoming signal. It is especially necessary at certain times.

Connect line 53 to line 43 to receive a logic high from input logic buffer 26. By continuing, timer 52 is started by a logic high and a predetermined Upon expiration of the period, timer 52 issues a negative pulse to logic inverter 46; This issues a logic high on stop line 48, causing system 10 to operate in the manner previously described. Put it in standby mode.

As shown in FIG. 2, system 10 indicates the arrival of a signal and also indicates memory space. may also include a message indicator 54 that may also indicate that the space is full. good. The message indicator 54 may be a light, LED or an audible signal. It may be a similar device. Such devices are well known in the art and itself does not form part of this invention.

The embodiment of system 10 shown in FIGS. 2 and 3 has a recording/playback speed. optionally includes a delay circuit that allows the system to receive messages at a rate of 1 bit transmission. , convert and record and play back messages at different bit rates. I can do it. The maximum bit rate per second depends on the specific micro Determined by the processor.

As shown most clearly in FIG. , which connects microprocessor 32 by lines 74 and 76, respectively. connected to. Speed selector 7 including speed selector switches 72a and 72b 2 are connected to inverters 68 and 70.

As best seen in FIG. 3, speed selector 72 controls the playback speed. for switching controller 6 in line 160 by line 79. Connected to the output of 0.

As shown, speed selector switches 72a and 72b are both open. and inverters 68 and 7 such that both lines 74 and 76 are high. At 0, low power and high power are generated. In this state, the microprocessor Record and playback at the same speed, in this case 32K bps. play bar When the lock switch 58 (shown in FIGS. 2 and 3) is closed, the switch The high output from the switching controller 60 is passed to the speed selector via line 79. This activates and closes the speed selector switch 72a, causing the inverter 6 8 causes a high output. In this configuration, the output of inverter 68 is low. , line 74 low, while the output of inverter 70 is high and line 7 Set 6 to high. In this configuration, the microprocessor can run at speeds of 16Kbps. Play back Sage. The bit rate output is selected by the 2 and t code. record and playback opening speed selector switches 72a and 72b (label Four speeds are selectable depending on the positioning of the inputs 79 and 81).

The receiver operator can manually control the operating mode of System] 0 and send messages. system 1 to playback and receive additional messages or data. Interrupt playback at any point to return 0 to standby mode. Can be done.

Referring to FIG. 6, a typical design capacitive memory circuit 300 includes a capacitor 30 1 and a resistor 302.

Capacitive memory circuit 300 indicates that the output of line 160 is connected to each momentary closure of switch 58. The playback switch 58 and the switch are connected in such a manner that the chain causes the switch to change state. is connected to the switching controller 60. Playback switch 58 is closed , line 160 of switching controller 60 goes high and line 104 goes high. and a logic high on line 30 to microprocessor 32 (shown in FIG. 2). and activate the system into playback mode. The second of switch 58 The closure generates a high to low line transition, which is conveyed to trailing edge detector 42. It will be done. Trailing edge detector 42 initiates the signal into logic inverter 46 to convert the signal to logic high. This is transferred to the microprocessor 32 via the stop line 48. to exit the recording and data conversion mode and return system 10 to the state described above. to return to standby mode.

As mentioned above, the system of the present invention provides for playback by an operator. or for later broadcast communications when the system is used in two-way communications. ``Electronic Scratch'' allows the narrator to dictate messages into memory. Useful for use as a "chipad". Manual recording function is provided by a second capacitive memory circuit 300', which is a manual recording switch 59, a second switching It is connected to the controller 60' and the second reset switch 108'. shown The manual recording circuitry complements the manual playback circuitry as described above. However, manual Closing the recorder switch causes the switching circuit to send a high signal via line 34. leading edge detector 36, which initiates a pulse to detect the micro Trigger the processor to be initialized to receive messages as described previously. wake up The message is input by microphone 17 (shown in Figure 1). , which communicates with control circuit 18 .

FIG. 7 is a block diagram of a preferred configuration of RAM 78 of system 10. RAM 78 includes four banks 311, 312, 313 and 314, each of which is conventional The design includes four RAM chips. However, to increase memory capacity, additional Adding a RAM bank means adding additional RAM chips to the RAM bank. is understood in the same way as can be. Counter circuit 320 and RAM bank select The controller 330 addresses incoming data and messages to and from RAM. provided for recalling stored materials.

The counter circuit 320 shown is an up-down counter in which the binary output is is coupled to selector 330 .

Bank selector 330 is connected to the microprocessor on the CASI line (line 332). and R by lines 34L342, 343 and 344, respectively. Connected to AM banks 311, 312, 313 and 314. Additional CAS La Lines 333, 334 and 335 are in the same manner as the CASI line (line 332) and may be configured with an additional RAM bank selector for memory expansion.

In the preferred embodiment, counter 320 is responsive to recording and conversion modes. Generates an up count and a down count in response to the playback function It consists of aspects. With this configuration, the last message recorded will be This is the first message that is reproduced in the message. Therefore, recording and converting During operation, counter 320 is activated by control circuit 18 at the beginning of the recording and conversion mode. the counter 320 receives two pulses in response to each received pulse. Count up using a decimal code. Bank selector 33 counts binary codes. 0 from counter 320 and in response, bank selector 330 The first RAM bank 311 is selected by each count, and the second RAM bank 311 is selected by each count. 312 follows. At the start of playback mode, the counter pulses at the down input terminal. counter 320 counts down in binary code, which is It is conveyed to the bank selector 330. RAM bank selection for playback It begins with the last RAM bank that receives the message. Record or playback function During this time, the CASI line 332 of the microprocessor 32 is connected to the specified RAM bank. is switched to

In operation, multiple messages can be stored in each memory in each bank. Ru. The microprocessor used may be of static or dynamic type. Ma The static version of the microprocessor consists of a static version of RAM; The dynamic version of the processor is preferably configured with a dynamic version of the RAM. Delicious.

Referring to FIG. 5, an analog-to-digital data storage system according to the present invention A telephone system incorporating the is shown. In the example shown, generically 202 and Two transmitters/receivers, shown as 202', connect wires 20 for interconnection. 4 and common ground 205.

Each transmitter/receiver 202 and 202' is connected to a power source 212, as in a conventional telephone. Includes receiver means 214 and transmitter means 210. Transmission/reception switch 216 ( Press for calling) is provided on each transmitter/receiver 202 and 202' to Configures the transmitter circuit 222 during message transmission, and shuts off the transmitter circuit 222 during message reception. to complete the circuit to receiver 214. The transmit/receive switch 216 is for internal communication or telephone system operation. A complete dual extension communication system, telephone system and It is understood that telephone and extension telephone communication systems are available.

Encoder 218 and encoder switch 219 transmit via line 240 210. Encoder 218 may be any of the types previously described. It is often of the DTMF type used in most telephone systems. Receiving The signal transmitters 202 and 202' are shown in conjunction with FIGS. 1, 2, and 3 above. and connected to an analog-to-digital data storage system 222 of the type previously described. The decoder 220 includes a decoder 220. Transmitter/receivers 202 and 202' A message input that is activated to indicate that a message has been received and placed in memory. indicator 224. Playback switch 226 and reset switch 2 28 is provided for each circuit 222, and while the message to be recorded is being recorded, A secure switch 230 protects transmitters/receivers 202 and 202' from being overheard. receiver 214 is switched out of the circuit. playback sui switch 226 enters a personal identification code via a telephone keypad (not shown). an extra active output so that the playback function is activated by inputting May be replaced by force (not shown).

The operation of the extension communication system is illustrated in FIG. transmitter/receiver via wire 204. Complete the circuit between transmitter 210 of 202 and receiver 214 of transmitter/receiver 202' let The transmitter/receiver 202' has a transmit/receive switch 216 connected to line 217. Complete the circuit from wire 204 to analog-to-digital storage circuit 222 via and is in receive mode. Messages are sent from transmitter/receiver 202 for recording. The transmitter encodes the encoder of the transmitter/receiver 202 to send it to the transmitter/receiver 202'. Activate switch 219 to activate encoder 218 and transmit/receive issue a code for transmission to device 202'. As mentioned above, the encoder switch switch 219 is preprogrammed by the transmitter to transmitter/receiver 202'. Prefer a phone keypad for a similar device so you can enter the code. Or be prepared. Transmitter/receiver 202' has a transmit/receive switch that connects the transmitter circuit. It is shut off to configure the receiver circuit and set for reception. As shown, Security switch 230 is in the open state and messages received on circuit 222 are rather than being played back at receiver 214 in the manner described below. only recorded.

Active 220 detects the message address and if sender/receiver 202' If so, issue a logic high and write the data via active line 221. to storage circuit 222, which is rotated in the manner described in connection with FIGS. 2 and 3. 222. Conversion and recording of analog messages into digital form is performed by circuit 222 in the manner described above in connection with FIGS. 2 and 3. It is done. At the end of the message, line 110 returns to its normal high state. , switch 230 is closed to reconfigure the receiver circuit. The message is the playback Playback is possible by activating the playback switch 226. Initiates the layback circuit so that the message in memory is reconverted to analog form and received. The signal is output to the transmitter 214.

The user of the remote unit is given the appropriate code to activate active 220. As long as messages are sent even from a remote unit to transmitter/receiver 202 or It is understood that transmission, storage, and playback can occur at 202'.

As previously mentioned, transmitters/receivers 202 and 202' can communicate via two-way wireless communication or It can also include other wireless transmitters/receivers, such as those that operate optically. As understood and shown and explained in connection with FIGS. Storage system 10 can be easily installed in such a transmitter/receiver.

As described herein, the audio storage system of the present invention can be used for two-way wireless communication, telephone, Incorporated into various communication systems such as internal communications, mobile telephones and the like You can In addition to the paging system, the audio storage system of the present invention also includes: Applications in medical records, industrial monitors, such as electronic notepads and similar I'll find a use for it. The system of the present invention has a variety of receivers and Can be easily integrated into the transmitter/receiver or as an additional item It may be incorporated into conventional receivers and transmitters/receivers. The system of the present invention power requirements, the remote receiver is small and lightweight, and the necessarily limited power Particularly suitable in vaging systems with sources.

Referring to Figure 8, data can be transmitted at speeds in analog form and at different speeds. An analog communication system is shown for receiving and playing back messages. Ru. The system includes a transmitter group with a control terminal 352 for inputting data. 350, including address data and message transmission rate data, modulation and code generation means 354, ε and transmitter means 356. Data is An input from control terminal 352 to message modulation and code generation means 354 , where the incoming message is temporarily stored and the address and speed code Data is generated and the analog message is modulated to the selected transmission rate.

Contains modulated analog messages, including address code and message recording. Transmission valve preceded by code to control storage and playback speed The cut is sent to transmitter means 356 for transmission. The transmitter means 356 includes wireless, such as transmission at radio frequencies, infrared or visible frequencies; You can be as hard-to-queer as the story.

The transmitted data is transferred to a receiver capable of receiving signals from transmitter means 356. is captured by receiver group 358 including means 14. Once the signal is received The recording and playback speed code is conveyed to the decoding and modulating means 16. The address code is processed and the transmitted address code is the pre-programmed address code. compared to the code. The transmitted address code data is transmitted to the receiver group 358. When matched with preset address code, later control of recording and playback speed For this purpose, a speed code is entered into the speed memory. receiver as described above Groove 358 includes an amplifier and It includes speaker means 24 .

Coding for both transmitter group 350 and receiver group 358 , the decoding and signal modulation functions are similar, but the transmitter group 358 Signal input and control commands for the Signal inputs for the signal group are derived from the receiver 14 and control commands are provided by the decoder. from the circuit of the modulating and modulating means 16. transmitter group 350 The coding circuit is of conventional design, so for example digital code generators, signal tones, etc. code or various types such as dual-tone multi-frequency (DTMF) code generators. Code generators are used with good results. Receiver group 358 deco The code generator circuit must only be compatible with the code generator circuit of transmitter group 350. is important. As mentioned above, the code transmitted is control terminals to be received and stored by receiver group 358 352 may also be included. However, along with the transmitted signal The use of the address code is not important; the receiver group 358 is function with an audio activation device that activates the recording circuitry of receiver group 358. can be done.

The operation of transmitter group 350 is best understood in conjunction with FIG. Modulation and code generation circuit 354 includes message modulation processor 354a and code generation circuit 354. is shown schematically as including the circuitry of a code generator 354b. some pages A control terminal that may be a computer on which messages are queued. Null 352 sends analog messages and addresses to modulation processor 354a. and issues a speed code to code generator 354b. The message is modulated While retained in processor 354a, code generator 354b is used for recording and speed. An appropriate code is generated and issued to transmitter 356 for transmission. control terminal module 352 issues a command to modulation processor 354a to generate an analog message. determines the speed at which the at L/S and playback speed codes are transmitted. Immediately after, the analog message is conveyed to the transmitter for transmission at the specified rate. It will be done. As shown most clearly in FIG. 10, receiver group 358 includes receivers 14 receives the transmitted address code and conveys it to the decoder circuit 16. ．． If the address codes match, an activation command is issued to the modulation processor 354a. go The decoder circuit 16 modulates the signal corresponding to the recording speed command to a processor. The signal is sent to circuit 354a to control the recording speed. Transmitted analog message signal is conveyed from receiver 14 to modulation processor 354a, where the data is preferably digital. converted to a digital format and stored in memory. receiver group operator By activating the playback function with issued by decoder 16 in the manner described, the message is stored in memory or is called up, reformatted to analog format, and loaded with amplifiers and speakers. It is played back at the command speed via the marker means 24.

Modulation processor 354a of transmitter group 350 and receiver group 358 Modulation processor 354a is very similar and can be used for either transmit or receive. Although used, they operate in substantially the same manner. The circuit is essentially 3 performs multiple functions, circuit control and switching, memory conversion, and signal conversion . As shown in FIG. 11, the modulation processor circuit includes memory 22, control logic control circuitry for switching, resetting and control functions in response to commands; 18, and converting the data contained in the signal from analog to digital for storage. and for transmission or playback as detailed above. It includes a signal conversion circuit 20 for converting from digital to analog.

Referring to FIGS. 12 and 13, the modulation profile shown in FIGS. Control means 18, signal conversion means 20 and memory means 22 of processor circuit 354a A schematic diagram of the circuit used in is shown. The word “audio” refers to the data being processed. Although used ubiquitously for the transmission of voice messages, this invention is The system is not limited to other data types and playbacks. It is understood that the ku form is used similarly.

As shown in FIGS. 12 and 13, the modulation process of transmitter group 350 Certain functions not used in receiver circuit 354a provide modulation for receiver group 358. located in processor circuit 354a. The following description of the modulation processor circuit is based on the receiver group. Loop 358 will be described in conjunction with modulation processor 354a. However, especially the fingers Unless otherwise specified, the description is based on the circuitry of modulation processor 354a of transmitter group 350. Equally suitable for roads.

The system receives, records, and plays back messages at different bit rates The playback speed circuit previously described that allows clearly indicated and explained in more detail below. Speed circuit is line 74 and a speed switch (inverter) connected to microprocessor 32 by 76. data) 68 and 70. Speed selector 72 controls the speed of inverters 68 and 70. Operated by output. A speed selector 72 is used to control the playback speed. For this purpose, lines 79 and 81 connect the output of switching controller 60. Continued. In the modulation processor 354a of the transmitter group 350, ) The playback speed is under the control of control terminal 352 and therefore Inverter 68 and 70° speed selector 72 and associated circuitry are not used. not present.

Messages are always transmitted at the same speed, allowing fixed recording and playback speeds. decoder 16 has a fixed recording and playback speed code. can be set in advance to issue. However, for maximum flexibility , the same receiver group receives and records another message transmitted at a different rate. and playback so that the decoder 16 can record and play back different Preferably, it is adapted to issue a playback speed code.

In operation, data to be transmitted is sent to the modulation processor of transmitter group 350. 354a, and is held there waiting for a transmission command. transmission The command includes an address code and a speed code, which is generated by code generator 354b. and then to transmitter 356. Speed code and transmission commands immediately Later, the command is sent to the microprocessor 32 and the message is sent to the memory 22. and played back to the transmitter at the commanded playback speed.

Used to store message data in digitized format in memory. The signal conversion circuit 20 converts the data into an analog file before being conveyed to the transmitter 356. It is understood that the same circuitry is used to convert back to format.

Analog messages, voice or data, are transmitted to receiver 14 by transmitter 356. sent. Messages can be generic such as tone, DTMF, digital or the like. preceded by a specified address code of the type used for and may also include a message termination code.

Referring to FIG. 13, where like numbers refer to like parts, decoder 16 is connected to line 371. By providing speed memory 370 that communicates with Different recording and playback speed codes for each individual message A decoder 16 is used to issue the .

Line 371 is an active line and is connected to the decoder via lines 373 and 374. speed memory 370 to receive the playback speed code output from 16; Activate.

The playback speed code is specified by counter 320 in speed memory 370. This is stored in the corresponding sector of RAM 78 where the message is stored. Also select Kuta. The playback speed code is decoded and stored in memory 370. When activated, line 371 is disabled and line 372 is enabled. deco 16 decodes the recording speed rate and this command causes lines 373 and 374 to and a recording speed memory sector of speed memory 370.

Line 372 is then disabled and line 381 from decoder 16 is enabled. Ru. Line 381 is an input logic buffer that functions as shown in connection with FIG. Activates the system's record and playback circuitry via the buffer 26.

Line 380 couples speed memory 370 to active line 381 to connect speed memory 370 to active line 381. Speed memory 370 to select recording speed from memory when activated. Activate.

The recording speed code is transferred from memory to microprocessor 32 via bus 390. conveyed to the input. The record command is issued by decoder 16 as previously described. line 381 is disabled.

For playback, counter 320 is loaded from RAM 78 in the manner previously described. sector along with the corresponding playback speed code from speed memory 370. select.

During playback, line 380 is disabled and speed memory 370 is This causes the playback speed code to be generated via line 390. is conveyed to the speed circuit of microprocessor 32 to set the speed.

The playback speed code is stored in a sector of RAM 78 and a corresponding sector of speed memory 370. messages to which codes are associated. In this manner, Stored messages are played back at the appropriate speed. playback speed code.

No memory address circuit is required for the transmitter group modulation processor 354a. No, because message storage is under control of control terminal 352. be.

Being able to transmit and playback at different speeds substantially reduces transmission time. , making analog message browsing practical. In addition, transmission is carried out over telephone lines. Data that must be sent is sent more slowly to maintain message fidelity. transmission at a higher speed and later playback at normal speed without loss of fidelity. I can do it.

Having described the invention in connection with specific preferred embodiments, it is clear that many (modifications) and It is understood that modifications and variations may be made, all reflecting the true spirit and scope of the invention. Go inside.

~ ~ Copy of amendment and submission of translation (Article 184-8 of the Patent Law) January 24, 1990

Claims (19)

[Claims] 1. A digital voice storage and communication system with an address followed by a voice message. at least one selectively addressing and transmitting communication packets including a code; a transmission station (350); at least two, each having a corresponding predetermined stored address; a receiving station (10, 358), each receiving station (10, 358); a receiving circuit (14, 214) responsive to the communication packet; connected to the receiving circuit and generating a recording active signal in response to the communication packet; a decoder (16, 220), the audio message of the communication packet in response to the record active signal at a first data rate; a digital memory (78) for storing messages; The improvements are: Signal conversion circuit (20, 222) for converting digital data to analog data )and, data from the digital memory at a second data rate different from the first data rate. A timer for clocking data representing stored voice messages. What is claimed is: 1. A digital voice storage and communication system comprising: 2. The decoder (16, 220) further comprises a separate recording active from the transmitter. Regardless of the signal, the predetermined stored address is sent to the communication packet. and automatically issuing said record active signal in response to said comparison. Digital audio according to claim 1, characterized in that it includes a comparator for generating a digital audio signal. Memory communication system. 3. The conversion circuit (20, 222) converts the voice message of the communication packet into converting from analog to digital format and converting the digital data at the first data rate; Digital audio storage according to claim 1 or 2, recorded in a digital memory (78). Communications system. 4. The signal conversion circuit (20, 222) is configured such that the decoder (16, 220) When the recording active signal ceases to be generated, the voice message in the communication packet is A further feature is that the conversion from analog data to digital data is completed. 4. The digital voice storage and communication system according to claim 3. 5. said digital memory (78) is capable of recording new voice messages; Edge detection to automatically reset digital voice storage and communication systems to 4. A device according to claim 1, 2 or 3, characterized in that it further comprises a device circuit (36). Digital voice storage communication system. 6. The communication packet is a rate defining the second data rate stored in the digital memory (78); Claim 1, 2 or 3, further comprising degree code data. Digital voice storage communication system. 7. The signal conversion circuit (20, 222) is terminated upon expiration of a predetermined period. and then the digital memory (22, 78) records a new voice message. further comprising a timer (52) for enabling recording of the A digital voice storage communication system according to claim 1, 2 or 3. 8. Further, the communication packet comprises a voice message of variable length. A digital voice storage and communication system according to claim 1, 2 or 3, characterized in that: 9. The digital memory (22, 78) stores digital voice messages having different lengths. 4. The method according to claim 1, 2 or 3, further characterized in that the sage is stored sequentially. digital voice storage communication system. 10. retrieving the voice message stored in the digital memory (78); and representing the stored voice message at the second data rate. Operator-activated playback to initiate analog data clock operations Claim 1, 2 or 3, characterized in that it further comprises a switch (58, 226). 3. The digital voice storage communication system according to 3. 11. The voice message is received and recorded in the digital memory (78). message indicators (54, 224) to inform the operator that ) The digital audio according to claim 1, 2 or 3, further comprising: Memory communication system. 12. The communication packet includes command data, the address code and the The command data is transmitted to the sound without substantial delay in the communication data packet. Claim 1, 2 or 3. The digital voice storage communication system according to 3. 13. moreover, an operator for storing in said digital memory (78) at said second rate; further including a recording switch (59) to enable the person to dictate the message. The digital voice storage communication system according to claim 1, 2 or 3, characterized in that . 14. Further, said transmission station (350) transmits voice messages at a third rate. a second memory for storing the data; accessing a voice message from said second memory and transmitting said voice message at a fourth rate; a transmission circuit for transmitting messages, and the fourth speed is higher than the third speed. Digital audio storage communication according to claim 1, 2 or 3, characterized in that system. 15. Claim further characterized in that the fourth speed is equal to the first speed. 15. The digital voice storage communication system according to item 14. 16. The second memory stores messages in a stacked sequential order. The digital voice storage communication system according to claim 14, characterized in that: 17. Monitoring the voice message recorded in the digital memory (78) The digital memory (78) includes a counter circuit (50, 320) for When it is full, the counter circuit (50, 320) is initialized and at the same time the previous counter circuit (50, 320) is initialized. The digital memory (78) erases the oldest recorded voice message. Digital sound according to claim 1, 2 or 3, characterized in that it enables Voice memory communication system. 18. moreover, operating said voice message previously stored in said digital memory (78); further including a message indicator (54, 224) for informing the The digital voice storage communication system according to claim 1, 2 or 3, characterized in that: 19. The communication packet is further characterized in that it includes speed data defining said first data rate. 4. A digital voice storage and communication system according to claim 1, 2 or 3.