JPH0349090A - Serial access memory - Google Patents

Abstract

PURPOSE:To improve economizing with the simplified constitution of the system by converting an address designated signal of the external input into a real address signal, comparing it with the output of a serial address counter and generating a reset signal. CONSTITUTION:The address designating signal inputting from the outside is converted into the real address at an address conversion circuit 10 and compared with the output of the serial address counter at the respective converters Co-Cn of a reset address detection circuit 30 and in the case of coincidence the reset address is detected. In response to the reset address the reset signal is outputted from a reset signal generation circuit 40 and an address pointer 7, counter 20 are resetted. Consequently, with the simple constitution eliminating outside reset generation circuit, the economization of the serial access memory is en hanced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a serial access memory used in video systems, etc., in which data is serially read or written, and in particular to its reset control method. .

(Prior art) Conventionally, as a technology in this field, Japanese Patent Application Laid-Open No. 61-2
Some of these were described in Publication No. 73793, etc. That-
An example of the configuration is shown in FIG.

FIG. 2 is a block diagram showing an example of a configuration of a conventional serial access memory.

This serial access memory uses external clock signal Pc
For example, a serial access control circuit 1 generates an internal clock signal Pci of one pulse at the rising edge of O, and an internal reset signal generation circuit 2 generates an internal reset signal Pr by taking in an external reset signal Pro using an internal clock signal Pc. , is equipped. External reset signal Pr
o is generated by determining the reset timing by a reset timing control circuit (not shown) outside the memory. The internal reset signal generation circuit 2 is composed of a delay type flip-flop (hereinafter referred to as D-FF) and the like.

On the output side of the serial access control circuit 1, in addition to an input control circuit 3 and an output control circuit 4 which are activated by an enable signal (not shown), data Din and Dout are input/input by a person/output control circuit 3.4. An input/output circuit (hereinafter referred to as an I/'O circuit) 5 whose output is controlled is connected. A data bus 6 is controlled on the output side of the I10 circuit 5.

Further, an address pointer 7 consisting of a plurality of registers EO to En is connected to the output side of the internal reset signal generation circuit 2, and the output side of each register EO to En is connected to the data transfer gate 8. The data transfer gate 8 is
Multiple pairs of N-channel type MO8) transistors (hereinafter referred to as NMO
NM of each pair of QO−Qn″′c elliptical configurations (referred to as 8)
O3QO-Qn are connected between data bus 6 and data register 9. The data register 9 stores data and is composed of a plurality of flip-flops (hereinafter referred to as FF) RO to Rn each consisting of anti-parallel inverters.

FIG. 3 is an operational waveform diagram of FIG. 2 during reading, and the operation of FIG. 2 will be explained with reference to this diagram.

The output of the output control circuit 4 causes the I10 circuit 5 to enter the data read mode. When the external reset signal Pro is input, the internal reset signal generation circuit 2 outputs a 1 shift pulse, that is, an internal reset signal Pri, at the rise of the external reset signal Pro. Then, the output PeO is sequentially output from registers EO to En in address pointer 7.
~Pen comes out and NMO8QO in data transfer gate 8
~Qn are turned on in order <, NMO8QO~Qn are turned on in order, FFRO~R in data register 9
n stored data are sequentially output to the data bus 6, and the data on the data bus 6 is read out in the form of serial data Dout via 1!15 110 times.

Here, when the external reset signal Pro is input, the serial access control circuit 81 takes in the external reset signal Pro using the internal clock signal Pci, outputs the internal reset signal Pri, and resets the address pointer 7. Then, only the register EO in the address pointer 7 is reset to "1", and the other registers E2 to En are reset to "0".Thereby, the output PeO of the address pointer 7 causes the NIVIO3 in the data transfer gate 8
QO to NMO8Q1. Q2. ...Turn on in order of 8 and so on.

(Problems to be Solved by the Invention) However, the serial access memory having the above configuration has the following problems.

In the conventional serial access memory, the address pointer 7 is reset by determining the reset timing outside the memory and inputting the external reset signal Pro to the internal reset signal generation port u2. Therefore, even in devices that are not very complex, such as video systems, and whose reset timing is a fixed address, a device external to the memory that controls the reset timing is required. This poses a problem of complicating the system and increasing costs, and it has been difficult to solve these problems.

The present invention addresses the problem that the prior art had, in a serial access memory where the reset timing is determined by an address, a reset timing control device is required outside the memory, which complicates the system and increases costs. This provides a serial access memory that solves the following problems.

(Means for Solving the Problems) In order to solve the above problems, the present invention sequentially designates addresses using a data bus, a data register for storing data, and clock I3, and designates an initial address using a reset signal. This is a serial access memory equipped with an address pointer and a data transfer gate that sequentially connects the data bus and the data register according to the output of the address pointer, to which the following circuit is added. That is, an address conversion circuit that converts a coded reset address designation signal input from the outside into an actual address, a serial address counter that sequentially outputs addresses in response to a clock signal and is reset by a reset signal, and the address conversion circuit. A reset address detection circuit detects a reset address by comparing the power of both the circuit and the serial address counter, and the output of the reset address detection circuit is input, and the reset signal is sent to the address pointer and serial address in synchronization with the clock signal. A reset signal generation circuit for outputting to the counter is provided within the serial access memory.

(Function) According to the present invention, since the serial access memory is configured as described above, the designated reset address converted by the address conversion circuit and the current address designated by the serial address counter are detected by the reset address detection circuit. When the two addresses match, the reset address detection circuit outputs a match signal. Then, the reset signal generation circuit inputs the signal in the matching state and outputs a reset signal in synchronization with the clock signal,
The address pointer and serial address counter are reset by the reset signal. Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a schematic configuration block diagram of a serial access memory showing an embodiment of the present invention, and the same elements as the conventional elements in FIG. 2 are given the same reference numerals. There is.

This serial access memory is provided with a reset timing control circuit inside the memory in place of the conventional external reset signal Pro and internal reset I/signal generation circuit 2 in FIG.

This reset timing control circuit includes an address conversion circuit 10, a serial address counter 20, a reset address detection circuit 30, and a reset signal generation diagram n40.
It consists of

The address conversion circuit 10 is a circuit that converts the coded reset address designation signals SO to Sn into addresses PAO to PAn and outputs the addresses PAO to PAD to the reset address detection circuit 30, and is composed of an encoder. . The serial address counter 20 is incremented (incremented) by, for example, +1 based on the internal clock signal Pc generated by the serial access control circuit 1 shown in FIG. It has a function of outputting to the detection circuit 30.

The reset address detection circuit 30 detects addresses PAO to P
This circuit compares An and PBC)-PBn and outputs signals PCO to PCn to the reset signal generation circuit 40 when they match, and is composed of a plurality of detection circuits CO to Cn. The signal generation circuit 40 inputs signals PCO to PCn and generates a reset signal P in synchronization with an internal clock signal Pc.
This circuit generates D, and its output side is connected to the serial address counter 20 and the address pointer 7.

Although not shown in FIG. 1, on the data bus 6 side, the I10 circuit 5, input/output control circuits 3, 4, and
and a serial access control circuit 1 are connected.

In this serial access memory, a specific example is shown in FIG. 4 in which the reset address designation signal is set to 1 bit of SO and the serial address is simplified to 3 bits.

In FIG. 4, from the address conversion circuit 10 to the address PAO
(=A, PL, P2), PAL (-P hundred, Pl, P
'Ding) is output. The serial address counter 20 has three FFs 21-0 to 21-2 connected in m1M, and each of these FFs 21-0 to 21-2 has an address A.
O-A2 is output and its address AO-A2
is inverted by the inverters 22-O to 22-2, and a reverse phase address λ"Φ- to λ is output. The address λ is A1.
．． PBO at A2, ττ, A1. The FBI is made up of τ. The reset address detection circuit 3o has detection circuits Co and CI, which are connected to a three-man NAND gate 31.
-1.31-2.32-1.32-2, and 2-man power NO.
It is composed of R gates 33-1 and 33-2. Also,
The reset signal generation circuit 40 includes a two-man NOR gate 41 inputting signals PCO and PCI, and an internal clock signal P.
A two-man power NOR gate 43 is connected to the output side node N41 of the NOR gate 41 and the output side of the inverter 42.

The reset address code shown in FIG. 4 is shown in Table 1 below, and its operating waveform diagram is shown in FIG.

Table 1 With the above configuration, the operation of the serial access memory shown in FIG. 1 will be explained.

In FIG. 1, when the internal clock signal Pc is supplied, outputs PeO to Pen are sequentially output from the registers EO to En in the address pointer, and NMO8QO to Qn in the data transfer gate 8 are turned on in sequence. , then the data stored in FFRO to Rn in the data register 9 is sequentially output to the data bus 6, which is connected to I10 in FIG.
It is output via the circuit 5 in the form of serial data Dout. When writing serial data Din, the serial data Din is input to the data bus 6 via the I10 circuit 5, and the data on the data bus 6 is stored in the data register 9 in order via the data transfer gate 8. be done.

In the reset operation, reset address designation signals SO to Sn inputted from the outside are converted into addresses PAO to PAn by the address conversion diagram n10, and are applied to the reset address detection circuit 30. Reset address detection circuit B30
are the output data PAO to PAn of the address conversion circuit 10
and the output data PBO~ of the serial address counter 20
PBn, and when they match, the signals PCO~PCn
is output and applied to the reset signal generation circuit 40.

The reset signal generation circuit 40 outputs a reset signal PD in synchronization with the internal clock signal Pc, and provides it to the address pointer 7 and the serial address counter 20. As a result, the address pointer 7 and the serial address counter 20 are reset, and then the internal clock signal Pc
starts operation from the initial state.

Next, referring to FIG. 5, when the reset address designation signal SO is at "L" level in FIG.
100'', the reset signal PD is automatically output and the reset state is established.

When the internal clock signal Pc is supplied, the above-described serial memory access is performed in synchronization with the internal clock signal Pc, and as shown in FIG.
At times ja-2, ja-s of 1, the output addresses AO1λ0 to A2. A2 is incremented.

At this time, the reset address designation signal SO is fixed at "L".When time τn arrives, the output address A2 is "L".
”, A1 becomes “L”, and AO becomes “L”. At this time, the output signal PCO of the detection circuit CO becomes "L", and the output side node N4 of the NOR gate 41 in the reset signal generation circuit 40
1 becomes "L".

When the internal clock signal Pc becomes "H" at time to, the reset signal PD output from the reset signal generation circuit 40 becomes "H" since the node N41 has become "L". That is, serial address counter 20 "100"
At time 10 when the next internal clock signal Pc rises, the reset signal PD automatically becomes "H" and the address pointer 7 is reset. At the same time, the serial address counter 20 is also reset, and the output address of the serial address counter 20 becomes "000".

After that, at time TO in the new serial cycle T2,
The internal clock signal Pc becomes "L", thereby the reset signal PD#, )L", and the serial address counter 20 increments to '001'. From then on, at time t1. tl.

The normal serial access cycle continues.

In this embodiment, an address conversion circuit 10, a serial address counter 20, a reset address detection circuit 30, and a reset signal generation circuit 40 are provided inside the memory, and reset can be performed automatically by external input reset address designation signals SO to Sn. As a result, control of the reset address of the serial access memory (that is, the serial memory bit length (R0 to Rn bit length)) can be realized without providing an external reset means. In particular, in a video system, etc., if you want to automatically reset the serial memory with a specific address of several bits (reset address designation signals SO to Sn), the reset address is encoded, and the encoded reset address designation signals SO to Sn Since the automatic reset timing can be set by inputting , it is possible to provide a low-cost reset means with a simple configuration and high timing accuracy.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.

(i) The overall configuration of the serial access memory may be modified to a configuration other than that shown in FIGS. 1 and 2.

For example, a memory cell array may be connected to the data register 9 via a transfer gate, and the row direction of the memory cell array may be selected by a row decoder or the like.

(ii) Address pointer 7, data transfer gate 8
, the data register 9, etc. may be constructed of other elements such as a P-channel MOS transistor, a complementary MOS transistor (CMO3>, etc.).

(iii) Address conversion diagram 1i' provided inside the memory! 10, serial address counter 20, reset address detection circuit 30, and reset signal generation circuit 4
0 may also be configured with circuits other than those shown, or other circuits such as a latch circuit may be added to improve their timing accuracy.

(Effects of the Invention) As described above in detail, according to the present invention, since the address conversion circuit, serial address counter, reset address detection circuit, and reset signal generation circuit are provided inside the memory, the coded reset address By inputting a designated signal from the outside, memory can be reset automatically and with highly accurate timing. Moreover, since the reset address, that is, the serial memory bit length can be controlled without providing an external reset means, the effects of system simplification and cost reduction can be expected.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a serial access memory according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional serial access memory, FIG. 3 is an operation waveform diagram of FIG. 2, and FIG. 4 is a block diagram of a conventional serial access memory. 5 is a main circuit diagram showing a specific example of FIG.
The figure is an operational waveform diagram of FIG. 4. 6... Data bus, 7... Address pointer, 8... Data transfer gate, 9...
...Data register, 10...Address conversion circuit, 20...Serial address counter, 30
...Reset address detection circuit, 40...
...Reset signal generation circuit, Pc...Internal clock signal, PD...Reset signal, SO~Sn
...Reset address designation signal.

Claims (1)

[Scope of Claims] A data bus, a data register that stores data, an address pointer that sequentially designates addresses using a clock signal and designates an initial address using a reset signal, and In a serial access memory equipped with a data transfer gate that is sequentially connected to a data register, an address conversion circuit that converts a coded reset address designation signal input from the outside into an actual address, and a clock signal. a serial address counter that sequentially outputs addresses and is reset by a reset signal; a reset address detection circuit that detects a reset address by comparing the outputs of both the address conversion circuit and the serial address counter; and the reset address horizontal output circuit. What is claimed is: 1. A serial access memory, comprising: a reset signal generation circuit that inputs an output and outputs a reset signal to the address pointer and the serial address counter in synchronization with the clock signal.