JPH0346823A - A/d converter for rf - Google Patents

Abstract

PURPOSE:To minimize the noise in the vicinity of a frequency in use with a low distortion and a wide dynamic range by applying an oversample type A/D converter, which is based on a DELTA-EPSILON modulator used as a band-pass filter for a high frequency signal, to an ultrasonic system. CONSTITUTION:A sampled analog signal having a center frequency f0 is inputted to a computing element 1. Since the output of a band pass filter (BPF) 12 is inputted to the computing element 1 also in a steady state, addition/subtraction is performed to execute the operation of signals having the same phase in accordance with the polarity of an input signal. Only a signal having the center frequency f0 out of the difference signal is integrated and passes through a BPF 11 and is encoded by a comparator 2. This encoded signal is integrated by the BPF 12 and is converted to an analog signal having the center frequency f0 and is operated as the sampled signal just preceding the input signal in accordance with its polarity to obtain the difference between signals having the same phase. The encoded signal of the output of the comparator 2 is converted to a digital signal by a decimation filter 5 and is outputted, and thus, the input analog signal is converted to the digital signal.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention is an AD converter that converts an analog signal into a digital signal.
The present invention relates to a converter, and particularly to an RF AD converter that converts an RF analog signal into a digital signal.

(Prior art) There are many methods for AD converters that convert analog signals into digital signals, but oversampling type Δ which applies the Δ-Σ modulation method used in data communications
- Because the Σ modulation type AD converter has the advantage of good linearity or a good S/N ratio due to decimation,
It is widely used in recent audio systems. First, Δ
Explain the principle of modulation. FIG. 9 is a block diagram of the Δ modulator. In the figure, reference numeral 1 denotes an arithmetic unit that calculates the difference between the sampled input analog signal and the signal just before the input analog signal to which the output of the comparator 2 is fed back. The comparator 2 compares the output of the arithmetic unit 1 with the zero potential, and creates a step wave that sets +Δ if positive and -Δ if negative.
When the value is +Δ, it is encoded as “1” and when it is −Δ, it is encoded as “0”. The integrator 3 integrates the encoded output of the comparator 2, converts it into an analog signal, feeds it back to the arithmetic unit 1, and supplies the analog signal immediately before the current sampled analog signal to the arithmetic unit 1. This converted waveform is shown in FIG. (A) is a diagram showing an input analog signal a and a pulse signal S approximated by a step wave using a quantization step width Δ, and (B) is a diagram showing an encoded signal C converted from the pulse signal S.

The main drawbacks of Δ modulation as described above are that DC signals cannot be transmitted and that the S/N ratio changes with the signal frequency.

This drawback can be solved by providing an integrator on the input side of the comparator 1. Such a modulator is called a Δ-Σ modulator, and its circuit is as shown in FIG. In the figure, the same parts as in FIG. 9 are given the same reference numerals. 4 is an integrator added to the Δ modulator in FIG. Whereas the delta modulator outputs the difference in signal amplitude, the delta-sigma modulator carries information about the actual signal amplitude.

The Δ-Σ modulation type AD converter converts the encoded signal output of the Δ-Σ modulator shown in FIG. 11 into a digital signal by passing it through a decimation filter. Figure 12 shows Δ
Oversampling type Δ−Σ using −Σ modulator
FIG. 2 is a block diagram of a modulation type AD converter. In the figure, the first
Parts equivalent to those in Figure 1 are designated by the same reference numerals. 5 is a decimation filter that converts the input encoded signal C into a binary string digital signal, and this circuit converts the input analog signal into a digital signal.
It is a converter.

(Problem to be Solved by the Invention) By the way, the above-mentioned Δ-Σ modulation type AD converter is suitable for handling baseband signals, but it is suitable for handling baseband signals, which are inherently high-frequency and have a pronounced band-limiting property, such as ultrasonic signals. It is not suitable for handling signals. This is because the Δ-Σ modulation type AD converter has conversion characteristics that start from direct current, so it is necessary to have conversion characteristics with less noise over the frequency band from direct current to high frequency regions. This is a big waste for circuits that handle only In addition, the frequency of the clock input to the comparator 2 is required to be about 200 times that of the input signal, and if you try to use it for ultrasonic waves around 2 MHz, the frequency of the clock input to the comparator 2 will be about 40
A clock rate of 0 MHz would be required. Currently, gate arrays that operate with a clock of 2 to 4 GHz are being created using GaAs logic elements or high-speed bipolar logic elements, but these devices have low noise and good conversion characteristics for signals around 2 MHz in the ultrasonic frequency band. It is difficult and impractical to have one.

The present invention has been made in view of the above points, and its purpose is to apply an oversampled AD converter based on a Δ-Σ modulator for band-pass applications to an ultrasound system for high-frequency signals. The object of the present invention is to realize an RF AD converter that takes advantage of its low distortion rate, wide dynamic range, and low cost, and has the least noise near the operating frequency.

(Means for Solving the Problems) The present invention for solving the above-mentioned problems subtracts an in-phase signal between a sampled input high-frequency analog signal and a signal immediately before the signal fed back in a steady state. an arithmetic unit, a bandpass filter that integrates and passes only a high-frequency signal that matches the center frequency of the input high-frequency analog signal, and compares the output signal of the bandpass filter with a zero potential, and encodes it based on its sign. a comparator that outputs a signal, and integrates the output coded signal of the comparator, passes only the high-frequency analog signal that matches the center frequency, and feeds it back to the arithmetic unit. It is characterized by comprising a bandpass filter that supplies a sampled signal, and a decimation filter that converts the output signal of the comparator into a binary series digital signal.

(Function) The sampled input analog signal is subjected to calculation of the signal difference in the same phase with the sampled signal just before the sampled input analog signal of the output of the BPF 12 fed back in the arithmetic unit 1, and is integrated in the BPFII, Only signals at the center frequency of the input analog signal are allowed to pass.

The comparator 2 compares the input signal with zero potential and encodes it depending on whether it is positive or negative. The BPF 12 integrates the encoded signal and restores it to an analog signal, and inputs only the signal having the frequency of the input signal to the arithmetic unit 1. Comparator 2
The output encoded signal is converted into a digital signal in a decimation filter 5.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. In the figure, parts equivalent to those in FIG. 12 are given the same reference numerals. In the figure, 11 is the center frequency f of the input analog signal. A bandpass filter (hereinafter referred to as BPF) passes the signal in the frequency band centered on and inputs it to the child terminal of comparator 2.
12 is a pass frequency band f which integrates the encoded signal output from the comparator 2, restores it to an analog signal, and inputs it to the arithmetic unit 3. It is a BPF with an integral action. This circuit consists of integrators 3, 4, and 4 of the Δ-Σ modulation type AD converter shown in FIG. The circuit has BPF12 and BPF11 replaced.

Next, the operation of the embodiment will be explained. The center frequency is f. The sampled analog signal is input to the arithmetic unit 1. In a steady state, the output of the BPF 12 is also input to the arithmetic unit 1, and addition and subtraction are performed so as to subtract signals of the same phase according to the polarity of the input signal.

This difference signal is f in BPFII. Only the signal centered at is integrated, passed through and encoded in comparator 2. This encoded signal is integrated in the BPF 12 and has a center frequency f. The input signal is converted into an analog signal, and the calculation unit 1 calculates the difference between the in-phase signals according to the polarity of the sampled signal immediately before the input signal. The encoded signal output from the comparator 2 is converted into a digital signal by the decimation filter 5 and output, which means that the input analog signal has been converted into a digital signal.

BPF12 and BPFII actually use the following RF integrator. FIG. 2 is a circuit diagram of an RF integrator used in the BPF 12. In the figure, 21 is an input resistor connected to the input terminal of the operational amplifier 22. The output of the operational amplifier 22 is connected to four integrating capacitors 23a and 2 of equal capacitance.
3b, 23c.

An integrating capacitor 23 divided into 23d is connected to each integrating capacitor 23a, 23b, 23c, and 23d.
The other terminal of the rotary switch 24 is connected to four fixed contacts arranged by dividing the entire circumference of the rotary switch 24 into four equal parts.

When a signal is input to this circuit, the input signal is input to the input resistor 2
1 and is input to the input terminal of the operational amplifier 22. The operational amplifier 22 constitutes an integrator whose output terminal is negatively fed back to the input terminal by integrating capacitors 23a to 23d. The low-return switch 24 rotates at an angular velocity of 2πf, and sequentially connects the moving contacts to the four fixed contacts at equal time intervals, that is, at 1/4 cycle intervals.
3a to 23d are switched and connected to the input terminals of the operational amplifier 22. Therefore, the operational amplifier 22 has a frequency f. In response to the input signal j-, a signal having a waveform as shown in FIG. 3 is output. The figure shows the input frequency f. The waveform of the output signal for the sine wave signal is shown. This waveform is 0', 9
The waveforms shown in the figure are such that the integrating capacitors 23a, 23b, 23c, and 23d are charged every 1/4 cycle of 0@, 180', 270'', respectively.If the input signal is a signal with a frequency different from the frequency f. In this case, the voltage charged in the integrating capacitors 23a to 23d changes, becomes zero on average, and is not output.

Even if the input signal is the encoded signal output from the comparator 2, the same operation is performed. By using the RF integrator of FIG. 4 in the BPF 12 of the embodiment of FIG. 1, the frequency f. It will output only the high frequency signal of.

Moreover, the circuit shown in FIG. 4 is used for BPFII.

In the figure, an input signal (fo) is input to a rotary switch 31 via an input resistor 30. An integrating capacitor 32 divided into four integral capacitors 32a, 32b, 32c, and 32d of equal capacity is inserted between the rotary inch 31 and the ground. This circuit is also R in Figure 2.
Similar to the F integrator, [rotary switch 3] - is 2πf,
) at the angular velocity of the integrating capacitors 32a, 32b, 32c,
32d and frequency f every 1−/4 cycles. , but the frequency f. Signals outside the range are averaged to zero and have no integral effect. Therefore, the signal passing through C is f. Only the signal centered on . As described above, according to this embodiment, it is possible to obtain a Δ-Σ modulation type AD converter that AD converts only the RF multiplied signal centered on f +, +. Furthermore, in this embodiment, an AD converter with less noise in a necessary frequency band can be obtained compared to a Δ-Σ modulation type AD converter in which DC is mainly used.

FIG. 5 is a diagram comparing the noise characteristics of the original Δ-Σ modulation type AD converter and this embodiment, and FIG. 6 is a diagram comparing the signal transmittance. As is clear from the figure, in the circuit of the example, only signals near the target frequency are allowed to pass.
The SN ratio in the vicinity is improved. Therefore, compared to the original Δ-Σ modulation type AD converter, it is possible to handle signals with the same amount of information with fewer resources, and it also has essentially low distortion and good linearity, making it possible to implement it into an LSI. The converter can be obtained at low cost.

Note that the present invention is not limited to the above embodiments.

A tank circuit as shown in FIG. 7 can be used for BPF II, 1.2 of the embodiment. In the figure, the same parts as in FIG. 1 are given the same reference numerals. In the figure, the same parts as in FIG. 1 are given the same reference numerals. In the diagram, 4
1 indicates that the number of resonant frequencies to be used for BPFII is f. And Q-
The tank circuit 42 in (1) has a resonant frequency f like the tank circuit 41 to be used for the BPF 12. This is a Q-ω tank circuit. The disadvantage of using these tank circuits 41 and 42 is that it is difficult to realize a Q-■ tank circuit, and it is difficult to completely match the resonance frequencies f0 of the tank circuits 41 and 42. .

FIG. 8 is a circuit diagram of another embodiment. This practical example is an RF integrator that replaces the DC En range Δ-Σ modulation type AD converter circuit with multiple integrators connected in series.
FIG. 2 is a block diagram of a Δ-Σ modulation type AD converter. 50 is the RF integrator shown in FIG. In the figure, the same parts ζ as in FIG. 1 are given the same reference numerals. In this way, by replacing all the integrators used in the Δ-Σ modulation AD converter in the DC region with the RF integrator 50 shown in FIG. 2, many types of RF AD converters can be realized.

(Effects of the Invention) As described above in detail, the present invention provides an RF AD converter that has the characteristics of IF, low distortion rate, and wide dynamic range, is low cost, and has the least noise near the operating frequency. The second effect of "obtainable and practical" is great.

[Brief explanation of drawings]

Fig. 1 is a program diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of an RF integrator used in the BPF 12 of the circuit shown in Fig. 1, and Fig. 3 is an output waveform of the RF integrator shown in Fig. 2. Figure 4 is a circuit diagram of an RF integrator used in BPFII, Figure 5 is a comparison diagram of the S/N ratio between a conventional Δ-Σ modulation type AD converter and the device of the embodiment, and Figure 6 is a diagram of the conventional RF integrator. Comparison diagram of signal transmittance between the Δ-Σ modulation type AD converter and the device of the embodiment, FIG. 7 is a block diagram of another embodiment of the present invention, and FIG. 8 is a block diagram of another embodiment of the present invention Figure 9 is a block diagram of the Δ modulator, Figure 10 is an explanatory diagram of the Δ modulator, Figure 11 is a block diagram of the Δ-Σ modulator, and Figure 12 is the conventional Δ-Σ modulation type AD conversion. FIG. 1... Arithmetic unit 2... Comparator 3.4...
・Integrator 5...Decimation filter 11.12...BPF 21, 30...Input resistor 22...Operational amplifier 23.23a, 23b, 23c, 23cL,,
32° 32a, 32b, 32c, 32d-- Integrating capacitor 24.31... Rotary switch 50... RF integrator

Claims (2)

[Claims] (1) an arithmetic unit (1) that performs subtraction of an in-phase signal between a sampled input high-frequency analog signal and a signal immediately before the signal fed back in a steady state; A bandpass filter (11) that integrates and passes only the matched high-frequency signal.
and a comparator (11) that compares the output signal of the bandpass filter (11) with the zero potential and outputs a signal encoded by the positive/negative of the result.
2), the output encoded signal of the comparator (2) is integrated, and only the high-frequency analog signal that matches the center frequency is passed through and fed back, and the signal immediately before the sampled analog signal is sent to the arithmetic unit (1). A bandpass filter (12) providing a sampled signal of
An RF AD converter comprising: and a decimation filter (5) that converts the output signal of the comparator (2) into a binary series digital signal. (2) The bandpass filter (11) includes an input resistor (30) inserted between a signal input end and a signal output end, and an input resistor (30) inserted between a signal input end and a signal output end.
A plurality of integrating capacitors (32) inserted between the output terminal of the input analog signal and the ground, and a rotary switch ( The bandpass filter (12) consists of an input resistor (21) connected in series to the signal input terminal, and an operational amplifier (22) that amplifies and outputs the input analog signal.
), a plurality of integrating capacitors (23) inserted between the output end and the input end of the operational amplifier (22) and forming a feedback circuit of the operational amplifier (22), and the plurality of integrating capacitors (23). 2. The RF AD converter according to claim 1, further comprising a rotary switch (24) which is cyclically switched and connected in the same order one after another at the angular velocity of the center frequency of the input analog signal.