JPH0344350U - - Google Patents
Info
- Publication number
- JPH0344350U JPH0344350U JP1989102281U JP10228189U JPH0344350U JP H0344350 U JPH0344350 U JP H0344350U JP 1989102281 U JP1989102281 U JP 1989102281U JP 10228189 U JP10228189 U JP 10228189U JP H0344350 U JPH0344350 U JP H0344350U
- Authority
- JP
- Japan
- Prior art keywords
- storage mode
- display
- storage
- circuit
- rom
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Description
図は本考案の実施例を示すブロツク図である。
1……アツプダウン制御回路、2……記憶モー
ド制御回路、3……ROM、4……メモリ制御回
路、5……表示駆動回路、6……表示装置、7…
…メモリ。
The figure is a block diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Up-down control circuit, 2...Storage mode control circuit, 3...ROM, 4...Memory control circuit, 5...Display drive circuit, 6...Display device, 7...
…memory.
Claims (1)
ツチ操作によつて、チヤンネルのアツプ及びダウ
ンを制御するアツプダウン制御回路と、 該アツプダウン制御回路から出力されるチヤン
ネルを示すデータに基ずき、チヤンネル番号を表
示するための表示データを作成するROMと、 該ROMから出力される表示データに基ずき表
示装置のセグメントを駆動する表示駆動回路と、 を備えたトランシーバの表示回路において、 選択されたチヤンネルを記憶するための記憶手
段と、 所定のキー操作により前記記憶手段に選択され
たチヤンネルの記憶を可能とする記憶モード制御
手段と、 該記憶モード制御回路が記憶モードになつたこ
とを示す信号に基ずいて、記憶モードであること
を示す文字を表示するための表示データを作成す
る前記ROM内に設けられた領域と、 を備え、 前記記憶モード中はチヤンネル番号の表示に代
えて記憶モードであることを示す文字を表示する
ことを特徴とするトランシーバの表示回路。[Scope of Utility Model Registration Claim] Based on an up-down control circuit that controls up and down channels by operating a key switch to select reception and transmission channels, and data indicating the channel output from the up-down control circuit. A display circuit for a transceiver, comprising: a ROM that creates display data for displaying channel numbers; and a display drive circuit that drives segments of a display device based on display data output from the ROM. a storage means for storing the selected channel; a storage mode control means for enabling the storage of the selected channel in the storage means by a predetermined key operation; and the storage mode control circuit is placed in the storage mode. an area provided in the ROM for creating display data for displaying characters indicating the storage mode based on a signal indicating the storage mode; A display circuit for a transceiver, characterized in that the display circuit displays characters indicating that the transceiver is in storage mode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989102281U JPH0344350U (en) | 1989-08-31 | 1989-08-31 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989102281U JPH0344350U (en) | 1989-08-31 | 1989-08-31 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0344350U true JPH0344350U (en) | 1991-04-24 |
Family
ID=31651187
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1989102281U Pending JPH0344350U (en) | 1989-08-31 | 1989-08-31 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0344350U (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5046021A (en) * | 1973-08-27 | 1975-04-24 | ||
JPS52113117A (en) * | 1976-03-18 | 1977-09-22 | Torio Kk | Digital frequency indicator |
JPS56157116A (en) * | 1980-05-07 | 1981-12-04 | Clarion Co Ltd | Mode display mechanism capable of preset |
-
1989
- 1989-08-31 JP JP1989102281U patent/JPH0344350U/ja active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5046021A (en) * | 1973-08-27 | 1975-04-24 | ||
JPS52113117A (en) * | 1976-03-18 | 1977-09-22 | Torio Kk | Digital frequency indicator |
JPS56157116A (en) * | 1980-05-07 | 1981-12-04 | Clarion Co Ltd | Mode display mechanism capable of preset |
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