JPH0344344U

JPH0344344U -

Info

Publication number: JPH0344344U
Application number: JP10364289U
Authority: JP
Priority date: 1989-09-04
Filing date: 1989-09-04
Publication date: 1991-04-24

Description

[Brief explanation of drawings]

第１図は本考案装置の実施例による全体構成の
ブロツク図、第２図は本装置要部の第１実施例構
成を示すブロツク図、第３図は第１実施例構成に
おける各部の信号波形図、第４図は第２実施例構
成を示すブロツク図、第５図は第２実施例構成に
おける各部の信号波形図、第６図は第３実施例構
成を示すブロツク図、第７図は第３実施例構成に
おける各部の信号波形図、第８図は第４実施例構
成を示すブロツク図、第９図は第４実施例におけ
る各部の信号波形図、第１０図は本装置の第２局
部発振をスイープしたときの検波特性を説明する
ための図である。１１……第１ヘテロダイン検波部、１２……ア
ンテナ（導波部）、１３……第１局部発振器、１
５……第１中間周波アンプ、１６……第２ヘテロ
ダイン検波部、１７……第２局部発振器、１９…
…第２中間周波アンプ、２０……ロジツク部、２
１……ＰＬＬ同期検波部、２３……スイープ発振
器、３１……カウンタ（分周器）、３３……シフ
トレジスタ、３４……ＡＮＤ回路、３５……Ｔフ
リツプフロツプ、３６，３７……ＡＮＤ回路、３
８……反転回路、３９……ＯＲ回路、４３……シ
フトレジスタ、４４……ＡＮＤ回路、４５……シ
フトレジスタ、４６……シフトレジスタ、４７，
４８……Ｄフリツプフロツプ、４９……ＡＮＤ回
路、５０……反転回路、５１，５２……ＡＮＤ回
路、５３，５４……Ｄフリツプフロツプ、５５…
…ＡＮＤ回路。 Fig. 1 is a block diagram of the overall configuration according to an embodiment of the device of the present invention, Fig. 2 is a block diagram showing the configuration of the main part of the device in the first embodiment, and Fig. 3 is a signal waveform of each part in the configuration of the first embodiment. 4 is a block diagram showing the configuration of the second embodiment, FIG. 5 is a signal waveform diagram of each part in the configuration of the second embodiment, FIG. 6 is a block diagram showing the configuration of the third embodiment, and FIG. 7 is a block diagram showing the configuration of the third embodiment. FIG. 8 is a block diagram showing the configuration of the fourth embodiment. FIG. 9 is a signal waveform diagram of each component in the fourth embodiment. FIG. FIG. 3 is a diagram for explaining detection characteristics when sweeping local oscillation. 11...First heterodyne detection section, 12...Antenna (waveguide section), 13...First local oscillator, 1
5...First intermediate frequency amplifier, 16...Second heterodyne detection section, 17...Second local oscillator, 19...
...Second intermediate frequency amplifier, 20...Logic section, 2
1...PLL synchronous detection section, 23...Sweep oscillator, 31...Counter (frequency divider), 33...Shift register, 34...AND circuit, 35...T flip-flop, 36, 37...AND circuit, 3
8...Inversion circuit, 39...OR circuit, 43...Shift register, 44...AND circuit, 45...Shift register, 46...Shift register, 47,
48...D flip-flop, 49...AND circuit, 50...inverting circuit, 51, 52...AND circuit, 53, 54...D flip-flop, 55...
...AND circuit.

Claims

[Claims for Utility Model Registration] (1) A first device that obtains a first intermediate frequency from a received wave of a waveguide and an oscillated wave of a first local oscillator forming a PLL circuit.
a second heterodyne detection section that obtains a second intermediate frequency from the first intermediate frequency and an oscillation wave of a second local oscillator that sweeps the oscillation frequency; In a frequency band identification device in a superheterodyne receiver equipped with a PLL synchronous detection section that performs identification, a reset pulse for dividing the free-running oscillation frequency of the PLL circuit and sweeping the oscillation of the second local oscillator is provided. and a shift register which receives the detection output from the second heterodyne detection section and the reset pulse as input, and synthesizes the output of this shift register and the detection output to obtain 18
It includes a first logic circuit that obtains one of the detected signals with a 0° phase difference, and a flip-flop that operates with the reset pulse as input, and combines the signal and the output of the flip-flop to generate a signal for each cycle of the sweep. and a second logic circuit which obtains outputs alternately and separately from each other and supplies inverted and non-inverted signals of each output for each cycle to the PLL synchronous detection section. Frequency band identification device for aircraft. (2) A first circuit that obtains a first intermediate frequency from the received wave of the waveguide and the oscillation wave of the first local oscillator forming the PLL circuit.
a second heterodyne detection section that obtains a second intermediate frequency from the first intermediate frequency and an oscillation wave of a second local oscillator that sweeps the oscillation frequency; A frequency band identification device in a superheterodyne receiver equipped with a PLL synchronous detection section that performs identification, including a first shift register into which the detection output from the second heterodyne detection section is input, and the output of this shift register and the above-mentioned A first logic circuit that combines the detection outputs and obtains one of the detection signals having a phase difference of 180 degrees from each other obtained in one sweep, and a second shift register, and the signal obtained above and a second circuit which synthesizes the outputs of the shift registers to obtain separate outputs alternately for each period of the sweep, and supplies inverted and non-inverted signals of each output for each period to the PLL synchronous detection section; A frequency band identification device in a superheterodyne receiver, comprising a logic circuit. (3) A first circuit that obtains a first intermediate frequency from the received wave of the waveguide and the oscillation wave of the first local oscillator forming the PLL circuit.
a second heterodyne detection section that obtains a second intermediate frequency from the first intermediate frequency and an oscillation wave of a second local oscillator that sweeps the oscillation frequency; In a frequency band identification device in a superheterodyne receiver equipped with a PLL synchronous detection section that performs identification, from the detection output of the second heterodyne detection section,
The D flip-flop includes a first shift register that obtains a predetermined pulse, and a D flip-flop that operates with the predetermined pulse from the shift register as input.
a first logic circuit that combines the output of the flip-flop and the detection output to obtain one of the detection signals having a phase difference of 180° obtained in one sweep; and a second shift register; The signal obtained in 1 and the output of the shift register are combined to obtain separate outputs alternately for each period of the sweep, and the inverted and non-inverted signals of each output for each period are subjected to the PLL synchronous detection. 1. A frequency band identification device in a superheterodyne receiver, characterized in that the frequency band identification device comprises: (4) A first circuit that obtains a first intermediate frequency from the received wave of the waveguide and the oscillation wave of the first local oscillator forming the PLL circuit.
a second heterodyne detection section that obtains a second intermediate frequency from the first intermediate frequency and an oscillation wave of a second local oscillator that sweeps the oscillation frequency; In a frequency band identification device in a superheterodyne receiver equipped with a PLL synchronous detection section that performs identification, a detection output from a second heterodyne detection section and a PLL synchronous detection section are provided.
It includes a D flip-flop into which signals obtained by combining the inverted and non-inverted outputs of the free-running oscillation outputs of the LL circuit are respectively input, and the output of the D flip-flop and the signal obtained in one sweep are
It includes a first logic circuit that obtains one of the detected signals with a phase difference of 80 degrees, and a second shift register, and combines the signal obtained above and the output of the shift register to complete one cycle of the sweep. a second logic circuit that obtains outputs alternately and separately for each cycle, and supplies inverted and non-inverted signals of each output for each cycle to the PLL synchronous detection section. Frequency band identification device in the receiver.