JPH0342913A - Code converting method - Google Patents

Abstract

PURPOSE:To enable digital-LSI-implementation with a simple circuit by expanding the pulse width of an input RZ signal and increasing a timing margin, differentiating the bits of the input signal after asynchronous integration with an optional clock width signal of the same frequency, and thus obtaining a desired NRZ signal. CONSTITUTION:A latch circuit 2 is constituted of the combinational feedback circuit of NANDs 3 and 4 and stored with an input set signal (3) and a reset signal (2) after two-wire separation temporarily to send out a positive output (4) and a complementary output (5). The signals (4) and (5) which are integrated asynchronously with a reception side are separated by two wires while the 'H'' part of the RZ input signal (1) is expanded, and then inputted to a bit differentiation part 7. The bit differentiation part 7 reads the set signal (5) and reset signal (4) in with the clock signal (10) of the reception side, NORs the read set signal (7) and reset signal (6), and sends the output NRZ signal (5) out. The NRZ signal (t) is synchronized with one cycle of the clock signal (10), so data '1' and '0' are transferred into a device as a '1' and a '0' signal respectively.

Description

[Detailed Description of the Invention] [Summary] Regarding a code conversion method in a transmission line interface of a receiving device for a digital data transmission line, the purpose of the present invention is to create a circuit configuration suitable for LSI implementation, and an RZ with a pulse occupancy rate of about 50% is used. Pulse signal occupancy rate 100
% NRZ signal at the receiving side interface of the digital data transmission line, a two-line separation circuit that separates the input RZ signal into a set signal and a reset signal, and a latch that extends the two-line separated set signal and reset signal. The circuit consists of an asynchronous integrator circuit, and a bit differentiator circuit that bit-differentiates the expanded latch signal with the incoming station clock signal and outputs an NRZ signal, and expands the pulse width of the input RZ signal to increase the retiming margin. is increased, and the asynchronously integrated input signal is bit-differentiated by an arbitrary clock width signal of the same frequency to obtain a desired NRZ signal.

[Industrial application field]

The present invention relates to a code conversion method in a transmission line interface of a receiving device for a digital data transmission line.

FIG. 4 shows a connection configuration diagram of the digital data transmission device. In the figure, IO is a transmitting side device, 20 is a receiving side device,
30 is a digital data transmission path, 11 is a transmission path interface on the sending side, 12 is a transfer path within the sending device, 13 is the transmitting device, 21 is a transmission path interface on the receiving side, 22 is a transfer path within the receiving device, and 23 is a transfer path within the receiving device. A receiving device is shown.

Transmission and reception between the transmitting device IO and the receiving device 20 is controlled by asynchronous clock signals, although they have the same frequency. Transfer path 12 within the transmitting device and transfer path 22 within the receiving device
The signal used in NRZ (NonReturn
o Zero) signal, that is, a bit signal with a pulse occupancy rate of 100%, data "1" is represented by a signal "1", and data "O" is represented by a signal "0".

However, the digital data transmission path 30 performs tying extraction and BSI (Bit 5 sequence index).
RZ (Return
to Zero) signal, that is, a bit signal with a pulse occupancy rate of approximately 50%, and data "1" is a bit signal "
1.0", the data "0" is the bit signal "0. O"
It is expressed by

At the transmission line interface 11 on the transmitting side, an AND signal of the clock signal on the transmitting side and the NRZ signal from the transmitting device 13 is sent to the digital data transmission line 30 as an RZ signal. The transmission line interface 21 on the receiving side retimes the signal using the clock signal on the receiving side, converts it again into an NRZ signal, and performs logical processing in the receiving device 23.

However, since the RZ signal flowing through the digital data transmission path 30 has a pulse occupancy rate of about 50%, that is, less than 100%,
In order to retiming this on the receiving side, the retiming margin is smaller than that of an NRZ signal with a pulse occupancy rate of 100%, and a circuit for extracting and generating the optimal clock is required in the transmission line interface 21 on the receiving side. .

[Conventional technology]

FIG. 5 shows a block diagram of a conventional transmission line interface on the receiving side. In the figure, 24 is a retiming section;
Reference numeral 25 indicates a transmission line clock extraction section, and reference numeral 26 indicates a pit buffer section.

The retiming section 24 consists of a flip-flop circuit,
It receives the RZ signal from the transmission path, places a buffer in response to the transmission path signal, and also performs a retie.

The transmission line clock extraction unit 25 is a circuit that extracts and generates a transmitting side clock signal from the change point of the RZ signal from the transmission line, and is suitable for analog tank circuits with L and C parallel elements, digital PLLs, etc. A large circuit resonates with the transmitter clock signal and detects the transmitter's oscillation pulse. The pit buffer unit 26 extracts every other oscillation pulse and reads the RZ signal, thereby transmitting the NRZ signal.

[Problems to be Solved by the Invention] In the conventional receiving side interface, in order to retiming the RZ signal from the transmission line, an analog tank circuit, a digital PLL circuit, etc. are used to extract and generate the clock signal of the inset. A transmission line clock extraction section with a large configuration was required. For this reason, it was not suitable for system-on-chip, ie, LSI, such as gate arrays.

In the present invention, without using a clock extraction circuit using an analog circuit or a digital PLL circuit with a large circuit scale,
It is an object of the present invention to provide a receiving side interface circuit that can retime an RZ signal and convert it into an NRZ signal.

[Means to solve the problem]

FIG. 1 shows the principle configuration diagram of the present invention. In the figure, 1 is a two-line separation circuit that separates the input RZ signal into a set signal and a reset signal, 2 is a latch circuit that stretches the two-line separated set signal and reset signal, and 3 is a latch circuit that stretches the stretched reset signal. A differentiating circuit, 4 a differentiating circuit for the expanded set signal, and 5 an OR circuit for outputting an NRZ signal by ORing the differentiated signals of the set signal and the reset signal. The two-line separation circuit 1 and the latch circuit 2 constitute an asynchronous integration section 6, and the differentiating circuits 3 and 4 and the OR circuit 5 constitute a bit differentiating section 7.

Input RZ with pulse occupancy rate of approximately 50% by 2-wire separation circuit 1
The signal is separated into two lines, a set signal and a reset signal, and the latch circuit 2 extends the pulse width of the separated set signal and reset signal to increase the retiming margin, and the signal is received by the asynchronous integration section 6. The desired pulse occupancy rate of 100% is obtained by bit-differentiating the input signal, which is asynchronous with the transmitting side clock signal and integrated by the transmitting side clock signal, by an arbitrary receiving side clock signal which is asynchronous and has the same frequency as the transmitting side in the bit differentiator 7. NRZ signals can be obtained.

[Effect]

A tying chart of the present invention is shown in FIG.

In the figure, ■ is the input RZ signal from the transmission line, ■ is the set signal separated by two lines, ■ is the reset signal separated by two lines, ■ is the latch signal of the set signal, ■ is the latch signal of the reset signal, and ■ is the differential signal of the latched set signal,
(2) indicates a differential signal of the latched reset signal, (2) indicates an NRZ signal sent from the OR circuit, (2) indicates a clock signal on the transmitting side, and [phase] indicates a clock signal on the receiving side.

Clock signal on the sending side and clock signal on the receiving side [phase]
have the same frequency but are asynchronous. The input RZ signal is synchronized with the transmitter clock signal ■, data "1" is represented by a bit signal "1.0", and data "0" is represented by a bit signal "0.0".Output NRZ signal is synchronized with the period of the clock signal [phase] on the receiving side, and the data “l” is synchronized with the period of the clock signal [phase] on the receiving side, and the data “l”
Data “0” is represented by a signal “0”.

When data "01100101" is inputted from all the transmission lines by the RZ signal, the "H" signal synchronized with the clock ■ on the transmitting side is separated into two lines, separated into a set signal ■ and a reset signal ■, and sent to the latch circuit. 2, the "L" portion of the set signal (2) is expanded to become the (2) signal, and the "L" portion of the reset signal (2) is expanded to become the (2) signal. “H” of the above integrated set signal ■ and reset signal ■
The "H" part of the input RZ signal ■ is stretched and separated, so by reading each separated signal with the clock signal [phase] on the receiving side, the differential signals ■ and ■ are obtained. By ORing the set signal (2) and the reset signal (2) read by the differentiating circuit in the OR circuit 5, data (2) based on the NRZ signal can be sent out.

Set signal integrated with the above transmitting side clock signal■
and the reset signal ■ are sufficiently large compared to the period of the asynchronous clock signal [stock], so it is certain that the clock signal [stock]
It can be read with [phase].

〔Example〕 A circuit configuration diagram of an embodiment of the present invention is shown in FIG.

In the figure, l is a two-line separation circuit, 2 is a latch circuit, and 3.
4 is a differentiation circuit, 5 is an OR circuit, 6 is an asynchronous integration section, and No. 7 is a j-bit differentiation section.

The two-line separation circuit l includes INVI, FF1. NANDl,NA
The input RZ multiplied signal is inverted by INVI and inserted into FFI, and the set signal ■ and reset signal @ are sent out.
Take the NAND of the Z input signal and get the two-wire separation signal ■ and ■
and are inserted into the latch circuit 2. Latch circuit 2 is NAND
3. It consists of a NAND4 combination feedback circuit, temporarily stores the input set signal (2) and reset signal (2) separated by two lines, and sends out a positive output (2) and a supplementary output (3). The signals ■ and ■ that are integrated asynchronously with the receiving side are the “” of the RZ input signal ■.
The H'' portion is separated into two lines in an expanded form and inserted into the bit differentiation section 7.

The bit differentiator 7 is FF2. FF3. A reset signal differentiator 3 consisting of an ANN13, and an FF4. FF5. ^ND
It consists of a set signal differentiator 4 consisting of 2 and an OR circuit 5 consisting of an ORI. Take the NOR of ■ and send out the output NRZ signal ■. Since the NRZ signal (2) is synchronized with one cycle of the clock signal [phase], data "1#" can be transferred into the device as a "1" signal and data "0" as a "0" signal.

〔Effect of the invention〕

According to the code conversion method of the present invention, an RZ signal can be retimed and converted into an NRZ signal without using a clock extraction circuit using an analog circuit or a large-scale digital PLL as in the past, and furthermore, a pit buffer can be used. Because it can be transferred to the clock in the receiving station without the need for
It becomes possible to create a digital LSI (gate array).

[Brief explanation of drawings]

Fig. 1 is a diagram of the principle configuration of the present invention, Fig. 2 is a tie chart of the invention, Fig. 3 is a circuit configuration diagram of an embodiment, Fig. 4 is a connection configuration diagram of a digital data transmission device, and Fig. 5 shows a block configuration diagram of a conventional example. In the figure, ■ is a two-wire separation circuit, 2 is a latch circuit, and 3.
4 is a differentiation circuit, 5 is an OR circuit, 6 is an asynchronous integration section, 7
is a pit differentiator, 10 is a transmitting side device, 11 is a transmitting side transmission line interface, 12 is a transfer path within the transmitting side device, 13 is a transmitting device, 20 is a receiving side device, 21 is a receiving side transmission line interface, and 22 is a receiving side. 23 is a receiving device, 24 is a retiming section, 25 is a transmission line clock extracting section, and 26 is a pit buffer section. Note that ■ to @ indicate the type of signal.

Claims (1)

[Claims] An RZ signal with a pulse occupancy rate of approximately 50% is converted to a pulse occupancy rate of 100%.
% of the digital data transmission line receiving side interface, which separates the input RZ signal into a set signal and a reset signal, and a two-line separation circuit (1) that separates the input RZ signal into a set signal and a reset signal. an asynchronous integrator (6) consisting of a latch circuit (2) that stretches the latched signal; and a bit differentiator (7) that bit-differentiates the stretched latch signal according to the incoming station clock signal and outputs an NRZ signal. A code characterized in that a desired NRZ signal is obtained by extending the pulse width of the RZ signal to increase the retiming margin and bit-differentiating the asynchronously integrated input signal with an arbitrary clock width signal of the same frequency. Conversion method.