JPH0341303U - - Google Patents
Info
- Publication number
- JPH0341303U JPH0341303U JP10002289U JP10002289U JPH0341303U JP H0341303 U JPH0341303 U JP H0341303U JP 10002289 U JP10002289 U JP 10002289U JP 10002289 U JP10002289 U JP 10002289U JP H0341303 U JPH0341303 U JP H0341303U
- Authority
- JP
- Japan
- Prior art keywords
- mode
- switch
- input
- processing means
- arithmetic processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007935 neutral effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 1
Landscapes
- Safety Devices In Control Systems (AREA)
- Programmable Controllers (AREA)
Description
第１図は本考案一実施例の要部回路図、第２図
は同上の動作説明図、第３図は本発明に係るプロ
グラマブルコントローラの概略構成図、第４図は
従来例の要部回路図、第５図は同上のモードスイ
ツチの正面図、第６図は同上の動作説明図である
。
１……ＣＰＵ、２……システムＲＯＭ、３……
ＲＡＭ、４……入出力用インターフエース、５…
…ＬＥＤ表示部、６……モードスイツチ、７……
Ｉ／Ｏポート、８……通信用ポート、９……周辺
機器である。
Fig. 1 is a circuit diagram of a main part of an embodiment of the present invention, Fig. 2 is an explanatory diagram of the same operation as above, Fig. 3 is a schematic configuration diagram of a programmable controller according to the invention, and Fig. 4 is a main part circuit of a conventional example. 5 is a front view of the mode switch same as the above, and FIG. 6 is an explanatory diagram of the operation same as the above. 1...CPU, 2...System ROM, 3...
RAM, 4...Input/output interface, 5...
...LED display section, 6...Mode switch, 7...
I/O port, 8... communication port, 9... peripheral device.
Claims (1)
ーケンス制御する演算処理手段を具備し、上記演
算処理手段のＲＡＭのイニシヤライズモードと、
ＲＵＮモードと、テストモードとを、片側を跳ね
返りスイツチ機構にするとともに他側をトグルス
イツチ機構にした３ポジシヨンのモードスイツチ
にて切り替え自在とし、上記モードスイツチの跳
ね返りスイツチ側をイニシヤライズモード、ニユ
ートラル位置をＲＵＮモード、トグルスイツチ側
をテストモードとしたプログラマブルコントロー
ラにおいて、モードスイツチのテストモードのス
イツチ入力がオフされたときから一定時間の間、
イニシヤライズモードのスイツチ入力が演算処理
手段に入力されるのを禁止する入力禁止回路をス
イツチ入力回路に設けたことを特徴とするプログ
ラマブルコントローラ。 comprising an arithmetic processing means for sequentially controlling the load based on a preset program, an initialization mode of the RAM of the arithmetic processing means;
The RUN mode and the test mode can be switched freely using a 3-position mode switch with a bounce switch mechanism on one side and a toggle switch mechanism on the other side, and the bounce switch side of the mode switch can be switched between the initialize mode and neutral. In a programmable controller whose position is RUN mode and toggle switch side is set to test mode, for a certain period of time from when the test mode switch input of the mode switch is turned off,
A programmable controller characterized in that a switch input circuit is provided with an input prohibition circuit that prohibits input of an initialization mode switch input to an arithmetic processing means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10002289U JPH0341303U (en) | 1989-08-28 | 1989-08-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10002289U JPH0341303U (en) | 1989-08-28 | 1989-08-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0341303U true JPH0341303U (en) | 1991-04-19 |
Family
ID=31649047
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10002289U Pending JPH0341303U (en) | 1989-08-28 | 1989-08-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0341303U (en) |
-
1989
- 1989-08-28 JP JP10002289U patent/JPH0341303U/ja active Pending