JPH0339843U - - Google Patents

Info

Publication number
JPH0339843U
JPH0339843U JP23790U JP23790U JPH0339843U JP H0339843 U JPH0339843 U JP H0339843U JP 23790 U JP23790 U JP 23790U JP 23790 U JP23790 U JP 23790U JP H0339843 U JPH0339843 U JP H0339843U
Authority
JP
Japan
Prior art keywords
periphery
plan
view
semiconductor
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23790U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP23790U priority Critical patent/JPH0339843U/ja
Publication of JPH0339843U publication Critical patent/JPH0339843U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP23790U 1989-01-10 1990-01-06 Pending JPH0339843U (en18)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23790U JPH0339843U (en18) 1989-01-10 1990-01-06

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP89589 1989-01-10
JP23790U JPH0339843U (en18) 1989-01-10 1990-01-06

Publications (1)

Publication Number Publication Date
JPH0339843U true JPH0339843U (en18) 1991-04-17

Family

ID=31716960

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23790U Pending JPH0339843U (en18) 1989-01-10 1990-01-06

Country Status (1)

Country Link
JP (1) JPH0339843U (en18)

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