JPH0332135A - Cell exchanging device - Google Patents

Abstract

PURPOSE:To prevent the blocking of a cell to other output port by providing an input stage cell exchange switching module and an output stage cell exchange switching module. CONSTITUTION:Cells reaching all input ports 2 is divided into plural groups and after the cells are once subjected to time division multiplex by an input stage cell multiplexing circuit 7 of input stage cell exchange switching modules 60-63, a cell selection circuit 8 shares the cells to an output port 5. Output stage cell exchange switching modules 70-73 write the cells to a storage circuit 10 and a storage control circuit 11 reads the stored cells according to a prescribed output rule and a cell multiplexing circuit 12 applies multiplex to the cells again and a cell selection circuit 13 shares the cells to each output port 5. Thus, even when the cells are concentrated to one output port, the switching is attained without giving effect on the cells of other output ports.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a cell switching device for exchanging various information such as voice, data, and images divided into blocks called cells at high speed. It is.

[Conventional technology]

A switching network called a Banyan network has been known as an example of a system for high-speed switching by directly referencing cell header information using hardware.

Figure 5 shows, for example, the Design of Unintegrated Services Packet Network (Design of Unintegrated Services Packet Network).
an integrated 5 services
PacketNetwork), IEEE Journal on Selected Areas Inco.
ected Areas inCom+*untcat
ions), Vof, 5AC-4+ pp, 13
73-i3so.

An example of the Banyan network shown in November 1986, in which la, 1. b is an input cell, 2 is an input port, 3 is a switching device consisting of a plurality of 2×2 unit switches 4, and 5 is an output port.

Note that in the above literature, the name "packet" is used instead of the name "cell," but both cells and packets express the same thing in that multimedia information is divided into blocks and a header containing destination information is added. are doing. However, in general, the length of one block of a packet is treated as variable, but the difference is that in a cell, the length of a block is treated as a fixed length according to international standards. ATM (Asynchronous
(us TransferMode) communication, the term cell is used, so the term cell will be used instead of packet in the following description of the conventional example.

Next, the operation will be explained. In Figure 5, a plurality of 2
The cell switching device 3 consisting of the ×2 unit switch 4 is configured to select an output port using the corresponding bit of the header bit string of each input cell 1 (la, lb collectively). The unit switches 4 lined up in a row are
If the first bit of the header section is O'', unit switch 4
Connect the human power port to the upper output port) 5a, and set it to “1”.
If so, connect it to the lower output port 15b. Similarly, the unit switches 4 arranged in the second column on the left side are connected to the output ports 5c and 5d according to the second bit of the header part of the input cell l.
A fifth unit switch 4 is arranged in a row to make a selection.
When interconnecting the wires as shown in the figure, by expressing the number of the output port 5 of the desired final stage in binary and adding it to the header of cell 1, no matter which input port 2 inputs cell 1, The desired output port 5 is reached.

[Problem to be solved by the invention]

Since the conventional cell switching device is configured as described above, there is a problem in that blocking (collision) occurs when cells la and cell ib aiming at the same output port 5 are input to the input port 2 at the same time. In order to deal with this issue, there is a system in which a buffer memory is provided in the input section or inside the unit switch 4, but when cells are concentrated on a certain output port, the buffer memory becomes full and cells are transferred to other output ports. There was also the issue of being blocked.

This invention was made to solve the above problems, and allows switching without causing blocking and even if cells are concentrated on one output port, without affecting cells going to other output ports. The purpose is to obtain a cell switching device.

[Means to solve the problem]

The cell switching device according to the present invention includes an input stage cell multiplexing circuit that divides input ports into which a plurality of cells are input into a plurality of groups, and time-division multiplexes each input cell for each group; an input stage cell exchange switch module having an input stage cell selection circuit that selects and passes cells destined for a specific output port group out of a plurality of output ports divided into a plurality of groups from an output signal of a multiplexing circuit; A storage circuit that writes each cell destined for a specific output port group outputted from the cell selection circuit of the above, and manages and stores the addresses of the cells stored in each of the output stage storage circuits for each destination, and stores them according to predetermined output rules. A storage control circuit that reads out the cells stored in the circuit, an output stage cell multiplexing circuit that multiplexes the cells read out from each output stage storage circuit, and a specific output port group from the output stage cell multiplexed signal. or one or more output stage cell exchange switch modules having an output stage cell selection circuit that selects and passes cells destined for a particular output port, and a speed that converts the speed of the time division multiplexed cells to the speed of the output port. and a cell output stage module having a conversion circuit.

[For production]

The cell switching device in this invention divides the cells that have arrived at the full power port into a plurality of groups, once multiplexes the cells by the input stage cell multiplexing circuit of the input stage cell exchange switch module within the group, and then selects the cells. It is distributed to the output port by the address filter by the circuit. One or more output stage cell exchange switch modules that receive this output write the cells into a storage circuit, and under the storage control circuit, the cell multiplexing circuit rewrites the cells in groups of output ports divided into a plurality of groups. After cells are multiplexed, a final address filter by a cell selection circuit distributes them to each output port, thereby reducing the probability that cells will be discarded.

〔Example〕

An embodiment according to the present invention will be described below with reference to the drawings.

FIG. 1 is an overall circuit diagram showing the cell switching device 3. As shown in FIG. This cell switching device 3 has an input port 2 that inputs a plurality of cells.
are divided into a plurality of groups, and for each group, input stage cell exchange switch modules 60 to 63 exchange each input cell, and exchange cells destined for a specific output port group sent from the previous stage cell exchange switch module. Processing output stage cell exchange switch module 70~
73, and the final stage cell output stage module 80~
It has 83.

The input stage cell exchange switch modules 60 to 63, for example, the input stage cell exchange switch module 60, include an input stage cell multiplexing circuit 7 that time-division multiplexes cells, and a plurality of output signals from the input stage cell multiplexing circuit 7. The input stage cell selection circuits 88 to 8d select cells destined for a specific output port group out of the output ports divided into a plurality of groups using an address filter, and allow the assigned cells to pass through.

In addition, output stage cell exchange switch modules 70 to 73,
For example, the output stage cell exchange switch module 70
As shown in the figure, header processing circuits 9a to 9d read and analyze the destination of cells destined for a specific output port group output from the cell selection circuit in the previous stage, and output the cells output from the header processing circuits 9a to 9d. , by specifying a write address, it is possible to store at that address,
In addition, there are memory circuits 10a to 10d that can read the stored cells regardless of the writing order when a read address is specified, and a header processing circuit that is located in the memory control circuit ll and reads the address of the cell written by the memory circuit. 9a
- 9d, an address exchange circuit 16 that allocates each output port group (hereinafter referred to as an outgoing line), and an outgoing line corresponding address FIFO 17a to 17d that allows the allocated addresses to be written in each outgoing line and on a first-come, first-served basis.
A read right granting circuit 18 provides a read address to the memory circuits 10a to 10d in a timely manner and permits reading, and a memory circuit that manages and holds the read address as a free address when a cell is read from the memory circuits 10a to 10d. Free address management circuits 19a to 19d that provide a write address when a new cell arrives at 10a to 10d, and memory circuits 10a to 10a.
An output stage cell multiplexing circuit 12 multiplexes the cells read from 0d, and an address filter selects the cells destined for a specific group among the specific output port groups out of this output signal, and the assigned cells are passed through. output stage cell selection circuits 13a to 13d. Further, in FIG. 1, cell output stage modules 80 to 83, for example cell output stage module 80, include speed conversion circuits 14a to 14d that convert the speed of time-division multiplexed cells to the speed of the output port.

Next, the operation will be explained. In FIG. 1, the cells have a fixed length, and the arrival of cells is random, but at the input port (2). It is assumed that the cell input phase is adjusted before being input to ~I+s, and that the cell inputs from all input ports 2 are supplied with the same cell phase.

First, the operation of the input stage (first stage) cell exchange switch modules 60 to 63 will be explained based on FIG. 3 using the input stage cell exchange switch module 60 as an example. input signal a
%d are time-divided by a cell multiplexing circuit 7 and multiplexed into a signal e shown in FIG. This signal e
In this case, the input stage cell selection circuits 8a to 8d corresponding to each of the output ports of the input stage cell exchange switch module 60 detect the first address given to the header part of the cell, and apply the first address to the signals f and p, for example. As shown, cells destined for a predetermined output port are selected and output. FIG. 3 shows how a cell whose first address is "l" is outputted as a signal r, and a cell whose first address is "2" is outputted as a signal P. Here, multiplexing is
The signals are multiplexed at a speed that is twice the link speed of the input port as the number of ports, and are multiplexed into synchronized time slots on a cell-by-cell basis, as shown in FIG. 3, for example. A time slot without an input cell is assigned as an empty slot so that the first address of the header does not correspond to any output port.

As described above, the input stage cell exchange switch module 60
63, the cells input at the link speed are switched according to the first address in the header section, and are sent out in bursts to the output port of the first stage at the multiplexed speed.

Next, the second stage output stage cell exchange switch module 7
The operations of 0 to 73 will be explained by taking the output stage cell exchange switch module 70 as an example. In FIG. 2, among the outputs of the input stage cell exchange switch modules 60 to 63, four signals inputted to the input stage cell exchange switch module 70 are respectively denoted by fr g+h*t.

The signal f y i is one in which cells are sent out in bursts on a signal line at a multiplexed speed, and the number of cells on the four signals varies. Therefore, these signals are supplied to the memory circuits 10a to 10d provided for each input port in the output stage cell exchange switch module 70, and after buffering them, the output is sent to the output stage cell multiplexing circuit 12. Perform multiplexing. If the arrival of input cells is uniform both in time and space, the output stage cell multiplexing circuit 1
On the condition that the speed of the output signal j of No. 2 is at least twice the input link speed of the output stage cell exchange switch module 70 as the number of ports, the cells input to the output stage cell exchange switch module 70 can be multiplexed without being discarded. It is thought that it can be converted into However, since the actual arrival of cells varies both temporally and spatially, the storage circuits 10a to 10d
It is necessary to buffer the cells once to absorb cell fluctuations.

The storage control circuit 11 has a function of not only reading cells addressed to the same outgoing line when reading cells, but also preventing the order of cells from being reversed.

Specifically, in order to manage and store the addresses of the memory circuits 10a-10d on the outgoing line side when cells are stored in the memory circuits 10a-10d, the addresses are first distributed to the outgoing line side by the address exchange circuit 16. , then the outgoing line corresponding address F
The data is stored in the IFOs 17a to 17d. The read right granting circuit 18 refers to the outputs of the outgoing line corresponding address FIFOs 17a to 17d, and selects all the storage circuits 10a to 10d within the range where the subsequent output stage cell multiplexing circuit 12 can multiplex the outputs of all the storage circuits 10a to 10d. Give a read address to send the cell. Various methods can be considered for controlling reading of the memory circuits 10a to 10d. For example, N cells (N is an integer greater than or equal to 2) are read out consecutively for the outgoing lines for which the remaining storage capacity of the outgoing line corresponding address FIFOs 17a to 17d is above a certain value, and for the other outgoing lines, A method that reads n cells (n is 1 or 0) consecutively and multiplexes them, or compares the amount of cells destined for each outgoing line and reads N cells for the outgoing line with the highest remaining capacity. A possible method is to read n cells continuously and for other outgoing lines, read out n cells and multiplex it, but either method will not work for outgoing lines with many cells. In this case, more cells will be read out than from an outgoing line with fewer cells. At this time, it is necessary to avoid a method in which reading is stopped for outgoing lines with fewer cells as destinations and the delay time increases beyond a certain value. In addition, in the output stage cell exchange switch module 70 at the final stage, it is necessary to perform speed conversion at the subsequent stage of the output line, and in order to avoid blurring here, reading from each memory circuit 10a to 10d must be performed uniformly. be. Therefore, the read right granting circuit 18 of the output stage cell exchange switch module 70 at the final stage reads cells addressed to each outgoing line in the order of the outgoing lines (control is performed).

Here, as an example, an intermediate stage output stage cell exchange switch module 70 which is not the final stage, that is, there is an output stage cell exchange switch module also at a subsequent stage, will be described. In addition, as a method, if the remaining amount of cells for each destination outgoing line exceeds 4 cells (equivalent to the number of input ports), 2 cells are read out consecutively, and if there are 4 cells or less, 1 or 0 cells are read out. Thinking about a method to read out and multiplex cells,
This will be explained along the timing diagrams of FIGS. 3 and 4.

Assume that a cell string as shown in FIG. 4 is input as a signal fwi. The signal g is transmitted from the input stage cell exchange switch module 61 to the output line of nine consecutive cells, 1. m
, n. For the outgoing line, for each of l, m, and n, the outgoing line corresponding address F
IFO corresponds to 17a, 17b, 17c, and 17d. The read right granting circuit 18 monitors the remaining cell storage capacity in each of the outgoing line corresponding address FIFOs 17a to 17d, and first, the outgoing line corresponding address FIFOs 17a to 1
When the address storing the first cell is stored in 7d, the read gate of the outgoing line corresponding address FIFO 17a addressed to k is opened to manually input the address. Then, one cell corresponding to this address is outputted from the memory circuit 10a to the output stage cell multiplexing circuit 12 to start multiplexing.

Multiplexing is performed by the outgoing line corresponding address FIFO 17a.

17b, 17c, and 17d are performed cell by cell in this order, and if there are no stored cells, the next FIFO is immediately read and multiplexing is started.

The first cell is the cell addressed to the outgoing line, and is the first cell of the signal f (hereinafter, the cell will be called, for example, the F1 cell using the number Fl of the data part of the cell, etc.). , an address is taken out from the outgoing line corresponding address FIFO 17a, and this address is used as a read address in the storage circuit 10a.
The cells are read out and multiplexed by applying At the same time, the read address is added to the empty address management FIFO 191a. Once this cell has been multiplexed,
Next, an address is taken out from the outgoing line corresponding address FIFO 17b addressed to outgoing line i, and the G2 cell is multiplexed. Next, it is the turn of the outgoing line corresponding address FIFO 17c for the outgoing line m, but since it is empty, it immediately becomes the turn for the outgoing line n, and the address is taken out from the outgoing line corresponding address FIFO 17d, and the G
3 cells are multiplexed. Next, it's the turn to address vAk, so
Gl cells are multiplexed. Next, it is the turn of outgoing line l, so 1
One cell is multiplexed. Next, 66 cells are multiplexed on the outgoing line m, and 67 cells are similarly multiplexed on the outgoing line n. Next, it is the turn of the outgoing line, and the outgoing line corresponding address FIFO1
Since the remaining capacity of 7a is 5 (indicated by a circle in FIG. 4), two pieces are read out consecutively, and H1 and G4 are multiplexed. Below, H2, H3°G5. C;9. F3. H5, F2. H4
, 12, G8 F4. Multiplexed in GIO order.

As described above, the output stage cell exchange switch module 70
The outgoing line corresponding address FIFOs 17a to 17b enable address management of the memory circuits 10a to 10d, and it becomes possible to temporarily store M cells. In general, the total sum of cells supplied from the signal lines to the output stage cell exchange switch modules 70 to 71 corresponds, on average, to the input link speed times the number of input ports, provided there is no temporal or spatial bias. , output stage cell exchange switch modules 70 to 73
The total number of cells that can be multiplexed on the multiplexed signal is considered to be about the same or smaller than the total number of cells that can be multiplexed on the multiplexed signal. Increases and decreases in the remaining cell storage capacity of the memory circuits 10a to 10d occur because the number of arriving cells temporally and spatially fluctuates from the average. This absorbs temporal fluctuations and reduces cell waste.

Furthermore, the memory circuits 10a to 10d of the output stage cell exchange switch modules 70 to 73 write at a multiplexed high speed even when a plurality of cells arrive at the same time.
Since the cells can be read at the outgoing link speed, they will not be discarded even if the number of cells within the capacity of the memory circuits 10a to 10d are concentrated at the same time.

In the above embodiment, the number of input ports and the number of output ports of the entire cell exchange switch are the same, but they may be different. In addition, output stage cell exchange switch modules 70 to 73
The number of stages may also be expanded by sequentially connecting multiple stages. In addition, in the above embodiment, the number of input and output ports of the entire cell exchange switch is 16, and this is divided into 4 x 4 cell exchange module modules, but other values may be used. Alternatively, it may be configured as a single cell exchange switch without being divided into such modules.

In addition, for the address in the cell header section, an example is shown in which the outgoing line number is assigned to two address sections in correspondence with a two-stage cell exchange switch module, but a coded number may be assigned to one address section. Some kind of conversion processing may be performed.

Furthermore, in the above embodiment, a case has been described in which one cell is outputted to only one output port, but depending on how the address is specified, the output stage cell selection circuits 13a to 13a may output to multiple output ports. 13h can be set, and a broadcasting function may be added.

Alternatively, the header section and the data section may be separated structurally, circuits with different speeds may be used, and the header section and the data section may be respectively assigned to a plurality of signal lines arranged in parallel.

Next, in the above embodiment, the link speeds of the input ports are the same, but the output stage storage circuits 10a to 10 shown in FIG.
Traffic concentration is possible by making the read speed from d faster than the link speed of the input port, and conversely, it is also possible to make the link speed of the input port faster than the speed of the output port. Although the multiplexing speed of signal j is assumed to be the same as the multiplexing speed of signal e, by increasing the multiplexing speed of signal j, it is possible to reduce cell discard between output stage cell exchange switch module stages. The rate can be made even lower.

Next, in the above embodiment, one outgoing line corresponding address FIFO 17a to 17d is provided for each outgoing line of the output stage cell exchange switch module 70, but a plurality of PIFOs are provided for each outgoing line according to priority. It is also possible to multiplex cells with higher priority first based on an r code indicating the priority added to the header of the cell in addition to the address. Further, in the read right granting circuit 18, an example has been shown in which when more than four addresses are accumulated in the outgoing line corresponding address FIFOs 17a to 17d, two consecutive addresses are read out, but other numerical values may be used. Any other method may be used as long as it gives priority to reading out FIFOs with a large amount of remaining storage.

In addition, if operating speed restrictions are required, serial/parallel conversion circuits are installed before and after this switch.

A parallel/serial conversion circuit may be added to process the signals as parallel signals.

〔Effect of the invention〕

As described above, according to the present invention, the cell switching device multiplexes input cells in the input stage cell switching switch module and then distributes them, and the output stage cell switching module transfers the cell string input from the previous stage to the storage circuit. The memory control circuit reads out the cells in the memory circuit according to a predetermined output rule, so even if cells are concentrated in a specific output port group at the same time, it will still be within the capacity of the output stage memory circuit. If so, the effect is that cells are not discarded.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a cell switching device according to an embodiment of the present invention, FIG. 2 is an enlarged block diagram of the output stage cell switching switch module in FIG. 1, and FIG. 3 is an enlarged block diagram of the input stage cell switching module in FIG. 1. FIG. 4 is a timing diagram showing the signal timing of each part of the switch module. FIG. 4 is a timing diagram showing the signal timing of each part of the intermediate stage output stage cell exchange switch module in FIG. 2. FIG. 5 is a conceptual diagram showing the conventional cell switching device. It is a diagram. 2 is a human power port, 3 is a cell switching device, 5 is an output port,
7 is an input stage cell multiplexing circuit, 8a to 8h is an input stage cell selection circuit, 9a to 9h is a header processing circuit, 10a to 10h
11 is a storage circuit, 12 is an output stage cell multiplexing circuit, 13a to 13h are output stage cell selection circuits, 14
a to 14h are speed conversion circuits, 16 is an address exchange circuit,
17a to 17d are outgoing line corresponding address FIFOs 118 are read right granting circuits, 19a to 19h are vacant address management circuits, 60 to 63 are input stage cell exchange switch modules, 70 to 73 are output stage cell exchange switch modules, 8
0 to 83 are cell output stage modules. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] An input stage cell multiplexing circuit that classifies a plurality of input ports that input cells into a plurality of input port groups, and time-division multiplexes the input cells for each input port group; an input stage cell exchange switch module having an input stage cell selection circuit that selects and passes cells destined for a specific output port group out of a plurality of output ports classified into a plurality of output port groups from an output signal; A memory circuit that stores cells destined for a specific output port group that are output from a stage cell selection circuit or a previous stage output stage cell selection circuit, and manages the number of cells stored in this memory circuit for each destination and outputs a predetermined output. A storage control circuit that causes cells to be output from the storage circuit according to rules; an output stage cell multiplexing circuit that multiplexes cells output from the storage circuit; an output stage cell exchange switch module having an output stage cell selection circuit that selects and passes cells headed for the output port of the output stage, and a time division multiplexed cell connected to the output stage cell exchange switch module at the final stage. and a cell output stage module having a speed conversion circuit that converts the speed to the speed of the output port.