JPH0332058A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To facilitate design by assigning a common word line to the pair of the adjacent transistors of the same channels, and connecting the other diffusion areas of respective transistors to a first bit line and a second bit line, respectively. CONSTITUTION:A common word line 9 is assigned to the pair of adjacent transistors of the same channels. The word line 9 is common to two memory cells, and the data of the two memory cells are read out at the same time, so two bit lines 10a and 10b become necessary. The wiring pitch of the word line 9 becomes twice the pitch of the transistor. Since the wiring pitch of the word line 9 becomes twice the pitch of the transistor this way, a decorder have only to generate a word line signal at a wider pitch, and the design of the decorder can be made easy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a conductor channel circuit device equipped with a CMOS gate array.

[Prior Art 1] Figure 747 is a plan view of a four-stage academic circuit board equipped with a gate array. In the figure, 1 is a conductor chip, 2 is an input/output pad, and 3 is a basic cell stage.

8 is an enlarged plan view showing the basic cell stage 3 of FIG. 7. FIG. Here, as an example of the basic cell stage 3, one of a gate separation type is shown. In the figure, 4
a is a P-type diffusion region, and 4b is an N-type diffusion region, which corresponds to the source or drain of the P-channel transistor and the source or drain of the N-channel transistor, respectively. 5a and 5b are the gates of P-channel and N-channel transistors, respectively. FIG. 9 is an equivalent circuit diagram of the basic cell stage 3 in FIG. 8. In the figure, 6
A is a P-channel transistor, and 6b is an N-channel transistor, which are connected in series.

The basic cell stage 3 of the gate separation type disconnects the transistors connected in series at tJ+ by turning off the transistor at the position to be separated, and constructs a desired circuit using the separated transistors.

Figure 10 shows a conventional ROM composed of a gate array.
FIG. 2 is a configuration diagram showing one row of memory cell portions of FIG.

The figure shows a portion of a basic cell stage that constitutes a large number of memory cells.

In the figure, thick solid lines indicate first-layer wiring, and broken lines indicate second @ wiring.

Further, in the figure, 7 is a contact hole, 8 is a through hole, 9 is a word line, 10 is a bit line, and 11 is a GND wiring.

The contact hole 7 has the function of connecting the first @ wiring and the gate or source/drain of the transistor, and the through hole 8 has the function of connecting the first Il-th wiring and the second @-th wiring.

The data 0/1 of the memory cell is determined by the position of the contact arranged on the gate portion of the transistor, and the position of the contact on the gate portion shown in FIG. 10 is only an example of ROM data.

FIG. 11 is an equivalent circuit diagram of FIG. 10.

The source and drain of the N-channel transistor 6b are connected to the GND wiring 11. Connected to bit line 10.

Further, the gate of the transistor is connected to a GND wiring or a word line depending on the data of the memory cell.

When one of the plurality of word lines becomes HIGH level, if the gate of the corresponding transistor is connected to that word line, the transistor is turned on and the bit line and the GND wiring are connected.

On the other hand, if the gate of the corresponding transistor is connected to the GND wiring, the transistor remains in the OFF state, and the bit line and the GND wiring are not connected.

In other words, data from the corresponding memory cell is read depending on whether the bit line and the GND wiring are connected or disconnected.

FIG. 12 is a block diagram of a ROM using the memory cell of FIG. 10.

In the figure, 12 is a basic cell stage comprising a plurality of memory cells, and 13 is a decoder that generates a word line signal.

[Problem to be solved by the invention] Conventional semiconductor conduit circuit'! ! Since ta was configured as above, assuming that the number of memory cells for one basic cell stage is n, as shown in the figure, n
You will need a word line for the book.

In addition, as shown in Figure 10, the word lines must be wired at the same pitch as the transistor pitch, and the decoder must generate word line signals at a very dense pitch. The problem with the design was that the line was in the dust chamber.

This invention was developed to solve the four problems mentioned above, and the decoder design in the gate array was reduced to 1%.
The purpose of this invention is to obtain a conductor conduit circuit configured with a ROM.

(Means for Solving Problem d1) The conductor collecting circuit device according to No. 5@Mei is such that adjacent transistors of the same channel are paired in a memory cell portion and assigned a common word line.

[Operation] In the semiconductor integrated circuit device of the present invention, adjacent transistors of the same channel are paired and shared by a common word line, so the wiring pitch of the word lines is 2@ of the pitch of the transistors, and the design can be reduced to 4. Become.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a memory cell showing one embodiment of the present invention.

In the figure, 10a and 10b are bit lines.

As shown in the figure, a common word line 9 is connected to a pair of adjacent transistors having the same channel.

FIG. 2 is an equivalent circuit diagram for the configuration of FIG. 1. Word line! 9 is common to the two memory cells, and the data of the two memory cells are read at the same time, so the first
Bits @ 10a, 1 as shown in Figs.
Two 0b are required.

As shown in FIG. 1, the wiring pitch of the word lines 9 is twice that of the conventional one.

FIG. 3 is a block diagram of a ROM using the memory cell shown in FIG. 1.

As can be seen by comparing FIG. 3 with the conventional FIG. 12, half the number of word lines 9 (n/2) is required to realize a ROM with the same gl.

Therefore, the decoder only needs to generate half the number of word line signals compared to the conventional decoder, so the circuit configuration can be simplified and the design can be done in g%.

FIG. 4 is a block diagram of a memory cell according to another embodiment of the present invention constructed using P/N/NN channel transistors. Further, FIG. 5 is an equivalent circuit diagram of FIG. 4.

In the figure, 14 is VDD wiring, 10a, 10b, 10
10d are bit lines, 9a is a word line for P-channel memory cells, and 9b is a word line for N-channel memory cells.

The N-channel memory cell is the same as shown in FIGS. 1 and 2. Further, the P-channel memory cell has the same configuration as the N-channel memory cell, and a VDD wiring is used instead of a GND wiring.

Since the operational logic of N-channel transistors and P-channel transistors is different, word lines must be provided separately.

Therefore, as shown in Figure 4, word lines for P-channel memory cells and word lines for N-channel memory cells must be provided alternately, and P-channel memory cells and N-channel memory cells are separated by one pitch of transistors. They are in misaligned positions.

The fsG diagram is a configuration diagram of a ROM using the memory cell of FIG. 4. In the figure, 15 is an inverter.

In FIG. 6, a decoder of easy design similar to that shown in FIG. 3 is used. By using the output of the decoder as the word line signal for the memory cells of one channel and the inverted signal thereof as the word line signal for the memory cells of the other channel, one decoder can handle the memory cells of both channels.

This is compared to the case where one decoder is provided for each P/N channel memory cell (two in total).
Fewer decoders are required.

In addition, in the other embodiment shown in FIG. 6, the output of the decoder is 4
(It is assumed that one of the outputs is HIGH), but in the case of a negative logic output, the decoder output is used as the word line signal for the P channel memory cell, and the inverter output is
Used as a word line signal for channel memory cells.

[Effect of the invention 1 As described above, according to the present invention, the word line wiring pitch is two times the transistor pitch, so the decoder only needs to generate word line signals at a wider pitch than before.
This has the effect of making the decoder design four-dimensional.

[Brief explanation of drawings]

1 is a block diagram of a memory cell showing an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of FIG. 1, FIG. 3 is a block diagram of a ROM using the memory cell of FIG. 1, and FIG. 5 is an equivalent circuit diagram of FIG. 4, and FIG. 6 is an RO using the memory cell of FIG. 4.
7 is a plan view of a semiconductor integrated circuit device equipped with a conventional gate array, FIG. 8 is an enlarged plan view showing a basic cell stage, and FIG. 9 is an equivalent of the basic cell stage in FIG. 8. 10 is a block diagram of a conventional memory cell, FIG. 11 is an equivalent circuit diagram of FIG. 10, and FIG. 12 is a block diagram of a ROM using the memory cell of FIG. In the figure, 1 is a semiconductor chip, 2 is an input/output pad, 3 is a basic cell stage, 4a is a P-type diffusion box area, 4b is an N-type diffusion chain acid, 4 is a resistance of the diffusion chain acid, 5a and 5b are P Channel, gate of N-channel transistor, 6a, 6b
are P-channel and N-channel transistors, 7 is a contact hole, 8 is a through hole, 9 is a word line,
9a and 9b are word lines for P-channel and N-channel memory cells, respectively, 10°10a, 10b, 10c, 10
d is a bit line, 11 is a GND wiring*, 12 is a basic cell stage comprising a plurality of memory cells, 13 is a decoder, 1
4 is a VDD wiring, and 15 is an inverter. In addition, the same reference numerals in the figures indicate the same parts or parts used for mourning. Fig. 1 7 Contact, temple, -le 3° through hole II' to rND building Fig. 2 tα, tb: Transistor Fig. 3 η Fig. 4 Fig. 6/fA'J-V Fig. 9 L-- −1 −−−−−+ −1++−−+
JFigure 10Figure 11Figure 12

Claims (1)

[Claims] (1) A CMOS gate array is provided, and a common word line is assigned to adjacent transistors of the same channel as a pair in the basic cell stage constituting the gate array;
A power supply is connected to a common diffusion region of the pair of transistors, and the other diffusion region of each transistor is connected to a first bit line and a second bit line, respectively, thereby forming a ROM memory cell. Semiconductor integrated circuit device.