JPH0330516A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To suppress an input direct current voltage to be lowered by a leaked current and to reduce phase error by constituting a phase locked loop circuit by providing a comparison control part to execute input direct current voltage control in one period of a long period signal by plural times. CONSTITUTION:A phase comparison control part 36 controls an input direct current voltage 31 of a voltage control oscillator(VCO) 28 in one period of the long period signal by the plural times. An output signal 40 of the phase comparison control part 36 becomes a pulse signal synchronous with the rise timing of a short period signal and the both rise and fall timing of the long period signal and the period is almost fixed. Such a pulse signal is inputted to a D latch circuit 22 as the output signal 40 of the comparison control part 36. Thus, even when the long period signal is inputted, the input direct current voltage 31 is controlled at the same short intervals as the case of the short period signal. As a result, the phase error caused by the leaked current of the phase looked loop circuit is reduced less than the conventional circuit.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a phase-locked circuit, and more particularly to a phase-locked circuit that obtains an output signal synchronized with an input signal. Communication LSI
(large-scale integrated circuits).

[Prior art]

For example, in digital data communications, digital data that has been frequency modulated on the transmitting side is demodulated on the receiving side. In this demodulation, it is necessary to generate a clock signal synchronized with the frequency modulated data.
A phase locked loop (PLI) is used to generate this clock signal. FIG. 3 shows a conventional phase locked circuit.

The phase comparator 1 shown in the figure consists of a frequency-converted input signal 9 and an output signal 10 of a VCO (voltage controlled oscillator) 8.
Which phases should be compared and based on this comparison result <v
It controls the cos input DC voltage 11 at a predetermined timing, and includes a phase comparison system 14 and a charge pump system 15.

The phase comparison system 14 consists of D latch circuits (master-slave type flip-flop circuits) 2 and 3 and an AND gate 4, and compares the phases of the input signal 9 and the output signal 10 of the VCO 8, and charges the output signal 2 according to the phase difference. A control signal 12 and a discharge signal 13 are output. The charge control signal 12 is generated by the D latch circuit 2 which uses the input signal 9 as a clock (CLK) input and the positive voltage: tjIXW1 voltage +V as a data (D) input, and the discharge control signal 13 is generated by the AND gate 4. Clock the output (CLK
) input, and the output of the D latch circuit 2 is data (D).
It is generated by the D latch circuit 3 which receives it as an input.

The charge pump system 15 includes a positive electrode measurement current drive circuit 5
and a negative electrode measurement current drive circuit 6.

Positive electrode measurement′? 3. The current drive circuit S is the D latch circuit 2 described above.
When the charge control signal 12 output from the phase comparator 1 becomes high level, it becomes active and causes a charge constant current IC to flow through the output line of the phase comparator 1. On the other hand, the negative electrode measurement current drive circuit 6 becomes active when the discharge control signal 13 output from the D latch rGl path 3 becomes high level, and supplies the charge constant i current to the output line of the phase comparator 1. A discharge constant current Id in the opposite direction to Ic is caused to flow. A loop filter 7 having a capacitor 7A charged by the charge constant current '4 Ic and discharged by the discharge constant current rd is arranged between the output line of the phase comparison D1 and the ground line, The average DC voltage due to charging and discharging of the capacitor 7A forming the loop filter 7 becomes the input DC voltage 11 of the above-mentioned VCOS, and the oscillation frequency of the VCOS is controlled by this input DC voltage 11.

FIG. 4 shows signal waveforms of the main parts of the phase synchronized circuit having the above configuration.

The human power signal 9 is a frequency modulated digital signal,
The signal period differs depending on the modulation data. That is, the short period tij and long period t2 are set to correspond to the digital signal 1.0.

Here, the signal belonging to the short period t is referred to as a short period signal 9A, and the signal belonging to the long period t2 is referred to as a long period signal 9B.

Note that t242t.

At the timing of the rising edge of the input signal 9, the charge control signal 12, which is the output of the D latch circuit 2, becomes high level, thereby operating the positive electrode measurement current drive circuit 5, and starting charging the capacitor 7A with the charge constant current Ic. Ru. On the other hand, when the output signal 10 of the VCO 8 becomes high level, the logical product output of the AND gate 4 becomes high level, and as a result, when the discharge control signal 13 which is the output of the D latch circuit 3 becomes high level, the D latch circuit 2 Simultaneously with the reset and termination of the charging, the negative electrode measurement current drive circuit 6 is operated and the discharge current I
d starts discharging from the capacitor 7A. This discharge period tdlx! Although it is fixed and equal to the pulse width of the output Q of the VC○8, the charging period tc is determined depending on the phase difference between the input signal 9 and the output signal 10. By controlling the charging period tc in this way, the input DC voltage 11 of the VCO 8
is controlled, and by controlling the oscillation frequency of this vcos, an output signal 10 synchronized with the input signal 9 is obtained.

An example of a PLL described is Japanese Patent Application No. 61-197177.

[Problem to be solved by the invention]

By the way, in the conventional phase-locked circuit, since the charging of the capacitor 7A was started at the timing of the rising edge of the input signal waveform, the control of the input DC voltage 11 was performed even in the case of the short-period signal 9H, as well as the long-period signal. Signal 9B
Even in the case of , it is once in one period of the signal. Therefore, the input DC voltage 11 of the VCO 8 fluctuates due to the leakage current IL at the input stage of the loop filter 7 and the VCO 8.
A phase error occurs due to fluctuations in the oscillation frequency of the VCO 8. In particular, since the control interval of the input DC voltage 11 is not constant, the input DC voltage 11 of the VCO 8 in the short period t1 and the input DC voltage 11 of the VCO 8 in the long period t2
A potential difference is generated between the two, and this causes the phase error to fluctuate between the short period t and the long period t2. That is, when the charging current of the capacitor 7A is Ic, the composite impedance of the loop filter including this capacitor 7A is Z, and the discharging current is Id, VC at the short period signal 9A is
The input DC voltage V of O8 is V,=Z(t c ・I c−td ・Id+t□・I
t)・・・・・・・・・・・・・・・(1), and the input DC voltage v2 of the VCO 8 in the long period signal 9B is V2=Z(tc ・Ic−td−Id+t,・I
3)・・・・・・・・・・・・・・・(2), between ■1 and v2.

d y=v□ v2=z + I t (tt
tz) (3) A potential difference is generated, and due to this potential difference, the phase error fluctuates between the short period t1 and the long period t2.

As is clear from the above equation, the phase error increases as the leakage current IL increases. Therefore, a phase-locked circuit is formed in a bipolar integrated circuit in which circuit components such as bipolar transistors, diodes, resistors, and capacitors are formed inseparably within a single silicon substrate using the same manufacturing process as silicon planar diffused transistors. In cases such as ij), the input impedance of vcos becomes particularly low, so the leakage current It increases, and the phase error becomes non-negligible.

An object of the present invention is to provide a phase-locked circuit in which phase errors caused by the leakage current are reduced.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, an oscillation means whose oscillation frequency changes according to the input DC voltage, and an input signal including a short-period signal and a long-period signal are compared with the oscillation output of the oscillation means, and the input DC voltage is adjusted based on the result of this phase comparison. A phase-locked circuit having phase comparison means for controlling voltage at a predetermined timing, in which the phase-locked circuit is configured by providing a comparison control section that executes input DC voltage control multiple times in one period of a long-period signal. be. Here, the number of times of input DC voltage control in one period of the long-period signal can be an integral multiple of the number of times of control in one period of the short-period signal. Furthermore, in order to suppress fluctuations in the phase error, it is preferable to make the control interval of the input DC voltage substantially constant. In order to easily realize such timing control, the above DC voltage control is executed at the timing of one edge change of the short period signal, and the above input DC voltage control is executed at the timing of both edge changes of the long period signal. It is a good idea to have it executed.

[For production]

According to the above-mentioned means, the input DC voltage control in one period of the long-period signal is executed multiple times, which suppresses the input DC voltage drop caused by the leakage current of the circuit in one period of the long-period signal. and achieves a reduction in phase error.

〔Example〕

FIG. 1 shows a phase locked circuit as an embodiment of the present invention. The phase-locked circuit shown in the figure is a communication LSI that has a function to demodulate frequency-modulated digital signals, although it is not particularly limited. Built into a bipolar integrated circuit.

The phase comparator 21 shown in FIG. 1 compares which phase of the frequency-modulated input signal 29 and the output signal 30 of the VCO (voltage controlled oscillator) 28, and based on the result of this comparison, the input DC voltage of <VC028. 21 at a predetermined timing, and includes a phase comparison system 34 and a charge pump system 35. The phase comparison system 34 includes a phase comparison control section 36, D latch circuits 22, 23, and an AND gate 24, and has an input signal 29 and an output signal 3 of the VCO 28.
0 and outputs a charge control signal 32 and a discharge control signal 33 as a result of this comparison. Here, the charge control signal 32 is transmitted to the phase comparison control section 36.
The discharge control signal 33 is generated by the D latch circuit 22, which uses the output signal 40 of
is generated by the D latch circuit 23 which uses the output signal 41 of the two-man AND gate 24 as a clock (CLK) input and the output signal 32 of the D latch circuit 22 as a data (D) input.

The phase comparison control unit 36 controls the input DC voltage 31 of the vC○ 28 multiple times in one cycle of the long-period signal 29B (see FIG. 2). 29 period changes (short period t and long period t
2), by making the output signal 40 into equally spaced pulses, the start timing of the control is controlled so that the control interval of the input DC voltage 31 is constant. Such timing control can be easily realized by executing the input DC voltage control at the timing of one edge of the short-period signal 29a, and by executing the input DC voltage control at the timing of the rain edge of the long-period signal. In the embodiment, an edge detector 37 detects an edge of the input signal 29, a D latch circuit 38 is connected so that the Q output is used as a data input and divides the output signal 30 of the VCO 28 into 1/2, and an edge detector By forming the phase comparison control section 36 including an AND gate 39 that calculates the AND of the output signal 42 of the latch circuit 37 and the output signal 43 of the latch circuit 38,
This enables input DC voltage control as described above.

Note that this input DC voltage control will be described in detail later.

Further, the charge pump system 35 includes a positive electrode measurement current drive circuit 25 and a negative electrode measurement current drive circuit 26. The positive electrode measurement current drive circuit 25 becomes active when the charge control signal 32 output from the D latch circuit 22 becomes high level, and causes a charge constant current Ic to flow through the output line of the phase comparator 21. On the other hand, the negative electrode measurement current drive circuit 26 becomes active when the discharge control signal 33 output from the D latch circuit 23 becomes high level, and outputs the charge constant current Ic to the output line of the phase comparator 21. Reverse discharge constant current I
d flows. Between the output line of this phase comparator 21 and the ground line, there is a loop filter 2 comprising a capacitor 27A that is charged by the charge constant current Ic and discharged by the discharge constant current Id.
7 is arranged, and the average DC voltage due to charging and discharging of the capacitor 27A forming this loop filter 27 is the above-mentioned VC0.
The oscillation frequency of VC028 is controlled by this input DC voltage 31. here,
The phase comparator 21. vC028 corresponds to the phase comparison means 2 oscillation means in the present invention.

FIG. 2 shows signal waveforms of the main parts of the phase synchronized circuit having the above configuration.

The input signal 29 is a digital signal subjected to same wave number modulation, and the signal belonging to the short period t□ is the short period signal 29A, and the signal belonging to the long period t2 is the long period signal 29B. Furthermore, t2
The cape is 2tl.

Such edges of the input signal 29 are detected by the edge detector 37. Output signal 4 obtained by this edge detection
2 is a pulse signal that rises at each rising and falling edge timing of the short-period signal 29A and the long-period signal 29B, and at this stage there is still a difference in the period between the short-period signal 29A and the long-period signal 29B. There is. Such edge detection is performed by connecting the output terminal of a two-person exclusive OR gate to one input terminal, either directly or via a predetermined delay element, and applying the input signal 29 to the other input terminal of the gate. In addition, this becomes possible by obtaining an exclusive OR output.

On the other hand, the output signal 30 of the VC028 is frequency-divided by 1/2 by the D latch circuit 38 which functions as a frequency divider, and the frequency-divided output signal 43 is transmitted to the AND gate 39. 37 output signal 42
The logical product is calculated. In this logical operation, the pulse signal 44 obtained by detecting the falling edge of the short-period signal 29A appears as the output signal 40 of the phase comparison control section 36 because the output state of the D latch circuit 38 is low level. Finally, the output signal 4 of the comparison control section 36
0 is a pulse signal that is synchronized with both the rising timing of the short-period signal 29A and the rising and falling timings of the long-period signal 29B, and its period is approximately constant. Such a pulse signal is input to the D latch circuit 22 as an output signal 40 of the comparison control section 36.

The charge control signal flow drive circuit 25 is an output of the D latch circuit 22 at the timing of the rising edge of the output signal 40.
is operated, and the capacitor 27 is
Charging of A starts.

On the other hand, when the output signal 30 of the VC028 becomes high level, the logical product output of the AND gate 24 becomes high level, and as a result, the discharge control signal 33 which is the output of the D latch circuit 23 becomes high level, and the D latch circuit 2
2 is reset and the charging is terminated, at the same time,
The negative electrode measurement current drive circuit 26 is operated, and discharge from the capacitor 27A is started by the discharge current Id.

This discharging period td is fixed and equal to the pulse width of the output signal of vC○28, but the charging period tc is fixed and equal to the pulse width of the output signal of vC○28.
and the output signal 30 are determined depending on the phase difference. By controlling the charging period tc in this manner, the input DC voltage 31 of the VC028 is controlled, and by controlling the oscillation frequency of this vC028, the output signal 3 synchronized with the input signal 29 is generated.
0 is obtained.

In the circuit operation described above, the basic operation of the phase comparator 21 is the same as in the conventional example, but in this embodiment, the equally spaced pulse signal from the 1-phase comparison control section 36 is input to the clock input terminal of the D latch circuit 22. As is clear from FIG. 2, the charge control signal 32. Each discharge control signal 33 is synchronized with the input signal 2.
9 is substantially constant regardless of the periodic change of the capacitor 27A, and as a result, the control interval of the input DC voltage 21 due to charging and discharging of the capacitor 27A becomes substantially constant. In other words, the long period signal 2
Even in the case of the 9B input, the input DC voltage 31 is controlled at short intervals similar to the case of the short period signal 29A. Therefore, the degree to which the input DC voltage 31 decreases due to leakage current in the circuit is about the same in one period of the long-period signal 29B as in one period of the short-period signal 29A, and as a result,
The phase error due to leakage current in the circuit is less than in conventional circuits.

According to the above embodiment, the following effects can be obtained.

(1) By inputting the input signal 29 not directly to the D latch circuit 22 but via the 1-phase comparison control unit 36, input DC voltage control is performed twice in one period of the long-period signal 29B. Therefore, the long-period signal 29
The input DC voltage control interval in one cycle of B is shorter than that of the conventional circuit, thereby reducing the drop in input DC voltage caused by leakage current in the circuit and reducing phase errors.

(2) Also, by performing phase comparison control so that the control interval of the input DC voltage 31 of the VC028 is almost constant, it is possible to change the phase error between the case of short period signal 29A input and the case of long period signal 29B input. can be suppressed.

(3) Furthermore, the input DC voltage 31 of VC02B is controlled at the timing of the rising edge of the short period signal 29A, and the input DC voltage 31 of VC028 is controlled at the timing of both the rising and falling edges of the long period signal 29B. By doing so, (1) above.

The input DC voltage control in (2) can be easily performed with a relatively simple configuration.

(4) The effects of (1) to (3) above are particularly noticeable when the circuit of this embodiment is built into a bipolar integrated circuit in which the leakage current of the circuit is relatively large.

Although the invention made by the present invention has been specifically described above based on Examples, the present invention is not limited to the above-mentioned Examples.
Various changes can be made without departing from the gist of the invention.

For example, as long as the loop filter 27 has a capacitor 27A, it may be adjusted to obtain desired filter characteristics by connecting a resistor in parallel or in series with the capacitor 27A, or a charge pump system may be used. It is also possible to operate 35 with a single power supply. The phase comparator 21, especially the phase comparator 36, can also be realized by other logic circuit configurations, and the number of phase comparison operations in the short period t1 and the long period t2 may be further increased to reduce the phase error.

In the above explanation, the invention made by the present inventor was mainly applied to communications mI and SI, which are the background fields of application, but the present invention is not limited to this, and the signal period is constant. A data processing LS is used as a circuit to obtain an output signal synchronized with an input signal that is not
It can also be applied to circuit devices other than I and LSI. The present invention can be applied to conditions where at least phase errors caused by leakage current can be reduced.

(Effects of the invention) The effects obtained by typical inventions disclosed in this cabinet are briefly explained as follows.

In other words, since the input DC voltage control is performed multiple times in one period of the long-period signal, the interval between input DC voltage controls in one period of the long-period signal is shorter than before, and the input DC voltage caused by leakage current is reduced. The drop in voltage is reduced, thereby making it possible to reduce phase errors.

Further, by performing phase comparison control so that the control interval of the input DC voltage is substantially constant, it is possible to suppress fluctuations in phase error between the case of short-period signal input and the case of long-period signal input.

Furthermore, by controlling the input DC voltage at the timing of the rising edge of the short-period signal, and by controlling the input DC voltage at the timing of both the rising and falling edges of the long-period signal, the input DC voltage control described above can be achieved. can be easily performed with a relatively simple configuration.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of a phase synchronization circuit according to the present invention. FIG. 2 is an operation timing diagram of the circuit of this embodiment, FIG. 3 is a conventional circuit diagram of a phase locked circuit, and FIG. 4 is an operation timing diagram of the conventional circuit. 21...Phase comparator, 28...■C0129...
Input signal, 29A... Short period signal, 29B... Long period signal, 30... Output signal I, 31... Input DC voltage, 36... Phase comparison control unit. Figure 2

Claims (1)

[Claims] 1. An oscillation means whose oscillation frequency changes according to an input DC voltage, and a phase comparison between an input signal including a short-period signal and a long-period signal and an oscillation output of the oscillation means; and phase comparison means for controlling the input DC voltage at a predetermined timing based on the comparison result, and obtaining an output signal synchronized with the input signal, wherein the phase comparison means controls one of the long period signals. A phase synchronized circuit comprising a phase comparison control section that executes input DC voltage control multiple times in a period. 2. The phase synchronized circuit according to claim 1, wherein the number of times of input DC voltage control in one period of said long period signal is an integral multiple of the number of times of input DC voltage control in one period of said short period signal. 3. The phase control unit executes the input DC voltage control at the timing of one edge change of the short period signal,
3. The phase locked circuit according to claim 1, wherein the input DC voltage control is executed at the timing of a change in both edges of the long-period signal. 4. The phase synchronized circuit according to claim 1, 2 or 3, wherein the phase comparison control section controls the start timing of the control so that the input DC voltage control interval is substantially constant.