JPH0329761Y2 - - Google Patents

Info

Publication number
JPH0329761Y2
JPH0329761Y2 JP1983098087U JP9808783U JPH0329761Y2 JP H0329761 Y2 JPH0329761 Y2 JP H0329761Y2 JP 1983098087 U JP1983098087 U JP 1983098087U JP 9808783 U JP9808783 U JP 9808783U JP H0329761 Y2 JPH0329761 Y2 JP H0329761Y2
Authority
JP
Japan
Prior art keywords
head
amplifier
recording
terminal
playback
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1983098087U
Other languages
Japanese (ja)
Other versions
JPS609005U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9808783U priority Critical patent/JPS609005U/en
Publication of JPS609005U publication Critical patent/JPS609005U/en
Application granted granted Critical
Publication of JPH0329761Y2 publication Critical patent/JPH0329761Y2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Television Signal Processing For Recording (AREA)

Description

【考案の詳細な説明】 (イ) 産業上の利用分野 本考案は録画及び再生機能を備えたビデオテー
プレコーダ(以下VTRと称する)に用いられる
ヘツド切換用集積回路に関する。
[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to an integrated circuit for head switching used in a video tape recorder (hereinafter referred to as VTR) equipped with recording and playback functions.

(ロ) 従来技術 一般にVTRにおいて、録画時ビデオテープに
対してビデオヘツドによつて映像信号を記録する
場合及び再生時前記ビデオテープに記録された前
記映像信号を再生する場合、前記映像信号を増幅
するため、記録アンプ及び再生用のヘツドアンプ
が内蔵された集積回路(以下ICと称する)が用
いられている。
(B) Prior art In general, in a VTR, when a video signal is recorded on a videotape by a video head during recording, and when the video signal recorded on the videotape is reproduced during playback, the video signal is amplified. Therefore, an integrated circuit (hereinafter referred to as an IC) is used which has a built-in recording amplifier and a playback head amplifier.

その構成は、第1図に示す如く、ビデオヘツド
1の一端に入力端子2、他端に出力端子3を接続
すると共に録画、再生切換用のスイツチ(通常
録再切換スイツチと呼ばれる)を接続し、前記入
力端子2にはヘツドアンプ5、プリアンプ6及び
アンプ7が順次接続されており、一方前記出力端
子3には記録アンプ8が接続されている。前記切
換スイツチがA側の場合は録画モードで、B側
の場合再生モード状態に設定され、ビデオヘツド
1からIC内のヘツドアンプ5及びプリアンプ
6を介してアンプ7にビデオテープ(図示せず)
に記録された映像信号を加えて、所定の振幅にな
し、テレビ受像機の画面上に再生する。
As shown in Figure 1, the configuration is such that an input terminal 2 is connected to one end of the video head 1, an output terminal 3 is connected to the other end, and a switch 4 for switching between recording and playback (usually called a recording/playback switch) is connected. A head amplifier 5, a preamplifier 6, and an amplifier 7 are connected in sequence to the input terminal 2, while a recording amplifier 8 is connected to the output terminal 3. When the changeover switch 4 is on the A side, it is set to the recording mode, and when it is on the B side , it is set to the playback mode. )
The recorded video signal is added to the video signal, adjusted to a predetermined amplitude, and reproduced on the screen of a television receiver.

ところが前述の構成では、再生時ビデオヘツド
1の接地点G1とICの内部に設けたヘツドアン
プ5の接地点G2との間にIC内部の接地ラインの
共通インピーダンス及び該ICが取付けられたプ
リント基板における接地ライン(銅箔のパターン
上)のインピーダンスにより電位差が生じ、これ
がレベルの非常に小さいヘツドアンプ5に加わる
映像入力信号に悪影響を及ぼし、信号対雑音比
(S/N)の悪化、歪の発生の原因となり、更に
前記ヘツドアンプ5の入出力間の電圧利得が高い
ために発振などの不安定な動作を引起す欠点とな
つていた。
However, in the above configuration, the common impedance of the ground line inside the IC and the IC are connected between the ground point G1 of the video head 1 and the ground point G2 of the head amplifier 5 provided inside the IC 9 during playback. A potential difference occurs due to the impedance of the ground line (on the copper foil pattern) on the printed circuit board, and this adversely affects the video input signal applied to the head amplifier 5, which has a very low level, resulting in deterioration of the signal-to-noise ratio (S/N) and distortion. Furthermore, since the voltage gain between the input and output of the head amplifier 5 is high, it has become a drawback of causing unstable operation such as oscillation.

(ハ) 考案の目的 本考案は、前述の欠点を除去したVTRの再生
時におけるS/Nの向上を図ることを目的とす
る。
(c) Purpose of the invention The purpose of the invention is to improve the S/N ratio during VTR playback by eliminating the above-mentioned drawbacks.

(ニ) 考案の構成 本考案は、ビデオヘツドの一端に接続された入
力端子と、該ビデオヘツドの他端に接続された出
力端子と、記録・再生の各モードに切換える切換
スイツチと、前記入力端子及び出力端子に各々接
続されたヘツドアンプ及び記録アンプと、接地端
子とを備えたヘツド切換用集積回路において、前
記切換スイツチの接地ラインと前記ヘツドアンプ
の接地ラインが接地された第1の接地端子と、前
記ヘツドアンプを除く記録アンプ等の接地ライン
に接続された第2の接地端子とを前記集積回路に
設けた構成である。
(d) Structure of the invention The invention comprises an input terminal connected to one end of a video head, an output terminal connected to the other end of the video head, a changeover switch for switching between recording and playback modes, and an input terminal connected to the other end of the video head. In a head switching integrated circuit comprising a head amplifier and a recording amplifier connected to a terminal and an output terminal, respectively, and a ground terminal, a first ground terminal to which a ground line of the changeover switch and a ground line of the head amplifier are grounded; , and a second ground terminal connected to a ground line of a recording amplifier, etc. other than the head amplifier, are provided on the integrated circuit.

(ホ) 実施例 第2図は本考案の実施例を示し、第1図と同一
素子には同一図番を示してあり、10はIC11
内に設けた録画・再生切換スイツチ、12は該録
画・再生切換スイツチ10を制御する制御回路、
13は前記ヘツドアンプ5及び該録画・再生切換
スイツチ10の接地ラインに接続された第1の端
子、14は記録アンプ8、プリアンプ6及びアン
プ7の接地ラインに接続された第2の接地端子、
15は前記制御回路12に接続された制御端子で
ある。
(E) Example Figure 2 shows an example of the present invention, in which the same elements as in Figure 1 are given the same figure numbers, and 10 is IC 11.
12 is a control circuit for controlling the recording/playback switch 10;
13 is a first terminal connected to the ground line of the head amplifier 5 and the recording/playback switch 10; 14 is a second ground terminal connected to the ground lines of the recording amplifier 8, preamplifier 6, and amplifier 7;
15 is a control terminal connected to the control circuit 12.

次に本考案の動作について説明すると、先ず録
画時操作ボタン(図示せず)の操作により、録画
のための制御信号が発生した場合、制御端子15
に該制御信号が印加され、録画・再生切換スイツ
チ10は制御回路12により第2図のA位置に設
定され、記録アンプ8を通してビデオヘツド1に
加えられた映像信号は、該ビデオヘツド1によつ
て磁気テープ(図示せず)に記録される。
Next, to explain the operation of the present invention, first, when a control signal for recording is generated by operating a recording operation button (not shown), the control terminal 15
The control signal is applied to the recording/playback switch 10, and the control circuit 12 sets the recording/playback switch 10 to position A in FIG. and recorded on a magnetic tape (not shown).

一方再生時、操作ボタンの操作により、再生の
ための制御信号が発生し制御端子15に該制御信
号が印加され、制御回路12によつて録画・再生
切換スイツチ10は第2図のB位置に切換わり、
前記磁気テープに記録された映像信号は、ヘツド
アンプ5、プリアンプ6及びアンプ7に加わり、
VTRに接続されるテレビ受像機等のデイスプレ
イ装置に画面が再生される。
On the other hand, during playback, a control signal for playback is generated by operating the operation button, the control signal is applied to the control terminal 15, and the control circuit 12 moves the recording/playback switch 10 to position B in FIG. switching,
The video signal recorded on the magnetic tape is applied to a head amplifier 5, a preamplifier 6, and an amplifier 7,
The screen is played back on a display device such as a television receiver connected to the VTR.

ここで再生時、映像信号、音声信号及びコント
ロール信号等の種々の信号が前記ICの取付けら
れるプリント基板上に現われ、接地ラインが振ら
れるが、ヘツドアンプ5とビデオヘツド1の接地
ラインが同一に構成してあり、この接地ラインは
前記第1の接地端子13にて共通に取出し、これ
に対し前記ヘツドアンプ5及びビデオヘツド1の
接地ラインを除く記録アンプ8、プリアンプ6、
アンプ7に接続された接地ラインは別個に第2の
接地端子14にて接続した構成であり、各接地ラ
イン間における電位変動は生じることがなく、安
定に動作し得る。
During playback, various signals such as video signals, audio signals, and control signals appear on the printed circuit board on which the IC is mounted, and the ground line is waved, but the ground lines of the head amplifier 5 and the video head 1 are constructed in the same way. This ground line is commonly taken out at the first ground terminal 13, and the recording amplifier 8, preamp 6,
The ground lines connected to the amplifier 7 are connected separately through the second ground terminal 14, and potential fluctuations do not occur between the ground lines, allowing stable operation.

(ヘ) 考案の効果 本考案のヘツド切換用集積回路によれば、先ず
ヘツド切換スイツチを集積回路(IC)内に設け
た構成で、該ヘツド切換スイツチの接地ラインと
ヘツドアンプの接地ラインとを共通接続すると共
にこれとは別個に記録アンプ等の接地ラインを設
けてあるので、従来ヘツド切換用集積回路を用い
たVTRにおける再生時のS/Nの低下を未然に
防止することができ、更に該集積回路を使用した
プリント基板の銅箔パターン設計上銅箔による電
圧降下を配慮する必要もなく、その設計が容易に
なる利点も得られる。
(f) Effects of the invention According to the head switching integrated circuit of the present invention, first, the head switching switch is provided in an integrated circuit (IC), and the grounding line of the head switching switch and the grounding line of the head amplifier are common. Since a ground line is provided for the recording amplifier, etc., in addition to this connection, it is possible to prevent a drop in S/N during playback in a VTR using a conventional head switching integrated circuit, and furthermore, There is no need to consider the voltage drop caused by the copper foil when designing the copper foil pattern of a printed circuit board using an integrated circuit, and there is an advantage that the design becomes easier.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のヘツド切換用集積回路の要部ブ
ロツク図、第2図は本考案の同ヘツド切換用集積
回路の要部ブロツク図を示す。 主な図番の説明、1……ビデオヘツド、2……
入力端子、3……出力端子、,10……録画・
再生切換スイツチ、5……ヘツドアンプ、6……
プリアンプ、7……アンプ、8……記録アンプ、
9,11……IC、13……第1の接地端子、1
4……第2の接地端子。
FIG. 1 is a block diagram of the main parts of a conventional integrated circuit for switching heads, and FIG. 2 is a block diagram of the main parts of the integrated circuit for switching heads according to the present invention. Explanation of main drawing numbers, 1...Video head, 2...
Input terminal, 3...Output terminal, 4,10 ...Recording/
Playback selector switch, 5...Head amplifier, 6...
Preamplifier, 7...amplifier, 8...recording amplifier,
9, 11 ...IC, 13...first ground terminal, 1
4...Second grounding terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ビデオヘツドの一端に接続された入力端子と、
該ビデオヘツドの他端に接続された出力端子と、
該ビデオヘツドの他端に接続された再生用の端子
と、記録モードに応じて前記入力端子の信号を、
再生モードに応じて前記端子の信号を選択的に発
生する切換スイツチと、前記入力端子及び出力端
子に各々接続されたヘツドアンプ及び記録アンプ
とを備えたヘツド切換用集積回路において、前記
切換スイツチの出力端と前記ヘツドアンプの接地
ラインとを直接に共通接続した後、集積回路の外
部に接地するようにしたことを特徴とするヘツド
切換用集積回路。
an input terminal connected to one end of the video head;
an output terminal connected to the other end of the video head;
A playback terminal connected to the other end of the video head and a signal from the input terminal depending on the recording mode,
In a head switching integrated circuit comprising a changeover switch that selectively generates a signal at the terminal according to a playback mode, and a head amplifier and a recording amplifier connected to the input terminal and the output terminal, respectively, the output of the changeover switch is 1. An integrated circuit for head switching, characterized in that the terminal and the ground line of the head amplifier are directly connected in common and then grounded to the outside of the integrated circuit.
JP9808783U 1983-06-24 1983-06-24 Integrated circuit for head switching Granted JPS609005U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9808783U JPS609005U (en) 1983-06-24 1983-06-24 Integrated circuit for head switching

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9808783U JPS609005U (en) 1983-06-24 1983-06-24 Integrated circuit for head switching

Publications (2)

Publication Number Publication Date
JPS609005U JPS609005U (en) 1985-01-22
JPH0329761Y2 true JPH0329761Y2 (en) 1991-06-25

Family

ID=30233040

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9808783U Granted JPS609005U (en) 1983-06-24 1983-06-24 Integrated circuit for head switching

Country Status (1)

Country Link
JP (1) JPS609005U (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0536686Y2 (en) * 1986-03-27 1993-09-16

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS482716U (en) * 1971-05-20 1973-01-13

Also Published As

Publication number Publication date
JPS609005U (en) 1985-01-22

Similar Documents

Publication Publication Date Title
US4466026A (en) Record/reproduce circuit for VTR
JPH0329761Y2 (en)
US5309297A (en) Digital cassette tape reproducing device including novel drive circuit
JP2718041B2 (en) Video tape recorder
JPS5914901Y2 (en) Recording/playback device
JP2773247B2 (en) Magnetic recording / reproducing device
JP2689786B2 (en) Crosstalk reduction circuit
JP2697127B2 (en) Magnetic recording / reproducing device
JP2692077B2 (en) Double cassette tape recorder
KR910004666Y1 (en) Audio signal control circuit for vtr
JPS6112614Y2 (en)
JPS5914897Y2 (en) tape recorder
US5497242A (en) Write current control circuit for audio recording
JPH0422406Y2 (en)
JP2790049B2 (en) Recording device
JPS5928504Y2 (en) magnetic recording and playback device
JPH02185196A (en) Camera incorporating type video tape recorder
JPH0329762Y2 (en)
JPH04252678A (en) Signal line connection structure for signal recording/ reproducing device
JPS5850485Y2 (en) magnetic recording and playback machine
JPH0548293Y2 (en)
KR920008552Y1 (en) Audio dubbing circuit for vtr
KR920002582B1 (en) Noise removing circuit for picture searching
JPS5914120A (en) Magnetic sound recording and reproducing device
JP2557243Y2 (en) Tape recorder