JPH03295323A - Digital radio receiver - Google Patents

Abstract

PURPOSE:To cope with a glitch unable to be absorbed with a filter, and to prevent synchronizing step-out by absorbing the glitch by generating a short pulse wider than the width of the glitch while synchronizing with the rise of the output of a clock, and on the other hand, delaying the original clock by the rise time of the short pulse, and passing both of them through an AND gate. CONSTITUTION:A pulse generation circuit 10 generating the pulse wider than the width of the glitch at the rise of a demodulation clock, a delay circuit 11 delaying the clock and data output by time required for the pulse to rise, and the AND gate 8 adding the clocks passing through the pulse generation circuit 10 and the delay circuit 11 and generating a new clock are provided. Then, the glitch is absorbed by generating the short pulse wider than the width of the glitch while synchronizing with the rise of the output of the clock, and on the other hand, the original clock is delayed by the rise time of the short pulse, and both of them pass through the AND gate 8. Thus, the glitch can be eliminated by executing digital processing in addition to the filter of an analog circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital radio receiving device using a leaky coaxial cable, and in particular to switching of demodulation output.

[Conventional technology]

FIG. 3 shows an example of the reception configuration of a conventional digital radio receiver similar to that disclosed in, for example, Japanese Unexamined Patent Publication No. 83-121327.

In the figure, (1) is a leaky coaxial antenna for trains, (2)
is a digital radio receiver, (3) is a voltage generation circuit (R5ST) that generates a voltage proportional to the strength of received radio waves, (
4) is a voltage comparison circuit; (5) is a latch circuit that outputs a switching (gate opening/closing) signal according to the rising edge of the demodulation clock;
(6) is a latch circuit (5).

(5) A match prohibition circuit that prevents the outputs from matching, and (7) a match prohibition circuit that prevents the outputs from matching. (7) is a glitch in the switching signal that occurs when the output voltage of the voltage generation circuit is reversed due to jitter (fluctuation) of the demodulated clock. ), (8)
(9) is an AND gate in which the switching signal, data, and clock are manually input, and (9) is an OR gate that always outputs the data and clock on the side where the radio waves are stronger.

In the configuration shown in Figure 3 above, two leaky coaxial antennas (1)
The radio waves taken in by the receivers enter the connected receivers (2) and are demodulated, and data and clocks are output. On the other hand, a voltage generating circuit (3) extracts a DC voltage proportional to the strength of the radio wave. Voltage comparison circuit (
4) compares the high and low levels of this voltage and uses the later AND gate (8
) switching signal (H-L gate opening/closing signal) is output.

This switching signal is output from the latch circuit (5) in synchronization with the rising edge of the demodulated clock of each receiver (2), passes through the match prohibition circuit (6), and is further filtered to prevent glitches caused by jitter of the demodulated clock ( 7) and is input to the AND gate (8). In addition, the demodulated data and clock of the receiver (2) are manually input to the other input terminal of the AND gate (8), and only the gate (8) receiving the open signal outputs the data and clock, and then the OR gate ( 9) and is output. Therefore, as mentioned above, the switch is always made to the side where the stronger radio waves are coming from, and data and clocks from the stronger electric field side are obtained.

[Problem to be solved by the invention]

However, as described above, the method of selecting the stronger radio wave using spatial diversity and switching the demodulated output at the rising edge of the demodulated clock causes glitches in the switching (open/close) signal due to the jitter of the demodulated clock. For this reason, of course, glitches occur in the data and clock that pass through the subsequent gate 1-, and since the terminal side judges the data at the falling edge of the demodulated clock, if a glitch occurs in the clock, it will cause a glitch in the clock. The order of the data was determined to be different by one bit, resulting in a burst error and a loss of synchronization.

Conventionally, in order to prevent this, a glitch noise removal circuit using a flip-flop was disclosed, for example, as shown in Utility Model Application Publication No. 1-63225, but in the above conventional configuration, the switching (opening/closing) signal is passed through a filter (7). However, when the human-powered radio waves are weak, the jitter of the clock becomes wide and cannot be absorbed, and if the time constant of the filter (A) is made too large, the switching signal becomes high.
-L.

There were problems such as the timing for L-H becoming longer and gate operation becoming unstable.

This invention has been made to solve the problems mentioned in section 2 above, and aims to provide a digital radio receiving device that can sufficiently cope with glitches caused by clock jitter when input radio waves are weak.

[Means to solve the problem]

A digital radio receiving device according to the present invention includes a plurality of leaky coaxial cable antennas mounted on a moving body, and a plurality of digital radio receivers connected to the antennas, respectively. In a digital radio receiver equipped with a switching means for switching and selecting a higher demodulated output based on a demodulated clock, there is provided a pulse generation circuit that generates a pulse wider than a glitch width at the rising edge of the demodulated clock, and a pulse rising time. The present invention includes a delay circuit that delays the clock and data output by the same amount, and an anchor that generates a new clock by adding the clocks that have passed through the pulse generation circuit and the delay circuit.

[Operation] In this invention, in synchronization with the rising edge of the clock output, a short pulse wider than the width of the glitch is generated to absorb the glitch, while the original clock is delayed by the rising time of the short pulse, In addition to filtering the analog circuit by passing both signals through an anchor, digital processing is also applied to eliminate glitches.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and in the figure,
The same parts as in FIG. 3 are given the same reference numerals, and the explanation thereof will be omitted.

In the figure, as a new configuration, (lO) indicates a pulse generation circuit that generates a pulse slightly wider than the glitch at the rising edge of the clock, and (11) indicates a delay circuit. It is synchronized with the rising edge of the clock and generates a short pulse wider than the width of the glitch to absorb the glitch, while the original clock is delayed by the rise time of the short pulse and both are passed through an AND gate. ,
In addition to the analog circuit filter, by applying rough digital processing to eliminate glitches, it is possible to cope with glitches in weaker radio wave conditions, and to obtain good line quality. ing.

Next, the operation will be explained. In the configuration shown in FIG. 1, the radio waves taken in by the two leaky coaxial antennas (1) enter the connected receivers (2) and are demodulated, and data and a clock are output. On the other hand, the voltage generating circuit (3y) extracts a DC voltage proportional to the strength of the radio wave.The voltage comparator circuit (4) compares the high and low levels of this voltage and outputs the switching signal (H- This switching signal is output from the latch circuit (5) in synchronization with the rise of the demodulation clock of each receiver (2), passes through the match prohibition circuit (6), and is further demodulated. It passes through a filter (7) to prevent glitches caused by clock jitter and is input to an AND gate (8).The other input terminal of the AND gate (8) is connected to a receiver (2).
The demodulated data and clock are input, and the data and clock are output only from the gate (8) to which an open signal is received, and then output through the OR gate (9).

Furthermore, the clock that has passed through the OR gate (9) is passed through a pulse generation circuit (10) that generates a pulse slightly wider than the glitch width at the rising edge of the clock, and a delay circuit (11) that delays the clock by the time that the pulse rises. It can be divided into Next, a delay circuit (10) and a pulse generation circuit (1
The clocks that have passed through 1) are added together again by an AND gate (8) and output.

In addition, in the above embodiment, a digital radio receiving device for a train using two leaky coaxial antennas was explained.
In the case of a device using three leaky coaxial antennas (Figure 2), the DC output voltages of the three voltage generating circuits are compared, and the digital H voltage is output only to the circuit with the highest voltage, and the subsequent Open the AND gate. Then, the demodulated output on the side of the strongest electric field is always obtained. Therefore, in this circuit as well, the above configuration has the same effect on glitches during switching in a weak electric field.

〔Effect of the invention〕

As described above, according to the present invention, glitches can be absorbed by generating short pulses wider than the glitch width in synchronization with the rising edge of the clock output in order to prevent glitches when switching the demodulation output of a digital radio receiver. On the other hand, the original clock is delayed by the rise time of a short pulse, and both are passed through an AND gate.In addition to the filter, digital processing is also applied, so it is sufficient to deal with glitches that cannot be absorbed by the filter. This has the effect of preventing synchronization and improving line quality.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG. 3 is a block diagram showing a conventional digital radio receiving apparatus. In the figure, 1) is a leaky coaxial antenna (antenna), 2) is a receiver, (3) is a voltage generation circuit (R5SI), and 4 is a leaky coaxial antenna (antenna).
is a voltage comparison circuit, (5) is a latch circuit, 6 is a match prohibition circuit, (7) is a filter, 8 is an ant gate, (9
) is an OR gate, 10) is a pulse generation circuit, and 11) is a delay circuit. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] It is equipped with a plurality of leaky coaxial cable antennas mounted on a mobile object and a plurality of digital radio receivers connected to each antenna, and the demodulated output of the receiver with a higher electric field is determined based on the demodulated clock. In a digital radio receiving device, the digital radio receiving device is equipped with a switching means for switching and selecting, and a pulse generating circuit that generates a pulse wider than the glitch width at the rising edge of the demodulated clock, and a delay that delays the clock and data output by the rising time of the pulse. circuit and
A digital radio receiving device characterized by comprising an AND gate that generates a new clock by adding the clocks that have passed through the pulse generation circuit and the delay circuit.