JPH03292057A - Picture processing circuit - Google Patents

Abstract

PURPOSE:To prevent occurrence of an interference stripe at binary coding by averaging a picture element with an averaging circuit with respect to the picture element of a dense density to output the picture element whose periodicity is made thin and emphasizing the picture element by an emphasis circuit with respect to the picture element whose density is thin. CONSTITUTION:A difference circuit 4 reads a picture data from a 3X3 matrix memory 3 and calculates a differentiating or a secondary differentiating value of a center picture signal (S0) with respect to its surrounding picture element. A difference output D0 of the difference circuit 4 is fed to a comparator circuit 5, in which the signal is compared with a threshold level T0 and in the case of D0>T0, the comparator circuit 5 outputs a selection signal to allow a selection circuit 8 to select an output of an emphasis circuit 6. In the case of D0<T0, the comparator circuit 5 outputs a selection signal to allow the selection circuit 8 to select an output of an averaging circuit 7.

Description

[Detailed Description of the Invention] [Summary] Regarding an image processing circuit when binarizing a multi-level image, the purpose is to prevent interference fringes from occurring during the binarization process, and a multi-gradation 3×3 image processing circuit is used. a memory that stores a matrix image, a difference circuit that extracts a difference between a center pixel of the 3×3 matrix image and surrounding pixels, and a comparison circuit that compares the output of the difference circuit with a predetermined threshold; An emphasis circuit performs emphasis processing on the value of a central pixel in a 3x3 matrix image by referring to the values of surrounding pixels; It is comprised of an averaging circuit that performs averaging, and a selection circuit that receives the outputs of the emphasizing circuit and the averaging circuit, selects one of them based on the output of the comparator circuit, and outputs the selected one.

[Industrial Application Field] The present invention relates to an image processing circuit for binarizing a multivalued image.

With the spread of facsimiles, image scanners, etc., there is a demand for converting read multivalued images into binary images (white/black images). Image processing methods such as the dither matrix method and the error diffusion method have been proposed as binarization processing methods.
Halftone images cannot be processed beautifully either, and improvements in image processing are required.

[Prior Art] Conventional binarization processing methods generally convert dot images into binary level images using a dither matrix method.

[Problems to be Solved by the Invention] The halftone image itself is a binarized image, and since this binarized image is binarized using a dither matrix method with a certain periodicity, Interference fringes of halftone dots were generated, resulting in a decrease in image quality.

The present invention has been made in view of these problems, and an object of the present invention is to provide an image processing circuit that can prevent interference fringes from occurring during binarization processing (for example, when using the dither matrix method). It is an object.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. In the figure,
1.2 is a shift register that sequentially shifts input multivalued images; 3 is a memory that stores a multi-tone 3×3 matrix image created by the shift register 1.2; 4 is a memory that stores the 3×3 matrix image created by the shift register 1.2;
3 a difference circuit that extracts the difference between the center pixel of the matrix image and its surrounding pixels; 5 a comparison circuit that compares the output of the difference circuit 4 with a predetermined threshold; 6 the center pixel of the 3×3 matrix image; 7 is an averaging circuit that averages the value of the central pixel of the 3×3 matrix image by referring to the values of the surrounding pixels; Reference numeral 8 denotes a selection circuit which receives the outputs of the emphasizing circuit 6 and the averaging circuit 7) and selects and outputs one of them based on the output of the comparator circuit 5.

[Operation] A dense halftone image has strong periodicity, and when binarized, interference fringes such as moiré are likely to occur. On the other hand, if the density is low, there is no periodicity, so even if it is binarized, no interference fringes will be created. Focusing on these characteristics, for pixels with high density, the averaging circuit 7 averages the pixel values and outputs a pixel value with reduced periodicity, and for pixels with low density, it outputs a pixel value with less periodicity. The value of is emphasized by the emphasizing circuit 6 and output.

Comparison circuit 5 compares whether the pixel density is high or low.

By adopting such a circuit configuration, it is possible to eliminate the occurrence of interference fringes during binarization (during dither matrix processing).

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

The operation of the present invention will be explained in detail based on the principle diagram shown in FIG. An image signal (analog signal) read by a reading element (not shown) such as a COD is converted into a multivalued image (digital signal) by an A/D converter (not shown). This multivalued image is the multivalued image shown in FIG. This multivalued image is directly stored in the memory 3 and also stored in the shift register 1. The output of shift register 1 enters memory 3, and
It also enters the second shift register 2. As a result, memory 3
Value image data from multi-SO to 88 as shown in FIG. 2 will be stored in . As shown in the figure, it is a 3x3 matrix.

The difference circuit 4 reads image data from the 3×3 matrix memory 3, and calculates a differential value or a quadratic differential value with respect to the surrounding pixels around the pixel value SO of the center pixel. The output of the differential circuit 4 obtained in this manner is assumed to be Do.

The emphasis circuit 6 reads image data from the memo IJ 3,
Emphasis processing is performed centering on the pixel value SO of the center pixel. Letting the output of this emphasis circuit 6 be EO, EO is expressed, for example, by the following equation.

EO-9SO-ΣS i (1) That is, when the center pixel has a certain pixel value and the surrounding pixel values are small, the pixel value of the center pixel is emphasized.

Next, the averaging circuit 7 reads the image data from the memory 3 and performs averaging processing centering on the center pixel value SO. The output MO of the averaging circuit 7 is, for example, expressed by the following formula (%) (2) The differential output DO of the differential circuit 4 is sent to the comparator circuit 5.

Comparison circuit 5 outputs the difference manually.

and a predetermined threshold TO. Differential circuit 5
If DO>To, it is determined that the image has a large change between the center pixel value SO and the surrounding pixel values. In this case, since the pixel density is low in the area, no interference fringes will occur even if the area is binarized. Therefore, the comparison circuit 5 outputs a selection signal for selecting the output of the emphasis circuit 6 to the selection circuit 8. As a result, the selection circuit 8 outputs the output EO of the emphasis circuit 6.

Conversely, if DO<TO, it is determined that the image has a small change between the center pixel value SO and the surrounding pixel values. In other words, this is an area with high pixel density. If the pixel values of such a halftone dot image with a high pixel density are directly binarized, interference fringes will occur.

Therefore, the comparator circuit 5 uses the averaging circuit 7 for the selection circuit 8.
Outputs a selection signal that selects the output of. As a result, the selection circuit 8 outputs the output MO of the averaging circuit 7. A binarization circuit (for example, a dither matrix method circuit,
(not shown), no interference fringes are generated, so 2
The quality of the valued image can be improved.

FIG. 3 is a time chart showing processing when the pixel density is high. (a) is the halftone period of the original image. (b) shows a gray area that appears alternately with halftone dots/black in the original image (to the human eye, it looks about 50% gray on average). Here, the white pixel value is O1 and the black pixel value is 100.
It is shown in

In other words, it is shown in terms of concentration. For such original drawings,
If image data is taken in at a sampling period as shown in (c), the pixel values at the input device will be as shown in (d).

For example, in the case of the first sampling period 1, the ratio of black area A1 to white area A2 in the original image is 3:1. Therefore, the density of the captured image is 75.

If the density is determined in the same manner for each sampling period, a gray undulation will be obtained that changes from 75, 50, 25.75.50.

If this value is converted into a binary value as it is, gray mottling (interference fringes) will occur as described above. Therefore, as explained with reference to FIG. 1, in such a region, the comparator circuit 5 determines that the output DO of the difference circuit 4 is smaller than the threshold value To, that is, it is a region in which there are few gradation changes. As a result, the selection circuit 8 is instructed to select the output MO of the averaging circuit 7. The averaging circuit 7 performs calculation according to equation (2), and calculates (
Output pixel values as shown in e). In this averaging process, the pixel values are restored to their original density, and the periodicity is weakened. Therefore, halftone processing (
Even when performing binarization), accurate processing without interference fringes can be performed.

FIG. 4 is a time chart showing processing when the pixel density is low. (a) is the halftone period of the original image. (b) is the value of the original image, for example, the eyes or eyebrows of a human face, and is a part that is desired to be preserved in image processing. Here, the white pixel value is shown as 0, and the black pixel value is shown as 100. In other words, it is shown in terms of concentration. For such an original picture, (C
), the pixel values at the input device will be as shown in (d).

For example, in the case of the first sampling period 1, the ratio of white area A1 to black area A2 in the original image is 3:1. Therefore, the density of the captured image is 25.

Similarly, when the density is sequentially determined for each sampling period, it changes to 25, 50.00.0. If such pixel values are simply averaged, the pixel values will disappear. Therefore, since the output Do of the difference circuit 4 becomes larger than the threshold value To, the comparator circuit 5 determines that this is an area where the gradation change is large. As a result, the selection circuit 8 is instructed to select the output EO of the emphasis circuit 6 in order to emphasize the original image. The emphasizing circuit 6 performs calculation according to equation (1) and outputs a pixel value as shown in (e).

When this pixel value is binarized, it can be binarized without losing the information of the original image.

FIG. 5 is a diagram showing a specific example of the configuration of the differential circuit. In the figure, 11 to 14 are difference calculators.

For example, a ROM is used as these difference calculators. The difference calculator 11 receives the center pixel value So and the peripheral pixel value S4.
is entered, the difference calculator 12 receives the center pixel value SO and the peripheral pixel value S8, the difference calculator 13 receives the center pixel value SO and the peripheral pixel value S2, and the difference calculator 14 receives the center pixel value S.
It contains O and the surrounding pixel value S6. The relationship between the center pixel value SO and other peripheral pixel values is the same as in FIG. 2.

The outputs of the difference calculators 11 and 12 enter an adder 15, and the outputs of the difference calculators 13 and 14 enter an adder 16. The outputs of these adders 15 and 16 enter an adder 17. The operation of the circuit configured as described above will be explained as follows.

The difference calculator 11 receives the center pixel value SO and the peripheral pixel value S4, calculates l5o-941, and outputs a value according to the calculated value. Specifically, I5O-8 is installed in the difference calculator 11.
The values corresponding to 41 are stored in a ROM table, and the values corresponding to the difference between SO and 84 are immediately output. The situation during this period is the same for the other difference calculators 12 to 14. The output of the adder 15 becomes I5O-S41+I5O-881, and the output of the adder 16 becomes 5o-321+t5O-861. Therefore, the adder 17 receiving these adder outputs
The output of is I5O-S41 + I5O-S81 +I5O
-821+I5O-S6. This value becomes the output Do of the differential circuit 4.

In other words, the difference circuit shown in the figure outputs a value larger than the threshold To when the difference between the center pixel value SO and the surrounding pixel values is large, and when the difference between the center pixel value SO and the surrounding pixel values is small. A value smaller than the threshold TO is output.

FIG. 6 is a diagram showing a specific example of the configuration of the comparator circuit 5. 2
1 is a register that holds the threshold value To given from the CPU, 22 is the output from the register 21 as the threshold value To,
The output from the differential circuit.

This is a comparator that compares these two values.

In the circuit configured in this way, the comparator 22
If >TO, set “11”; if DO<To, set “0”
The output of the comparator 22 is input to the selection circuit 8 (see FIG. 1) as a selection signal.
When O>TO, the pixel density is low, so the output of the emphasizing circuit 6 is selected; when Do<TO, the pixel density is high, so the output of the averaging circuit 7 is selected.

As a result of the signal outputted in this way being binarized using a dither matrix, even if the pixel density of the halftone dots is high, the image is averaged and has no periodicity, and is binarized, so there is no interference. A binarized image (halftone image) without stripes is obtained.

[Effects of the Invention] As described above in detail, according to the present invention, gray areas with little change such as the background of a halftone image (a photographic image of a newspaper, etc.) are converted to the original continuous gray level. At the same time, it is possible to perform processing that preserves the contrast (resolution) in areas with large changes such as faces. Even when the multivalued image thus obtained is binarized, a high quality image free of interference fringes can be obtained, which greatly contributes to improving the performance of image reading devices (facsimiles, image scanners).

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a diagram showing multivalued image data stored in memory, Fig. 3 is a time chart showing processing when the pixel density is high, and Fig. 1114 is a diagram showing the processing when the pixel density is high. FIG. 5 is a diagram showing a specific example of the configuration of the differential circuit; FIG. 6 is a diagram showing a specific example of the configuration of the comparison circuit. In FIG. 1, 1.2 is a shift register, 3 is a memory, 4 is a differential circuit, 5 is a comparison circuit, 6 is an emphasis circuit, 7 is an averaging circuit, and 8 is a selection circuit.

Claims (1)

[Claims] Memory (3) for storing a multi-gradation 3×3 matrix image
and a difference circuit (4) that extracts the difference between the center pixel of the 3×3 matrix image and the surrounding pixels, and the difference circuit (4).
a comparison circuit (5) that compares the output of the 3x3 matrix image with a predetermined threshold; and an emphasis circuit (6) that performs emphasis processing on the value of the central pixel of the 3×3 matrix image by referring to the values of surrounding pixels; an averaging circuit (7) that averages the value of the central pixel of the 3×3 matrix image by referring to the values of surrounding pixels; and receiving the outputs of the emphasizing circuit (6) and the averaging circuit (7); An image processing circuit comprising a selection circuit (8) that selects and outputs one of the outputs of the comparison circuit (5).