JPH03289783A - Recording disk reproducing device - Google Patents

Abstract

PURPOSE:To complete initialization before a spindle motor control system is set at a stationary state and to accelerate rise when reproduction is started by performing the initial setting of the readout address of a variable delay means by using the reference synchronizing signal of the spindle motor control system. CONSTITUTION:The initial setting of the readout address pointer 51 of the variable delay means 41 is performed by using the output of a reference synchronizing signal generation circuit 35 in the spindle motor 39 control system. Therefore, phase difference between a write address pointer 50 and the readout address pointer 51 can be kept in a horizontal scanning period of 0.5 at average after the spindle motor 39 control system is set at the stationary state even when the initial reset of the variable delay element 41 is performed before the spindle motor 39 control system is set at the stationary state. In such a way, the rise can be accelerated when the reproduction is started.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an initial reset operation of time axis correction means in a time axis correction circuit of a recording disc playback device such as a video disc player.

2. Description of the Related Art In recent years, recording disc playback devices have been widely applied in the consumer field as video disc players and the like.

In the future, it is desirable to introduce inexpensive and high-performance recording disc playback devices.

In recording disk playback devices, especially video disk players, unless the time axis correction circuit removes high-frequency jitter components caused by disc eccentricity, the playback screen will not be colored or color unevenness will occur. A time axis correction circuit is required. In recent years, time base correction circuits using digital variable delay elements (FIFOs) have been introduced because digital elements such as memories are available at low cost.

Hereinafter, an example of the above-mentioned conventional recording disk reproducing apparatus will be explained with reference to the drawings, taking a video disk player as an example.

FIG. 4 is a block diagram showing the configuration of a conventional recording disk reproducing apparatus. In the figure, 1 is a video disk, 2 is a pickup, 3 is a video signal demodulation circuit, 4 is a horizontal synchronization separation circuit, 6 is a reference synchronization generation circuit, 6 is a first phase comparator,
7 is a first loop filter, 8 is a spindle driver,
9 is a spindle motor, 1o is an A/D converter, 11 is a digital variable delay element, 12 is a D/A converter, 13 is a terminal, 14 is a color burst separation circuit, 15 is a second phase comparator, 16 is a The second loop filter, 17 is the VCO (
18 is a frequency divider, 19 is a fixed frequency oscillator, 2o is a write address pointer,
21 is a read address pointer, and 22 is an address pointer reset circuit.

The operation of the conventional recording disk reproducing apparatus configured as described above will be explained below.

In FIG. 4, a pickup 2 converts signals recorded on a video disc 1 into electrical signals.

The output of the pickup 2 is demodulated into a composite video signal by a video signal demodulation circuit 3, converted into an 8-bit digital signal by an A/D converter 10, and input to a digital variable delay element 11.

At the same time, the composite video signal is input to the horizontal sync separation circuit 4. The horizontal synchronization separation circuit 4 extracts only the horizontal synchronization signal from the input video signal and inputs it to the first phase comparator 6. The output of the reference synchronization generation circuit 6 is input to the other input of the first phase comparator 6 . 1st
The output of the phase comparator e is input to the first loop filter 7, the output of the first loop filter 7 is input to the motor drive circuit 8, and the spindle motor 9 is rotated by the output of the motor drive circuit 8. . That is, the reference synchronization generation circuit 5
The rotational speed of the spindle motor 9 is controlled so that the generated signal and the output of the horizontal synchronization separation circuit 4 are in phase. now,
If the oscillation frequency of the reference synchronization generation circuit 6 is set to the horizontal scanning frequency of the regular video signal, the spindle motor 9 is controlled so that the output of the video signal demodulation circuit 3 becomes the frequency of the regular video signal. . However, the output of the video signal demodulation circuit 3 is
It contains high-frequency jitter components that cannot be sufficiently removed by controlling the spindle motor 9 alone, and cannot be reproduced as is on a television receiver.

Therefore, a digital variable delay element 11 is used to remove the jitter component.

The output of the A/D converter 1o is sent to the color burst separation circuit 1.
4 is input. The color burst signal circuit 14 extracts only a color burst signal based on the input digital video signal and inputs it to the second phase comparator 15. Second
The output of the splitter 18 is input to the other input of the phase comparator 15. The output of the second phase comparator 15 is input to a second loop filter 16, and the output of the second loop filter 16 is input as a control input to the VCO 17, thereby changing the oscillation frequency of the VCO 17.

The output of VCOl 7 is used as a write clock for digital variable delay element 11 and write address pointer 2o. The output of the fixed frequency oscillator 19 is used as a read clock for the digital variable delay element 11 and as a read address pointer 21. Therefore, in the digital variable delay element 11, the input signal is vC0
A time delay corresponding to the difference between the oscillation frequency of the fixed frequency oscillator 17 and the oscillation frequency of the fixed frequency oscillator 19 is outputted. Now, the oscillation frequency of the fixed frequency oscillator 19 is set to four times the burst signal of the regular video signal, the median value of the oscillation frequency of the VCO 7 is also set to be approximately equal to the oscillation frequency of the fixed frequency oscillator 19, and the division If the ratio is set to 1/4, the digital variable delay element 11 is written with a write lock synchronized with the jitter of the input burst, and read out with a fixed clock.
1 can remove jitter. Since the control characteristics of the VCOl 7 can be determined purely electrically, it can be controlled up to a high frequency range, and therefore the spindle motor 9
It is possible to suppress high-frequency jitter that could not be removed by conventional control.

Therefore, the output of the terminal 13 can be reproduced as is on a television receiver.

Next, the operation of the digital variable delay element 11 will be explained.

The write clock of the digital variable delay element 11 is inputted with the write clock, that is, the output of the VCO17.

The output of the fixed frequency oscillator 19 is input to the read clock. The digital variable delay element 11 has 8-bit input/output, and can independently control write and read addresses. The write address pointer 2o counts the write clock, increments sequentially, and is reset when a certain set value is reached. The output of A/D conversion 810 is stored in the memory cell specified by write address pointer 2o in digital variable delay element 11. Information stored in the memory cell designated by the read address pointer 21 in the digital variable delay element 11 is output to the D/A converter 12.

The read address pointer 21 counts the read clock, increments sequentially, and is reset when a certain set value is reached.

FIG. 6 is a diagram showing the operation of the address pointer reset circuit of the digital variable delay element in the conventional recording disc reproducing apparatus. FIG.

Now, set values to be reset for both the write address pointer 20 and the read address pointer 21 are equal to values corresponding to one horizontal scanning time of the input video signal,
Furthermore, in the initial setting, as shown in FIG. 5, the address pointer reset circuit 22 outputs a reset command to the write address pointer 20, and after 0.5 horizontal scanning time has elapsed since the write address pointer 2° starts operating. When a reset command is output to the read address pointer 21 so that the read address pointer 21 starts operating, the operation of each address pointer becomes as shown in FIG. In the figure, solid lines indicate changes in the value of the read address pointer 21, and broken lines indicate changes in the value of the write address pointer 20.

The actual values of both address pointers are digital values, so they take discrete values, but here they are shown consecutively for ease of viewing. The write clock is a clock generated by the VCO 17, and its frequency changes depending on the jitter of the output of the A/D converter 1o. On the other hand, since the read clock is a constant frequency clock generated by the fixed frequency oscillator 19, the initial setting shown in FIG. 6 is performed after the spindle motor control reaches a steady state. You only need to do it once.

This video signal reproducing device can reproduce up to ±O, S horizontal scanning time jitter.

FIG. 7 shows the operation when initial setting is performed before the spindle motor control reaches a steady state.

As is clear from the figure, if initial settings are made before the phase is locked to the spindle motor reference phase, the synchronization phase of the signal input to the digital variable delay element will shift after the steady state has been reached. Therefore, the difference between the write address and the read address does not become 0.6 horizontal scanning time on average, and the jitter margin decreases.

Problems to be Solved by the Invention In a recording disk reproducing apparatus having such a configuration, in the initial setting, the address pointer reset circuit outputs a reset command to the write address pointer, and 0.5 horizontal scan is performed after the write address pointer starts operating. After the time has elapsed, a reset command is output to the read address pointer and the read address pointer starts operating, so if the initial settings are made before the phase is locked to the spindle motor reference phase, the steady state will not occur. After transition, the synchronization phase of the signal input to the digital variable delay element will shift, and the difference between the write address and read address will not be 0.6 horizontal scanning time on average, and the jitter margin will decrease. It was necessary to initialize the spindle motor after it reached a steady state.

Therefore, the time required for the spindle motor to start reproducing information correctly from a stopped state is the sum of the time required for the spindle motor control system to reach a steady state and the time required for initial settings. There was a problem in that the start-up was slow at the start, and it took too long to reach the playback state.

In view of the above-mentioned problems, the present invention makes it possible to complete initial settings before both the spindle motor (J) systems reach a steady state, and provides a recording disk reproducing device that has a faster start-up at the start of reproduction. It's true.

Means for Solving the Problems In order to solve the above problems, the recording disk reproducing apparatus of the present invention includes a spindle motor for giving the recording disk appropriate rotation for reading recorded signals, and a pickup that converts the received signal into an electrical signal;
a demodulator that demodulates an information signal including a synchronization signal included in the pickup output, a synchronization separation circuit that extracts the synchronization signal from the demodulator output, a reference synchronization generation circuit that generates a reference synchronization signal, and a synchronization separation circuit output; A phase comparator that performs a phase comparison with a reference synchronization; a motor drive circuit that converts the output of the phase comparator into a signal suitable for driving a spindle motor; a first clock generating means; and a second clock generating means. ,
a write address instruction circuit, a read address instruction circuit, and the information signal in synchronization with a first clock to store information at an address specified by the write address instruction circuit, and in synchronization with a second clock; A variable delay means for outputting information stored at an address designated by the read address designation circuit and a write address designation circuit are reset at a time synchronized with a synchronization signal input to the variable delay element, and the read address designation circuit is reset. , is characterized by having an address reset circuit that performs the reset at a time synchronized with the reference phase.

In the present invention, according to the above-described configuration, the read address of the variable delay means is initially set using the reference synchronization signal of the spindle motor control system, so that the system spindle control system can be set in a steady state before the system spindle control system reaches a steady state. Even after the initial reset of the variable delay element, the difference between the write address and the read address can be maintained at 0.5 horizontal scanning time on average after the spindle motor control system reaches a steady state, and the difference at the start of playback can be maintained at 0.5 horizontal scanning time. This is something that can make the process much faster.

Embodiment Hereinafter, a recording disc reproducing apparatus according to an embodiment of the present invention will be described with reference to the drawings, taking as an example a video disc player that operates.

FIG. 1 is a block diagram showing the configuration of a recording disk reproducing apparatus according to the present invention. In the figure, 31 is a video disc, 32
is a pickup, 33 is a video signal demodulation circuit, 34 is a horizontal synchronization separation circuit, 36 is a reference synchronization generation circuit, 36 is a first phase comparator, 37 is a first loop filter, 38 is a spindle driver, and 39 is a spindle motor , 4o1d
A/Dl & converter, 41 is a digital variable delay element, 42
is a D/A converter, 43 is a terminal, 44 is a color burst separation circuit, 46 is a second phase comparator, 46 is a second loop filter, 47 is a VCO (pressure controlled variable frequency oscillation circuit), 48 is a 49 is a fixed frequency oscillator, 6o is a write address pointer, 61 is a read address pointer, and 62 is an address pointer reset circuit.

The operation of the recording disk reproducing apparatus according to one embodiment of the present invention constructed as described above will be explained below.

In FIG. 1, a pickup 32 converts signals recorded on a video disc 31 into electrical signals. The output of the pickup 32 is demodulated into a composite video signal by a video signal demodulation circuit 33, converted into an 8-bit digital signal by an A/D converter 40, and input to a digital variable delay element 41. At the same time, the composite video signal is input to the horizontal sync separation circuit 34. The horizontal synchronization separation circuit 34 extracts only the horizontal synchronization signal from the input video signal and inputs it to the first phase comparator 36 . The output of the reference synchronization generation circuit 35 is input to the other input of the first phase comparator 36 . The output of the first phase comparator 36 is input to the first loop filter 37, the output of the first loop filter 37 is input to the motor drive circuit 38, and the output of the motor drive circuit 38 is used to drive the spindle motor 3.
9 rotates. That is, the rotation speed of the spindle motor 39 is controlled so that the phase difference between the signal generated by the reference synchronization generation circuit 35 and the output of the horizontal synchronization separation circuit 34 is constant. If the reference synchronization generation circuit 36 is now oscillated, the spindle motor 39 is controlled so that the output of the video signal demodulation circuit 33 has the frequency of the regular video signal. However, the output of the video signal demodulation circuit 33 is
Due to the eccentric nut 1, a high frequency jitter component that cannot be sufficiently removed by controlling the spindle motor 39 alone is included, and the image cannot be reproduced on a television receiver as it is.

Therefore, a digital variable delay element 41 is used to remove the jitter component.

The output of the A/D converter 4o is sent to the color burst separation circuit 4.
4 is input. The color burst separation circuit 44 extracts only the color burst signal from the input digital video signal and inputs it to the second phase comparator 46 . Second
The output of the divider 48 is input to the other input of the phase comparator 46 . The output of the second phase comparator 46 is input to the second loop filter 46, and the output of the second loop filter 46 is input as a control input to the VCO 47 to change the oscillation frequency of the VCO 47.

The output of Eo 47 is used as a write clock for digital variable delay element 41 and write address pointer 6o. The output of the fixed frequency oscillator 49 is used as a read clock for the digital variable delay element 41 and a read address pointer 61. Therefore, in the digital variable delay element 41, the input signal is transferred to the VCO 47.
A time delay corresponding to the difference between the oscillation frequency of the fixed frequency oscillator 49 and the oscillation frequency of the fixed frequency oscillator 49 is outputted. Now, the oscillation frequency of the fixed frequency phase oscillator 49 is set to four times the burst signal of the regular video signal, and the median value of the oscillation frequency of the VCO 47 is also set to be approximately equal to the oscillation frequency of the fixed frequency oscillator 49. If you set the division ratio to 1/4,
The digital variable delay element 41 is written with a write clock synchronized with the jitter of the input burst, and read out with a fixed clock.
1 can remove jitter. Since the control characteristics of the VCO 47 can be determined purely electrically, it is possible to control up to a high frequency range, and therefore it is possible to suppress high frequency jitter that cannot be removed by controlling the Novi 2 motor 39.

Therefore, the output of the terminal 43 can be reproduced as is on a television receiver.

Next, the operation of the digital variable delay element 41 will be explained.

A write clock, that is, the output of the VCO 47 is input to the write clock input terminal of the digital variable delay element 41 . The output of the fixed frequency oscillator 49 is input to the read clock input terminal. The digital variable delay element 41 has 8-bit input/output, and can independently control write and read addresses. The write address pointer 6o counts the write clock, increments sequentially, and is reset when a certain set value is reached. A
The output of the /D converter 4o is a digital variable delay element 41.
The data is stored in the memory cell designated by the write address pointer 6o. The data stored in the memory cell specified by the read address pointer 61 in the digital variable delay element 41 is input to the D/A converter 42 . The read address pointer 61 counts the read clock, increments sequentially, and is reset when a certain set value is reached.

FIG. 2 is a diagram showing the operation of the address pointer reset circuit of the digital variable delay element in a recording disc reproducing apparatus according to an embodiment of the present invention, and FIG. FIG. 3 is a diagram showing address operation of a digital variable delay element.

Now, the spindle motor control system consists of the horizontal synchronization separation circuit 34
There is a phase difference of 18 between the output of
It shall be controlled so that the value becomes 00. Also, a write address pointer 5o and a read address pointer 6
1, both set values to be reset are equal to values corresponding to one horizontal scanning time of the input video signal, and furthermore, in the initial setting, as shown in FIG. A reset command is output to the write address pointer 60 in synchronization with the output of the reference synchronization generating circuit 36, and then a reset command is output to the read address pointer 61 in synchronization with the output of the reference synchronization generating circuit 36, Q≦. When the address pointers start operating, the operations of each address pointer become as shown in FIG.

In the figure, a solid line indicates a change in the value of the read address pointer 61, and a broken line indicates a change in the value of the write address pointer 5o.
shows the change in value. The actual values of both address pointers are digital values, so they take discrete values, but here they are shown consecutively for ease of viewing. The write lock is a clock generated by VCOs7, which is
The frequency changes depending on the jitter of the output of the D converter 40. On the other hand, the read clock is a fixed frequency oscillator 49.
Since this is a clock with a constant frequency that oscillates, the delay time can be controlled in the digital variable delay element 41, and the jitter contained in the input data signal can be removed and output.

The initial reset shown in FIG. 2 only needs to be performed once.

Furthermore, as shown in FIG. 2, even if the initial setting is performed before the spindle motor control reaches a steady state, the read address pointer 61 operates in synchronization with the output of the reference synchronization generating circuit, so the spindle motor After the control enters the steady state, the write address pointer 6o
The phase difference between the read address pointer 61 and the read address pointer 61 is 0.6 on average.
horizontal scanning time. In this video signal reproducing device, ±0.
Jitter up to 5 horizontal scanning times can be reproduced.

As described above, the recording disk reproducing apparatus according to the embodiment of the present invention includes a video disc, a pickup, a video signal demodulation circuit, a horizontal synchronization separation circuit, a reference synchronization generation circuit, and a first phase comparator. , a first loop filter, a spindle driver, a spindle motor, an A/D converter,
A digital variable delay element, ])/A converter, a terminal, a color burst separation circuit, a second phase comparator, a second loop filter, a VCO (voltage controlled variable frequency oscillator), and a branch By providing a fixed frequency oscillator, a write address pointer, a read address pointer, and an address pointer reset circuit, even if the initial setting is a spindle mode, the read address pointer operates in synchronization with the output of the reference synchronization generator circuit. Therefore, it is possible to provide a video disc player in which the phase difference between the write address pointer and the read address pointer is always 0.5 horizontal scanning time on average after the spindle motor control enters a steady state.

In this embodiment, the spindle motor control system has a phase difference of 1 between the output of the horizontal synchronization separation circuit and the output of the reference synchronization generation circuit.
However, if this phase difference is other than 18o0, the difference between the write address and the read address is controlled to be 0.5 horizontal scanning time on average. , the time at which the address pointer reset circuit resets the write or read address pointer may be delayed.

Although the present invention has been described using a video disc player as an example, the present invention can be similarly applied to other recording disc playback devices.

Effects of the Invention As described above, the recording disk reproducing apparatus of the present invention includes a spindle motor for giving the recording disk appropriate rotation for reading out the recorded signals, and an electrical system for transmitting the signals recorded on the recording disk. A pickup that converts the information signal into a signal, a demodulator that demodulates the information signal including the synchronization signal contained in the pickup output, a synchronization separation circuit that extracts the synchronization signal from the demodulator output, and a reference synchronization generation circuit that generates the reference synchronization signal. , a phase comparator that performs a phase comparison between the output of the synchronization separation circuit and a reference synchronization, a motor drive circuit that converts the output of the phase comparator into a signal suitable for driving the spindle motor, and a first clock generation means; a second clock generation means, a write address instruction circuit, a read address instruction circuit, and the information signal to store information at an address specified by the write address instruction circuit in synchronization with the first clock;
A variable delay means outputs the information stored at the address indicated by the read address instruction circuit in synchronization with a second clock, and resets the write address instruction circuit at a time synchronized with the synchronization signal input to the variable delay element. By providing an address point circuit that resets the reading ratio address instruction circuit at a time synchronized with the reference phase, the read address of the variable delay means is initially set using the reference synchronization signal of the spindle motor control system. Especially yoshi? Even if the initial reset of the variable delay element is performed before the spindle control system reaches a steady state, the difference between the write address and the read address will be maintained at 0.6 horizontal scanning time on average after the spindle motor control system reaches a steady state. This makes it possible to speed up the start-up at the start of playback.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a recording disk reproducing apparatus according to an embodiment of the present invention, and FIG. 2 shows the operation of an address pointer reset circuit of a digital variable delay element in a recording disk reproducing apparatus according to an embodiment of the present invention. A waveform diagram, FIG. 3 is a waveform diagram showing the operation of the address pointer reset circuit of the digital variable delay element in the recording disc reproducing apparatus of the address of the digital variable delay element of the recording disc reproducing apparatus according to an embodiment of the present invention, FIG. 7 is a diagram showing the address operation of the digital variable delay element of a conventional recording disk reproducing device, and FIG. 7 is a waveform diagram showing the operation when initial setting is performed before the spindle motor control reaches a steady state. be. 31...Video disk, 32...Pickup, 33...Video signal demodulation circuit, 34
......Horizontal synchronization separation circuit, 36...Reference synchronization generation circuit, 36...First phase comparator, 3
7...First loop filter, 38...
・Nubindle driver, 39...Spindle motor, 40...A/D converter, 41...
・Digital variable delay element, 42... D/A converter, 43... terminal, 44... color burst separation circuit, 46... second Phase comparator, 46... Second roof reilter, 47...
...VCO (voltage controlled variable frequency oscillator circuit, 48...
...Frequency divider, 49...Fixed frequency oscillator,
6o...Write address pointer, 61...
...Read address pointer, 62...
Address pointer reset circuit.

Claims (1)

[Claims] A spindle motor for giving the recording disk appropriate rotation to read out the recorded signals, a pickup for converting the signal recorded on the recording disk into an electrical signal, and information including a synchronization signal contained in the pickup output. A demodulator that demodulates a signal, a sync separation circuit that extracts a sync signal from the demodulator output, a reference sync generation circuit that generates a reference sync signal, and a phase comparison between the output of the sync separation circuit and the reference sync. a phase comparator, a motor drive circuit that converts the output of the phase comparator into a signal suitable for driving the spindle motor, first clock generation means, second clock generation means, and a write address instruction circuit; A read address instruction circuit stores information at an address specified by the write address instruction circuit in synchronization with a first clock, and outputs the read address instruction in synchronization with a second clock. a variable delay means for outputting information stored at an address designated by the circuit; and resetting the write address designation circuit at a time synchronized with a synchronization signal input to the variable delay element; and resetting the read address designation circuit. , and an address reset circuit that performs the reset at a time synchronized with the reference phase.