JPH03283809A - Attenuator - Google Patents

Abstract

PURPOSE:To prevent an excessive signal applied to an output terminal from being transmitted to an internal circuit by separating a relay in an output level adjusting circuit in the last stage into the input side and the output side and individually controlling them by a relay control means. CONSTITUTION:An output level adjusting circuit 201 in the final stage consists of output level control relays 61 and 62 independent of each other and a balanced pi-type attenuator circuit 9, and relays 61 and 62 are individually controlled by relay drivers 65 and 64. Control signal J and K which individually control relay drivers 64 and 65 are the output signals of a relay control means 63 for which a detection signal E and control signals G and H are inputted. The relay is divided to the input-side relay 61 and the output-side relay 62 and are controlled by the relay control means 63 independently of each other in such a manner, thereby, the internal circuit is automatically protected even when the excessive signal is applied.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an attenuation device for a signal generator used as a measurement signal source in electronic measurement.

BACKGROUND OF THE INVENTION FIG. 4 shows the structure of a conventional attenuator for a balanced output signal generator. In FIG. 4, 1 is a balanced output type signal generating circuit, and its output signals A and B have the following relationship: A=-8 (1). Signal generation circuit 1 is connected to output level adjustment circuit 100 via resistors 2 and 3. The output level adjustment circuit 100 is composed of an output level control relay 4.5 and a balanced π-type attenuation circuit 6, and an output level adjustment circuit with a similar configuration may be used depending on the required output level range and resolution of this device. are connected in series in multiple stages. In FIG. 4, the intermediate output level adjustment circuit is omitted, and only the first stage output level adjustment circuit 100 and the final stage output level adjustment circuit 200 are illustrated. Therefore, the output level adjustment circuit 200 at the final stage is similarly composed of an output level control relay 7.8 and a balanced π-type attenuation circuit 9, and the output level control relay 7.8 is connected to the output signal cutoff relay 12. It is connected to the. A resistor 10.11 is selectively connected to the output signal cutoff relay 12, and the output terminals 14, 15゜1 are connected via the internal circuit protection relay 13.
6. A reverse input signal detection circuit 17 is connected to the output terminals 14 and 15, and its detection signal E is supplied to a relay driver 18. Relay 4.5, 7, 8.1
2 is controlled by a relay driver 19°20.21 which receives control signals F, G, and H, respectively, and relay 1
3 is controlled by a relay driver 18.

FIG. 5 shows the configuration of the reverse input detection circuit 17.

In FIG. 5, one end of the resistor 31 is connected to the output terminal 14 in FIG. The other end of the resistor 31 is connected to the anode and cathode of a grounding resistor 32 and detection diodes 33 and 37, respectively. diode 33
The cathode of is connected to one terminal of a detection capacitor 34, a resistor 35, and a comparator 36. Similarly, the anode of the diode 37 is connected to a detection capacitor 38 and a resistor 39.
and a child terminal of the comparator 40. Further, one end of the resistor 41 is connected to the other output terminal 15 of the device in FIG. The other end of the resistor 41 is connected to the anode and cathode of a grounding resistor 42 and detection diodes 43 and 47, respectively. diode 43
The cathode of is connected to one terminal of a detection capacitor 44, a resistor 45, and a comparator 46. Similarly, the anode of the diode 47 is connected to a detection capacitor 48 and a resistor 49.
and a child terminal of the comparator 50. The voltage dividing point of resistor 51.52 connected between +V and ground is the + terminal of comparator 36.46, and the voltage dividing point of resistor 53.54 connected between -V and ground is: They are connected to one terminal of comparators 40 and 50, respectively. Comparators 36, 40.
The output of 46.50 is pulled up by a resistor 55 and supplied as a detection signal E to the relay driver 18 in FIG.

Next, the operation of the conventional example will be explained. The reverse input signal detection circuit 17 shown in FIG.
The positive peak is detected by the diode 37, the capacitor 38, and the resistor 39. The detected positive peak value and the comparison voltage determined by the resistor 51.52 are compared by the comparator 36, and if the detected positive peak value is higher than the comparison voltage, the output E of the comparator 36 is
becomes 0. In addition, the detected negative peak value and the resistor 53
．． 54 is compared with the comparison voltage determined by the comparator 40, and if the detected negative peak value is lower than the comparison voltage,
The output E of the comparator 40 becomes 0. Similarly, the signals are subjected to voltage division, detection, and comparison processing. Therefore, normally the detection signal E is +V, but if an excessive signal is mistakenly applied to the output terminal 14 or 15 in FIG. 4, the detection signal E becomes O. In FIG. 4, when the detection signal E becomes O, the relay 13 opens and the output terminal 14.
The signal applied to relay 15 is not transmitted to the circuits before relay 12. Also, at this time, the resistance 31.4 in FIG.
By setting 1 to a sufficiently high value, damage to the reverse input signal detection circuit 17 itself due to excessive signals can be prevented.

Therefore, even if an excessive signal is accidentally applied to the output terminals 14, 15, the internal circuit of the device will not be damaged.

In FIG. 4, if no excessive signal is applied to output terminals 14 and 15, control signals F and G are set to 0, and H is set to +V,
Signals A and B from the signal generation circuit 1 are supplied to output terminals 14 and 15 via resistors 2 and 3. In this state, the output level of this device is the maximum value, and the output impedance is the sum of resistors 2 and 3. Here, in a balanced output type signal generator, the values of resistors 2 and 3 are usually made equal. In other words, the value of resistor 2 is R^[Ω], and the value of resistor 3 is R
When a[Ω] is assumed, the output impedance R[Ω] is as follows: R=R^+RB=2 R^ (2). From this state, if the output level control signals F and G are set to +V,
A balanced π-type attenuation circuit 6.9 is inserted between resistor 2.3 and output terminals 14 to 16, and the output level of this device is attenuated, but the output impedance is maintained at twice the value of resistor 2. . Therefore, output level adjustment circuits similar to the output level adjustment circuit 100 consisting of the relay 4.5 and the balanced π-type attenuation circuit 6 are connected in multiple stages between the resistors 2 and 3 and the relay 12, and each control By combining signals,
The output impedance is constant and any output level can be obtained.

Furthermore, when the output signal cutoff control signal H is set to O, the signals A and B of the signal generation circuit 1 are not transmitted to the output terminals 14 and 15, and only the resistor 10.11 is connected to the output terminal 14.15. become. At this time, the values of resistors 10 and 11 are set to resistor 2
If it is set equal to the value of , the output impedance will remain constant even if the output signal of this device is cut off.

In this way, the conventional balanced output type signal generator attenuation device also includes the output signal cutoff relay 12 and the internal circuit protection relay 13, so that the output terminal 14
, 15.16, the output impedance can be kept constant, and even if an excessive input is accidentally applied to the output terminals 14.15,
Can automatically protect internal circuits.

Problems to be Solved by the Invention However, in such a conventional attenuation device for a balanced output type signal generator, relays 4, 5, 7 for output level control are
．． In addition to 8, it was necessary to add two relays: an output signal cutoff relay 12 and an internal circuit protection relay 13. Therefore, the number of relays increases, resulting in problems such as decreased reliability, increased cost, and increased occupied space.

The present invention solves these conventional problems,
It is an object of the present invention to provide an excellent attenuation device for a balanced output signal generator that has the same functions as conventional devices without adding an output signal cutoff relay and an internal circuit protection relay.

Means for Solving the Problems In order to achieve the above object, the present invention has a structure in which the relay in the final stage output level adjustment circuit is separated into an input side and an output side, and these are individually controlled by a relay control means. By doing so, all of the output level adjustment operation, output signal cutoff operation, and internal circuit protection operation can be performed.

action The present invention has the following effects due to the above configuration.

That is, in a normal state, the two relays in the output level adjustment circuit at the final stage are brought into an interlocked state by the relay control means and operate as an output level adjustment circuit. Further, when cutting off the output signal, each of these relays operates independently to cut off the signal of the signal generation circuit from the output terminal. Furthermore, if an excessive signal is accidentally applied to the output terminal, each of these relays operates independently to prevent the excessive signal applied to the output terminal from being transmitted to the internal circuit.

Embodiment FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, the same elements as those in the conventional example shown in FIG.
Output level control relay 4゜5, balanced π type attenuation circuit 6, 9
, output terminals 14, 15.16, reverse input signal detection circuit 17
, the relay driver 19 has the same configuration and operation as the conventional example shown in FIGS. 4 and 5, and receives the control signal F.
.

The control of G and H is also equivalent.

The final stage output level adjustment circuit 201 is composed of independent output level control relays 61 and 62 and a balanced π-type attenuation circuit 9, and the relays 61 and 62 are individually controlled by relay drivers 65 and 64. . The control signal J, which controls the relay drivers 64 and 65 individually, is an output signal of the relay control means 63 which receives the detection signal E and the control signals G and H as inputs.

FIG. 2 shows an embodiment of the relay control means 63. In FIG. 2, the NAND circuit 71 receives the detection signal E
and the control signal H as human power, and the NOT circuit 72 uses the output of the NAND circuit 71 as human power. The NOT circuit 73 receives the control signal G as an input. The NAND circuit 74 is the NOT circuit 7
2.73 is input, and the NAND circuit 75 receives the control signal G and the output of the NOT circuit 72 as input. NAND
The circuit 76 inputs the detection signal E and the output of the NAND circuit 74, and the NAND circuit 77 receives the detection signal E,! -NAN
The output of the D circuit 75 is input. NOT circuit 78 is NA
The output of the ND circuit 76 is input, and the output signal J of the NOT circuit 78 and the output signal of the NAND circuit 77 serve as control signals for the relay drivers 64 and 65 in FIG.

Next, the operation of the above embodiment will be explained. A truth table for the relay control means 63 shown in FIG. 2 is shown in FIG. Third
In the figure, the "1" part indicates +V. In FIG. 1, if an excessive input is mistakenly applied to the output terminal 14 or 15, the detection signal E of the reverse input signal detection circuit 17 becomes O, as described in the description of the conventional example. Detection signal E is 0
Then, from FIG. 3, the output signal J of the relay control means 63
becomes O, and K becomes +V. Therefore, the relay 61 is connected to the inner contact and the relay 62 is connected to the outer contact, and the excessive signal applied to the output terminal 14.15 is not transmitted to the internal circuits other than the reverse input signal detection circuit 17. Damage to the circuit can be prevented.

When no excessive input is applied to the output terminals 14 and 15, the detection signal E becomes +V. In this state, control signals F, G
When is set to O and H is set to +V, the output signal J of the relay control means 63 becomes 0 as shown in FIG. Therefore, the relays 4.5, 61.62 are all connected to the outer contacts, and the signals A, B of the signal generation circuit 1 are supplied to the output terminal 14.15 via the resistor 2.3. In this state, the output signal of this device is at its maximum value, and the output impedance is the sum of resistors 2 and 3, that is, twice the value of resistor 2.

Next, as in the conventional case, when the output level control signals F and G are set to +V from this state, the resistor 2.3 and the output terminal 14
, 15 and 16 are inserted, and the output level is attenuated while keeping the output impedance of the device constant. Therefore, between the resistor 2.3 and the relay 61, the relays 4 and 5 and the balanced π-type attenuation circuit 6
By connecting circuits equivalent to the output level adjustment circuit 100 consisting of the following in multiple stages and combining their respective control signals, it is possible to set an arbitrary output level without changing the output impedance.

When the output signal cutoff signal H is set to O in the above-mentioned state, the output signal J of the relay control means 63 becomes +V and K as shown in FIG.
becomes O. Therefore, the relay 61 is connected to the outer contact, and the relay 62 is connected to the inner contact. Therefore, the signals A and B of the signal generating circuit 1 are not supplied to the output terminal 14.15, and only the balanced π-type attenuation circuit 9 is connected to the output terminal 14.15. At this time, the value of resistor 2 is R/2
[Ω], and the amount of attenuation of the balanced π-type attenuation circuit 9 is A[dB], then the “balanced π-type attenuation circuit 9 between the output terminals 14 and 15
The combined resistance value RT [Ω] of is obtained by the following equation (3).

K=10...(4) Above (
From equation 3), it can be seen that if the amount of attenuation is large, the combined resistance RT is approximately equal to the value of R. For example, the attenuation amount A is 20d
If the combined resistance value RT is calculated from equation (3) for B, it is as follows.

0 = 10 = 10 (5) That is, the combined resistance value of the balanced π-type attenuation circuit 9 deviates by only +2% with respect to the twice the value of the resistance 2. Therefore, even if the output signal of this device is cut off, the output impedance can be kept almost constant.

According to the above embodiment, the final stage output level control relay, which has conventionally operated, is divided into the input side relay 61 and the output side relay 62, respectively, and these relays 61 and 62 are By independently controlling the control means 63, the output impedance of this device can be kept constant even if the conventionally required output signal cutoff relay and internal one-path protection relay are omitted, preventing accidental output. Even if an excessive signal is applied to the terminals 14 and 15, the internal circuit can be automatically protected.

Effects of the Invention As is clear from the above examples, the present invention has the following effects.

(1) Reliability is improved because the number of relays can be reduced compared to conventional devices.

(2) The number of relays can be reduced, contributing to lower prices.

[Brief explanation of the drawing]

Fig. 1 is a schematic block diagram of a damping device for a balanced output signal generator according to an embodiment of the present invention, Fig. 2 is a circuit diagram showing an embodiment of relay control means in the same device, and Fig. 3 is a circuit diagram of the same. FIG. 4 is a schematic block diagram of a conventional attenuation device for a balanced output signal generator, and FIG. 5 is a circuit diagram of a reverse input signal detection circuit in the conventional device. 1...Balanced output type signal generation circuit, 2.3...Resistor,
4.5, 61.62... Output level control relay 6.
9...Attenuation circuit, 14-16...Output terminal, 17...
- Reverse input signal detection circuit, 19, 64. 65... Relay driver, 63... Relay control means, 100...
First stage output level adjustment circuit, 201...Final stage output level adjustment circuit.

Claims (1)

[Claims] A final stage output that includes a balanced output type signal generation circuit, a multi-stage output level adjustment circuit connected in series to the signal generation circuit, and two independent relays to output a signal to the output terminal of the device. The output level is adjusted by individually controlling two relays: a level adjustment circuit, a reverse input signal detection circuit connected to the output terminal, and a final stage output level adjustment circuit connected to the output terminal. A damping device comprising relay control means for performing operation, output signal cutoff operation, and internal circuit protection operation, respectively.