JPH03283196A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the danger of the occurrence of a cut defect by constituting a line to be cut when a memory cell for redundancy is used instead of a memory cell used at regular time by means of plural fuses which are connected in serial. CONSTITUTION:Two fuses 8a and 8b connected in serial as the cut possible line are interposed between the gate of a PMOS transistor P2 forming a transmission gate 7c and a power line VDD, and an NMOS transistor N4 is interposed between the gate of an NMOS transistor N2 forming the transmission gate 7c and a ground line GND. If it is assumed that the occurrence rate of the cut defect of one fuse is alpha, the occurrence rate of the cut defect of the line where n-number of fuses 8a and 8b are connected in serial comes to be alpha<n>. In such a case, alpha<1, alpha<n> becomes smaller than alpha. Thus, the occurrence rate of the cut defect becomes small.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a semiconductor memory device that can be rescued by redundancy, and in particular, by cutting a predetermined line in the circuit and changing the internal structure of the circuit. In a semiconductor memory device in which a redundant memory cell is selected in place of a defective memory cell, cutting defects in the predetermined line can be reduced.

[Conventional technology]

RAM (Random Access Mea+or
Semiconductor memory devices such as y) are used for manufacturing memory cells and word lines.

After completing the bit line wiring, etc., a test is performed to see if the memory cells function normally. If even one memory cell in a semiconductor memory device is defective, the entire semiconductor memory device is determined to be defective.
In such a case, it would be extremely wasteful to discard the semiconductor memory device itself because it would also discard the normally operating memory cells.

Conventionally, redundant memory cells are built into a semiconductor memory device in advance, and if a defective memory cell is discovered during testing, a predetermined line in the circuit is cut and the internal structure of the circuit is removed. By changing the structure and creating a structure in which when a defective memory cell is accessed during writing or successive writing, a redundant memory cell is forcibly accessed in place of the defective memory cell. was working properly.

Normally, a fuse is built in the line that will be cut if a defective memory cell is discovered, and by cutting the fuse with a laser, etc., the internal structure of the circuit is changed and the redundant memory is replaced. The cell was being accessed.

[Problem to be solved by the invention]

However, in the past, only one fuse was built in one cutting line, so the failure rate of the semiconductor memory device itself due to faulty cutting of the fuse was relatively high. (formed from silicon, etc.) is recrystallized, there is a drawback that failure of the semiconductor memory device is unavoidable.

Note that it is possible to reduce the occurrence of disconnection defects by cutting one fuse more than once, for example.
Laser cutting has a large effect on the substrate, so it is not a good idea to cut the same spot multiple times.

This invention was made by focusing on the problems that the conventional technology has, and has a redundant relief function and reduces the occurrence of defects due to faulty cutting of fuses, recrystallization of cut fuses, etc. The purpose of the present invention is to provide a semiconductor memory device that can perform the following steps.

[Means to solve the problem]

In order to achieve the above object, the present invention provides the following features: by cutting a predetermined cuttable line and changing the internal structure of the circuit;
In a semiconductor memory device having a function of selecting a redundant memory cell in place of a defective memory cell, the cuttable line is configured by connecting a plurality of fuses in series.

[Operation] If the occurrence rate of a disconnection failure in one fuse is α, then the occurrence rate of a disconnection failure in a line in which n fuses are connected in series is αn. Here, since α<1, α'' becomes even smaller than α, and the incidence of cutting defects is dramatically reduced.

Further, if the probability that a cut fuse recrystallizes is β, then the probability that a cut line will be connected due to recrystallization of the fuse is β7. Since β<1, βn becomes even smaller than β, and the incidence of defects in the semiconductor memory device due to fuse recrystallization is dramatically reduced.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

1 to 7 are diagrams showing one embodiment of the present invention.

First, the concept of the semiconductor memory device 1 will be explained according to FIG. 2. The semiconductor memory device 1 includes a plurality of word lines W0 to W7 arranged in a grid pattern and bit lines (not shown).
For example, a memory cell such as SRAM (Static RAM) is configured between the row decoder 2 and the word line to which the memory cell is connected. This is performed with the word line driver 3 being driven and the word line raised.

In this embodiment, the redundant word line R corresponds to the word lines W0 to W3 wired on the upper side in FIG.
W, and a redundant word line R is provided corresponding to the word lines W4 to W7 wired on the lower side in FIG.
W is provided.

Note that these redundant word lines RWO, RW.

Similarly to word lines W0 to W, memory cells (
redundant memory cells) are connected.

Further, a redundant row decoder 4 and a redundant word line driver 5 are provided corresponding to the redundant word lines RWo, RW.

FIG. 3 is a circuit diagram showing an example of the address buffer 6. As shown in FIG.

That is, an external address signal Ai (A, ~A'?) supplied from the outside via an address bus (not shown) or the like is converted to an internal address signal a via inverters 6a and 6b.
i (ao~ah>), and is also read as an internal address signal b1, (b+o-b I7) via inverters 6a, 6b, 6c, and 6d,
Then, the output of the inverter 6c is the internal address signal 1
) If is the inverted data of the internal address signal. 5(b
oo~b0. ).

Note that there is PM on the power line VIID side of the inverter 6a.
O3 (P channel MO3) l-transistor P.

is provided, and the output side of the inverter 6a and the ground line GN
An NMO3 (N channel MO3) transistor N1 is provided between the PMOS transistor P+ and the NMO3) transistor NI, and the gates of the PMOS transistor P+ and the NMO3) transistor NI are changed from "H" to "L11" when reading the external address signal A□.
The control signal φ falls to . is supplied.

The internal address signal a is supplied to a redundant address detection circuit 7 as shown in FIG.
(Co ”Cb ).

That is, the output of the inverter 7a, whose input side is supplied with the internal address signal a, is connected to the input side of the inverter 7b,
The output of the inverter 7b is supplied to the transmission gate 7d.

Since the transmission gates 7c and 7d are configured so that only one of them is open, the internal address signal a is converted into the internal address signal C8 only via the inverter 7a (i.e. , internal address signal C4 is the inverted value of internal address signal a.)
When converted into internal address signal C8 via inverters 7a and 7b (in other words, internal address signal C1
has the same value as internal address signal a. ).

To explain the specific configuration, PMO3! which forms transmission game) 7c! - Gate of transistor P2 and power line■.

There are two series-connected fuses 8a and 8b as disconnectable lines between the gate of the NMOS transistor N2 forming the transmission gate 7c and the ground line GND. NMO3) transistor N
4 is interposed.

On the other hand, a PMOS transistor is connected between the gate of the PMOS transistor P3 forming the transmission gate 7d and the power supply line VDD.
A resistor R+ is interposed between the gate of the transistor P4 and the gate of the NMO transistor N3 forming the transmission gate 7d and the ground line GND.

and PMO3) transistors Pz, P4 and NMO3
) The gates of transistors N3 and N4 are common, and the gates of NMOS transistor N2 and PMO3I-transistor P3 are common.

FIG. 4 is a circuit diagram showing the low-bridging decoder 8,
FIG. 5 is a circuit diagram showing the row decoder 2 and word line driver 3.

That is, as shown in FIG. 4, a row decoder 8 consisting of a NAND circuit 8a and an inverter 8b receives an internal address signal S. (bo.), bz (bat) and su, fu (bot) are supplied, and the redundancy determination signal R
OM is supplied. As will be described later, the redundancy determination signal ROM is connected to the redundancy word line RW or RW.
, it is a signal that becomes "L++" when selecting , but becomes "°'H" in other cases.

Therefore, in the normal case where the redundancy determination signal ROM is uH++, the internal address signal tzo (boo).

If bz (bob) and ba7 (ba7) are all H'''' (that is, if the low relay decoder 8 is selected), the output of the NAND circuit 8a is ``L +1, and the output of the inverter 8b is ``'' H”.

Then, internal address signals b1゜(boo), ba
(bob), ba, (bat), any of the power supply terminals RA, ~RA of each driver 3a to 3h of the word line driver 3 is connected to the power supply line vnn, and any one of the word lines W. -W7 becomes drivable.

Note that each internal address signal boo (boo),
Of bz (bat) and tzt (bat), the internal address signal b+t (ba7) is the most significant bit and is used to select the top and bottom side word lines in FIG. Therefore, when selecting one of word lines W0 to W3, bat
becomes “H”, and the word lines W4 to W.

When selecting one of them, b17 becomes "H''.

As shown in FIG. 5, internal address signals b1□ (bob), b+:+(boi
), bi4(bo4)-, tzs(bos) and b16(boJ are supplied and the NAND circuit 2a
The output of is supplied to the gate of the NMO3) transistor on the high potential side of the drivers 3a to 3h via the inverter 2b,
In addition, the output of the NAND circuit 2a is directly connected to the drivers 3a to 3.
It is supplied to the gate of the NMOS transistor on the low potential side of h.

Furthermore, the output of each driver 3a-3h is connected to word lines W0-W7.

Therefore, if row decoder 2 is selected, power supply terminal R
The word lines W0 to W corresponding to the drivers 3a to 3h whose A and -RA are connected to the power supply line VDD will rise.

FIG. 6 is a circuit diagram showing the redundant row decoder 9, and FIG. 7 is a circuit diagram showing the redundant row decoder 4 and the redundant word line driver 5.

That is, as shown in FIG. 6, the control signal φ. The output of the inverter 9a to which is supplied is one input of the NAND transistor NMO3I-transistor N.

and the gate of transistor P5 (PMO3), and the other input side of NAND9b is supplied with an internal address signal b17 or signal b17. 7 is supplied, NAND
The output of 9b is supplied to the input side of inverter 9C.

The output of the inverter 9C is connected to the power supply terminal RRA of each driver 5 constituting the redundant word line driver 5.
, or RRA.

Here, word line W. - If a memory cell connected to any of word lines W3 is defective, one redundant word line RW is used, and if a memory cell connected to any of word lines W4 to W7 is defective, uses the other redundant word line RW.

As described above, when selecting the word lines Wo to W3, the internal address signal b07 is "'H", and when selecting the word lines W4 to W7, the internal address signal b17 is "HI+". Therefore, according to the internal address signal b17 or bo'1, the driver 5a of the redundant word line drivers shown in FIG.
and 5b is made drivable.

Furthermore, as shown in FIG. 7, a redundant row decoder 4
is composed of a NAND circuit 4a and a NOR circuit 4b, and the output (ROM) of the NOR circuit 4 is supplied to the gate of the NMO3) transistor on the power supply side of the drivers 5a and 5b and to the inverter 4C, 4a
The output of is supplied to the gate of the transistor NMO3) on the ground line GND side of the drivers 5a and 5b.

The input side of the NAND circuit 4a receives internal address signals 00 to 00, which are the outputs of the redundant address detection circuit 7 shown in FIG.
C5 is supplied. Therefore, the output of the NAND circuit 4a becomes "L" (that is, the redundant row decoder 4 is selected) when all of the internal address signals 00 to C6 become "H".

Then, the output of the driver 5a is the redundant word line RW.
, the output of the driver 5b is supplied to the redundancy word line RW, and the output of the inverter 4c is supplied as a redundancy determination signal ROM to the NAND circuit 8a of the row-brid decoder 8 shown in FIG. Supplied.

Further, the output of the redundancy determination circuit 10 is supplied to the NOR circuit 4b as well as the output of the NAND circuit 4a.

Here, the redundancy determination circuit 10 includes an inverter 10a, a resistor R2 and a fuse 11a interposed in series between the power supply line VDD and the ground line GND.

11b, and the input side of the inverter 10a and the PMO3 transistor P6 are connected between the resistor R2 and the fuse lla.
■ Power line through. and is connected to.

The output of the inverter 10a is supplied to the gate of the PMOS transistor P6 and the NOR circuit 4b.

Next, the operation of this embodiment will be explained.

Now, assuming that all normally used memory cells in the semiconductor storage device 1 are normal, in this case there is no need to use redundant memory cells, so the fuses 8a and 8b
, lla and Ilb are not cleaved.

Then, in the redundancy determination circuit 10, the inverter 10a
Since the input side of the inverter 10a is connected to the ground line GND via the fuses lla and 11b, the output of the inverter 10a becomes H'', the PMO3) transistor P6 is turned off, and the output of the inverter 10a is supplied. The output of the NOR circuit 4b becomes "IIL".

If the output of the NOR circuit 4b is “L”, the driver 5a,
5b is not driven, and the redundant word line RW,
, RW, does not stand up.

That is, the redundancy determination circuit 10 functions to stop the operation of the redundant row decoder when all memory cells are normal.

On the other hand, the redundancy determination signal ROM which is the output of the inverter 4C
, becomes II HII, so the low-brid decoder 8
is an internal address signal. (b,.),b++(bo
one word line W determined by b) and b+t(bot). -Driver 3a~ so that W7 starts up.
Connect any of the power supply terminals RA, ~RA, of 3h to the power supply line V.
Connect to DD.

Then, the row decoder 2 outputs the internal address signal b1□
(box) , b+3(bc+z) , baa (
b04).

When selected by bus (bos) and b+6 (boi, ), the drivers 3a to 3h to which any of the word lines W0 to W are connected become driven, and any of the word lines W0 to W rises. It becomes possible to successively write and write data in memory cells connected to the word line that has risen.

Next, an explanation will be given of the operation when a defect is found in a memory cell of the semiconductor memory device 1.

All internal address signals C8 are applied to addresses corresponding to word lines to which defective memory cells are connected.
The fuses 8a and 8b of the corresponding redundant address detection circuit 7 and the fuses lla and llb of the redundancy determination circuit 10 are all cut with a laser so that the voltage becomes 'H'°.

Redundancy determination circuit 1 with fuses lla and llb disconnected
0, the input side of the inverter 10a is connected to the power supply line (2) via the resistor R2. , the output of the inverter 10a becomes "L".

Then, the PMOS transistor P is turned on and stable power is supplied to the input side of the inverter 10a, and the output of the inverter 10a is stabilized at "'L", so the NOR
The output of the circuit 4b is determined only by the output of the NAND circuit 4a.

On the other hand, fuses 8a and 8b of the redundant address detection circuit 7
When disconnected, PMOS transistors P, , P and NMO3I-transistor N3. N.

Since the gate of P is connected only to the ground line GND,
MO3) Transistors P2 and P4 turn on, and NMO
3) Transistors N3 and N4 are turned off.

Furthermore, since the gates of the PMO3) transistor P3 and the NMOS transistor N are connected to the power supply line vflI, the PMO3) transistor P3 is turned off, and the NMOS transistor N
O3I-transistor N2 is turned on.

Therefore, since the transmission gate 7C is turned on and the transmission gate 7d is turned off, the internal address signal a supplied to the redundant address detection circuit 7 is outputted only via the inverter 7a.

Therefore, the internal address signal C4, which is the output of the redundant address detection circuit 7 with fuses 8a and 8b cut,
is the inverted value of internal address signal a.

Now, if a word line connected to a defective memory cell is to be selected during writing or successive writing, all internal address signals Ci become H"", so the NAND circuit 4a
The output of the inverter 4c becomes "L", the output (ROM+) of the NOR circuit 4b becomes "H", and the drivers 5a and 5b become ready to drive.
OMo) becomes °“L”.

Therefore, the row decoder 8 to which the redundancy determination signal ROM is supplied is in a non-selected state, so that the word line W is applied regardless of the internal address signal b I i+ b Of. -W, none of them stand up.

On the other hand, if the internal address signal bat is "IIH", power is supplied to the driver 5a by the redundant row/brief decoder 9, and if the internal address signal boff is H", power is supplied to the driver 5b.

Then, the redundant word line RW or RW + connected to the driver 5a or 5b to which power is supplied rises, and writing or reading of the redundant memory cell becomes possible.

In other words, with the configuration of this embodiment, if a word line to which a defective memory cell is connected is selected,
Since the redundant word line RW or RW is selected, the appearance is completely the same as when a normal semiconductor memory device 1 is used.

Furthermore, in this embodiment, redundant word lines RW are used instead of the word lines W0 to W7 used during normal operation.
, RW, is selected by cutting off both fuses 8a and 8b built into the redundant address detection circuit 7 in a series-connected state, and
Since this is realized by cutting off both of the two fuses Ila and llb built into the redundancy determination circuit 10 while connected in series, these fuses 8a8b,
The risk of failure of the semiconductor memory device 1 due to poor cutting of lla and llb is extremely small.

In addition, since the fuses 8a, 8b, lla, and llb are usually made of polysilicon or the like, there is a risk that the fuses that should have been cut may become conductive due to recrystallization, changing the circuit structure. With the configuration of the example, the circuit functions normally unless both fuses 8a and 8b or both fuses lla and llb are conductive, so the risk of defects due to recrystallization of the fuses is extremely small.

In the above embodiment, there are two fuses 8a.

Although the case where the cuttable line is constructed by connecting 8b, lla, and llb in series has been described, the present invention is not limited to this, and three or more fuses may be used.

However, as the number of fuses increases, the time required for disconnection also increases, so in consideration of the incidence of defects and the time required for disconnection, it is sufficient to connect two fuses as in the above embodiment.

Further, the configuration in which a redundant memory cell is selected in place of a defective memory cell by cutting a predetermined line and changing the internal structure of the circuit is not limited to the configuration of the above embodiment; Other configurations are also possible.

〔Effect of the invention〕

As explained above, in the present invention, the line to be cut when a redundant memory cell is used instead of a memory cell used during normal operation is configured with a plurality of fuses connected in series. This has the effect of extremely reducing the risk of defects in semiconductor memory devices due to defects or recrystallization of fuses.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a redundant address detection circuit in an embodiment of the present invention, FIG. 2 is a conceptual diagram of a semiconductor memory device, and FIG. 3 is a circuit diagram showing an example of an address buffer.
FIG. 4 is a circuit diagram showing an example of a row decoder, FIG. 5 is a circuit diagram showing an example of a row decoder, FIG. 6 is a circuit diagram showing an example of a redundant row decoder, and FIG. The figure is a circuit diagram showing an example of a redundant row decoder. ■...Semiconductor storage device, 2...Row decoder, 3
... Word line driver, 4... Redundant row decoder, 5... Redundant word line driver,
7...Redundant address detection circuit, 8a, 8b, 1la1
1b...Fuse, 10...Redundancy judgment circuit, Wo~
W,...word line, RW,,RW,...redundant word line

Claims (1)

[Claims] (1) In a semiconductor memory device having a function of selecting a redundant memory cell in place of a defective memory cell by cutting a predetermined cuttable line and changing the internal structure of the circuit, the cuttable line What is claimed is: 1. A semiconductor memory device comprising a plurality of fuses connected in series.