JPH03282803A - Voltage clamping circuit - Google Patents

Abstract

PURPOSE:To stably clamp a voltage by inverting the output of a comparator to drive a metal-insulator semiconductor field effect transistor (MIS FET) for short-circuit and positively using the supply voltage dependence of the comparator output. CONSTITUTION:The gate of a MIS FET M19 for short-circuit is driven by the output of an added inverter i1, and the gate of a MIS FET M18 is connected to point B1 of a differential circuit. The inverter I1 is added to eliminate the positive dependence of the clamp voltage, and the output from a differential amplifying circuit is inverted to eliminate the abuse due to insertion of the inverter I1. Thus, the voltage is stably clamped.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a voltage clamp circuit using a MISFET (insulated gate field effect transistor), and in particular, to a voltage clamp circuit using a MISFET (insulated gate field effect transistor), and in particular to a voltage clamp circuit using a MISFET (insulated gate field effect transistor). Connect the voltage to the clamp circuit.

[Conventional technology]

FIG. 4 is a circuit diagram of a conventional voltage clamp circuit 9.

This conventional example uses a solar cell P which is a non-regulated power source.
When the output of 1 is used as a negative power supply of the semiconductor integrated circuit device Ll, the negative voltage -vss obtained by the output of the solar cell PI (which can generally be considered as a constant current output)
This is to clamp so that t does not fall too low. In addition, in FIG. 4, since a diode D1 for backflow prevention is provided between the output terminal of the solar cell Pi and the semiconductor integrated circuit device MLl, the negative voltage -VSSI is supplied to the semiconductor integrated circuit device L1. It is separated from the negative voltage -VSS2, but if the negative voltage -VSSI increases significantly, the negative voltage -VSS2 will also increase due to the influence. Preventing large fluctuations in -VSS1 results in preventing fluctuations in negative voltage -VSS2. In addition, a voltage holding capacitor C is connected between the negative voltage -VSS2 and the ground (positive power supply).
1 is provided.

Next, the configuration of this conventional example will be explained.

This conventional example includes a trimming circuit Tl that divides and outputs a negative voltage -VSS2 according to a voltage division ratio determined by digital inputs Sit to Sin, a comparator 1cl- that receives the divided voltage output of this trimming circuit T1, and a comparator 1cl- for shorting. The comparator 1d consists of an enhancement type PMIS FET N13 and a depletion type PMIS FET N14 forming a differential pair, and a current mirror serving as an active load of this differential pair. Configure NMIS
FET N15. Mlfl, PMIS FET Mll, N12 which constitutes a constant current source circuit, constant current source Jl, PMIS FET N17 which constitutes an inverting amplifier circuit,
It is composed of NMIS FET N18.

The operation of this conventional example will be explained.

If the negative voltage −VSS 1 drops significantly, lllOs
Since the gate-source voltage of the FET exhibits constant voltage characteristics, the NMOS FE constitutes the impulse load of the differential amplifier circuit.
The gate voltage of T N15 and N113 also decreases, and the gate voltage of NMOS FET M18 in the output stage decreases. As a result, the gate voltage of short NMOS FET N19 increases, turning on this NMOS FET l11, and -VS
Compensate for the significant drop in SI.

-VSS when clamped by this negative feedback effect
I (-VSS2) is enhancement type PIII
Let the threshold voltage of SFET N13 be VTE,
When the threshold voltage of the depletion type PMIS FET N14 is VTD and the voltage division ratio of the trimming circuit Tl is α, it is expressed as VTE-VTD-VSSI (-VSS2)=. In other words, in a voltage clamped state, PMIS FETs N13 and N14 forming a differential pair are balanced, and such a balanced state is achieved by adjusting the threshold voltages of both transistors forming a differential pair. This is a case where the difference is output from the trimming circuit, from which the above relational expression is derived.

In reality, since the response speed of the comparator is finite, the clamp voltage will be lower than the ideal value determined by the above formula, but it is possible to increase the capacity of the voltage holding capacitor CI and improve the operating speed of the comparator. By increasing the shorting capability of NMISFET N19 for shorting, it is possible to clamp the voltage to a value that does not cause any problems.

[Problem to be solved by the invention]

In the conventional clamp circuit using the MIS FET described above, when the NNl5 FET N19, which has sufficient short-circuiting ability, turns on -H, the voltage will rise significantly beyond the compensation range of the reduced negative voltage -VSSl. There is (
In other words, if the potential approaches the ground level 1, there is a problem in that in such a case, the clamp circuit malfunctions and this potential rise is accelerated.

The reason why this problem occurs will be explained using FIGS. 4 and 5.

Negative voltage -VSSI due to excessive charging from solar cell Pi
becomes below the clamp voltage, and the NMISFET for shorting
Consider a case where N19 turns on and then shifts to the off state. If the negative voltage -VSSI does not rise excessively, the current capacity of the NMIS FET N18 that constitutes the output stage is larger than the current capacity of the PMIS FET N17 in the sum region, so the short-circuit NIS FET Mll
? The gate of becomes low level and turned off, and the negative voltage -vsst almost becomes the clamp level. However, as a result of the short circuit, when the negative voltage -VSSI voltage increases significantly, the source potential of NMIS FET N18 also increases accordingly, and on the other hand, the NMIS FET that forms the current mirror load of the differential circuit 115. MlB(
7) C) The potential also rises in the same way. However, since the depletion type PMIS FET 14 is in the triode region, the potential at point A1 hardly changes, and as a result, the gate-source voltage of the old NMIS FET 8 decreases, causing it to turn off. Become. Then, PMIS FET
Ml? The output current of comparator 1 drives the gate of NMIS [19], which maintains the on state, and the clamp voltage shifts sharply towards the ground side.In this way, the output of comparator 1 has a positive dependence on the power supply voltage. have This relationship is illustrated in FIG. 5.

The voltage clamp circuit of the present invention comprises a differential pair consisting of two first conductivity type NIS FETs having different threshold voltages, a common source of the differential pair, and a first conductivity type NIS FET. a current source connected between a power source and a first conductivity type MIS FET forming the differential pair;
and a signal obtained from a common connection point between the load element and the first conductivity type NIS FET, and a load element connected between the drain of the first conductivity type NIS FET and the second power supply. a comparator consisting of an inverting amplifier circuit whose operating power supply is an inverting amplifier circuit, an inverter whose input is the output of the inverting amplifier circuit, the output of the inverter constituting the comparator being the gate input voltage, and the first and second power supplies and a second conductivity type NIS FET provided therebetween.

[For production]

By inverting the comparator output with an inverter and driving the Is FET for shorting with this inverted output, the dependence of the clamp voltage on the power supply voltage can be eliminated.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of one embodiment of the voltage clamp circuit of the present invention, and FIG. 2 is a diagram for explaining the operation of this embodiment.

This embodiment differs from the conventional example shown in FIG.

The gate of short MIS FET Mll3 is driven by the output of newly added inverter E1, and the gate of NMIS FET18 is driven by B1 of the differential circuit.
A point connected to a point. By adding the inverter If, the characteristics of this embodiment are changed to 5 as shown in FIG.
This is the opposite of the figure, and the positive dependence on the clamp voltage disappears.

Further, by reversing the output output from the differential amplifier circuit, the adverse effects caused by inserting the inverter II can be eliminated.

FIG. 3 is a circuit diagram of another embodiment of the voltage clamp circuit of the present invention.

The nut weave is an inverted circuit of the conductivity type of the MIS transistor shown in FIG. 1, and the same effect as the embodiment shown in FIG. 1 can be obtained.

〔Effect of the invention〕

As explained above, the present invention inverts the comparator output to drive the shorting MIS FET, and actively utilizes the power supply voltage dependence of the comparator output.
This has the effect of stably performing voltage clamping.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of one embodiment of the voltage clamp circuit of the present invention, FIG. 2 is a diagram for explaining the operation of this embodiment, and FIG. 3 is a circuit diagram of another embodiment of the voltage clamp circuit of the present invention. FIG. 4 is a circuit diagram of a conventional example, and FIG. 5 is a diagram for explaining the operation of the conventional example. la, 1b, 1d... Comparators. Pi・・・・・・・・・・・・Solar cell, L 1...
......LSI. T1・・・・・・・・・Trimming circuit, C1・
・・・・・・・・・Holding capacitor, Jl・・・・
・・・・・・・・・Constant current source, Il・・・・・・・・・・
...Inverter, Mll, M121M17. M13
・・・・・・Enhancement type PMIS M14・・・・・・・・・Depression type P
MISM15. MlB, MlB...FET, FET, enhancement type NMIS FET, [19......NMISF for shorting
E.T.

Claims (1)

[Claims] 1. Two first conductivity type MIs with different threshold voltages
A differential pair consisting of SFETs, a current source connected between a common source of the differential pair and a first power source, and a drain of a first conductivity type MISFET forming the differential pair and a second power source. an inverting amplifier circuit whose input is a load element connected between the two and a signal obtained from a common connection point between the load element and the first conductivity type MISFET, and whose operating power supplies are the first and second power supplies; , a comparator consisting of an inverter whose input is the output of the inverting amplifier circuit, and a second conductivity type provided between the first and second power supplies, the gate input voltage being the output of the inverter constituting the comparator. MISF
A voltage clamp circuit with ET.