JPH03280451A - Semiconductor device mounting wiring board and manufacture thereof - Google Patents
Semiconductor device mounting wiring board and manufacture thereofInfo
- Publication number
- JPH03280451A JPH03280451A JP8005990A JP8005990A JPH03280451A JP H03280451 A JPH03280451 A JP H03280451A JP 8005990 A JP8005990 A JP 8005990A JP 8005990 A JP8005990 A JP 8005990A JP H03280451 A JPH03280451 A JP H03280451A
- Authority
- JP
- Japan
- Prior art keywords
- resist film
- conductive circuit
- hole
- film
- alumina ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000007747 plating Methods 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 18
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000011248 coating agent Substances 0.000 claims abstract description 11
- 238000000576 coating method Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052802 copper Inorganic materials 0.000 abstract description 10
- 239000010949 copper Substances 0.000 abstract description 10
- 229910000679 solder Inorganic materials 0.000 abstract description 4
- 241000587161 Gomphocarpus Species 0.000 abstract description 2
- 230000000149 penetrating effect Effects 0.000 abstract description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 11
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 239000011133 lead Substances 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 238000007788 roughening Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910000851 Alloy steel Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000012255 powdered metal Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Landscapes
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は半導体素子搭載用配線板及びその製造法に関す
る。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a wiring board for mounting semiconductor elements and a method for manufacturing the same.
(従来の技術)
従来の半導体素子搭載用配線板は、セラミックグリーン
シート上にタングステン、モリブデン。(Conventional technology) Conventional wiring boards for mounting semiconductor elements are made of tungsten and molybdenum on ceramic green sheets.
モリブデン−マンガン等の高融点金属粉を主成分とした
ペーストを印桐して回路を形成し、ついでこれらを積層
して焼成し、さらに回路の上面にニッケルめっき、金め
つきを施し、リードピンを銀ロー付して製造するか又は
ガラスエポキシ基板などの有機質基板上に銅の被膜を形
成し、これらをエツチングなどの方法で回路を形成し、
さらに回路の上面にニッケルめっき、金めつきを施し、
リードピンをはんだ付けして製造していた。A circuit is formed by printing a paste mainly composed of powdered metals with high melting points such as molybdenum and manganese, then these are laminated and fired, and the top surface of the circuit is plated with nickel and gold, and lead pins are attached. It is manufactured by silver brazing, or by forming a copper film on an organic substrate such as a glass epoxy board, and forming a circuit by etching or other methods.
Furthermore, the top surface of the circuit is nickel plated and gold plated,
It was manufactured by soldering lead pins.
(発明が解決しようとする課題)
しかしなから前者の方法では印刷法によるため配線密度
が低く、ワイヤーボンディング端子数が多いものは多層
化にする必要があり、また還元雰囲気中で焼成、ロー付
する力ど製造工程が複雑となる欠点がある。(Problem to be solved by the invention) However, since the former method uses a printing method, the wiring density is low, and devices with a large number of wire bonding terminals need to be multilayered. The disadvantage is that the manufacturing process is complicated.
一方後者の方法では基板の熱伝導率が低いため。On the other hand, in the latter method, the thermal conductivity of the substrate is low.
半導体素子から発生する熱の放熱性に劣るという欠点が
ある。A drawback is that the heat dissipation performance of the heat generated from the semiconductor element is poor.
本発明は上記の欠点の力い半導体素子搭載用配線板及び
その製造法を提供することを目的とするものである。An object of the present invention is to provide a wiring board for mounting semiconductor elements and a method for manufacturing the same, which overcomes the above-mentioned drawbacks.
(1111題を解決するための手段)
本発明はアルミナセラミック基板のほぼ中央部の半導体
素子が搭載される部分を除いた部分の周辺の表面に形成
されたワイヤーボンディング部。(Means for Solving Problem 1111) The present invention provides a wire bonding portion formed on the peripheral surface of an alumina ceramic substrate excluding a portion where a semiconductor element is mounted at approximately the center thereof.
ワイヤーボンディング部と接して形成された導通回路、
導通回路の上面の一部に形成された耐めっきレジスト膜
、導通回路及びアルミナセラミック基板を貫通して形成
された貫通孔0貫通孔内に挿入固着されたピンとからな
る半導体素子搭載用配線板及びアルミナセラミック基板
の任意の個所に貫通孔を形成した後、#アルミナセラミ
ック基板の表面を化学政に粗化し、ついでめっき法によ
シ金属被膜を形成し、さらにその上面にレジスト膜を形
成し、エツチング法で金属被膜の必要な部分のみを残し
て導通回路を形成し、しかる抜導通回路の一部に耐めっ
きレジスト膜を形成し、耐めっきレジスト膜を形成して
いない導通回路の先端部分にワイヤーボンディング部を
形成した後0貫通孔内にピンを挿入して固着する半導体
素子搭載用配線板の製造法に関する。A conduction circuit formed in contact with the wire bonding part,
A wiring board for mounting a semiconductor element, comprising a plating-resistant resist film formed on a part of the upper surface of a conductive circuit, a pin inserted and fixed in a through hole formed by penetrating the conductive circuit and an alumina ceramic substrate, and After forming through holes at arbitrary locations on the alumina ceramic substrate, the surface of the alumina ceramic substrate is chemically roughened, a metal coating is then formed by a plating method, and a resist film is further formed on the top surface of the alumina ceramic substrate. Using the etching method, a conductive circuit is formed by leaving only the necessary parts of the metal coating, and a plating-resistant resist film is formed on a part of the conductive circuit, and a plating-resistant resist film is formed on the tip of the conductive circuit where the plating-resistant resist film is not formed. The present invention relates to a method of manufacturing a wiring board for mounting a semiconductor element, in which a wire bonding part is formed and then a pin is inserted into a through hole and fixed.
本発明における粗化法については特に制限はなく1例え
ばSnow溶液又#′1NH4F、 (NH4)2S
O4。There are no particular limitations on the roughening method used in the present invention. For example, Snow solution or #'1NH4F, (NH4)2S
O4.
濃H!SO4、HzO等の混合溶液からなるフッ化物混
合物中に浸漬するか又は加熱したNaOH,KOH等の
融液中に浸漬することにより粗化することができる。Thick H! It can be roughened by immersing it in a fluoride mixture consisting of a mixed solution of SO4, HzO, etc., or by immersing it in a heated melt of NaOH, KOH, etc.
ワイヤーボンディング部及び導通回路を構成する金属被
膜の形成に用いられる金属としては、ニッケル、ニッケ
ル合金、銅、鋼合金、金等が用いられる。めっき法につ
いては特に制限はないが。Nickel, nickel alloy, copper, steel alloy, gold, etc. are used as the metal used to form the metal coating that constitutes the wire bonding portion and the conductive circuit. There are no particular restrictions on the plating method.
無電解めっき法で行うことが好ましい。めっきは例えば
無電解銅めっきを施した彼、その上面にニッケル、金め
つき等を施すことが好ましい。It is preferable to use an electroless plating method. As for the plating, it is preferable to apply electroless copper plating, for example, and then apply nickel or gold plating on the upper surface.
レジスト膜及び耐めっきレジスト膜は、熱硬化性のレジ
ストを金属被膜の上面にスクリーン印刷し、加熱、硬化
して形成してもよく、感光性レジストフィルムを金属被
膜上に貼付してもよく特に制限はない。The resist film and plating-resistant resist film may be formed by screen printing a thermosetting resist on the top surface of the metal coating and heating and curing it, or may be formed by pasting a photosensitive resist film on the metal coating. There are no restrictions.
エツチング法i11. レジスト膜の形成方法により
適宜選定するものとし特に制限はない。Etching method i11. It shall be appropriately selected depending on the method of forming the resist film, and there are no particular limitations.
ピンの材質は9%に制限はないが、コパール。The material of the pin is not limited to 9%, but it is copper.
42合金、52合金等のNi系合金、銅、銅合金などが
使用できる。ピンの長さは挿入して固着する導通回路及
び導通回路を形成するアルミナセラミック基板より突出
させるため導通回路及び導通回路を形成するアルミナセ
ラミック基板より長いものを用いることが好ましく、突
出長さは2−以上あることが好ましい。このピンと導通
回路との固着は、半田、銀ろう、熱硬化性樹脂、耐熱性
熱可塑性樹脂等が用いられる。Ni-based alloys such as 42 alloy and 52 alloy, copper, and copper alloys can be used. The length of the pin is preferably longer than the conduction circuit and the alumina ceramic substrate forming the conduction circuit to protrude from the conduction circuit to be inserted and fixed and the alumina ceramic substrate forming the conduction circuit, and the protrusion length is 2. - or more is preferable. Solder, silver solder, thermosetting resin, heat-resistant thermoplastic resin, or the like is used to secure the pin to the conductive circuit.
(実施例) 以下本発明の詳細な説明する。(Example) The present invention will be explained in detail below.
実施例1
第1図に示すように寸法が80X80mmで厚さが1.
0 IIImのアルミナセラミック基板(日立化成工業
製、商品名ハロツクス570)1のほぼ中央部の半導体
素子が搭載される部分を除いた部分の任意の個所に2.
54肛間隔で直径0.64 me(φ)の貫通孔2を2
08個形成した彼、脱脂液(日立化成工業製1曲品名H
CR201)で洗浄し、乾燥後350℃に加熱したN
a OH融液中に1分間!!!潰し粗化を行った。つい
で!1度10]rii1%のH280a液中に5分間浸
漬し、超音波による振動エネルギーを付与して中和し、
さらに水洗、乾燥後再び350℃に加熱したNaOH融
液中融液中間1分間浸漬粗化を行った。この後上記と同
様に濃度10重iチの市804溶液中に5分間浸漬して
中和、水洗後熱電解めっき液(日立化成工業製、商品名
L−592中に6時間V潰して厚さ10 l1mの鋼の
被膜を形成した。Example 1 As shown in Fig. 1, the dimensions are 80 x 80 mm and the thickness is 1.
0 IIIm alumina ceramic substrate (manufactured by Hitachi Chemical Co., Ltd., trade name Halox 570) 1, at any location except for the area where the semiconductor element is mounted in the approximate center.
2 through holes 2 with a diameter of 0.64 me (φ) at 54-hole intervals.
He formed 08 pieces, degreasing liquid (manufactured by Hitachi Chemical, product name H
CR201), dried and heated to 350°C
a 1 minute in the OH melt! ! ! It was crushed and roughened. Next! 1 degree 10]RII immersed in 1% H280a solution for 5 minutes, neutralized by applying vibrational energy by ultrasonic waves,
Furthermore, after washing with water and drying, roughening was performed again by immersion in a NaOH melt heated to 350° C. for 1 minute in the middle of the melt. After that, in the same manner as above, it was immersed in Ichi 804 solution with a concentration of 10 parts Ichi for 5 minutes to neutralize it, washed with water, and then crushed in a thermal electrolytic plating solution (manufactured by Hitachi Chemical Co., Ltd., trade name L-592 for 6 hours to form a thick layer). A steel coating of 10 lm was formed.
次に感光性レジストフィルム(日立化成工業製。Next, a photosensitive resist film (manufactured by Hitachi Chemical Co., Ltd.).
商品名PH’l’−862AP’−40)を前記銅の被
膜上全面に貼付し、さらKその上面に、得られる導通回
路と同形状に透明な部分を形成したネガフィルムを貼付
し、露光してネガフィルムの透明な部分の下面に配設し
た感光性レジストフィルムを硬化させた。ついでネガフ
ィルムを取り除き、さらに現像して硬化していない部分
、詳しくは露光していない部分の感光性レジストフィル
ムを除去゛シ、塩化mエツチング液でエツチングを行い
導体回路として不必要な部分の銅の被膜を除去した。A film (trade name: PH'l'-862AP'-40) was applied to the entire surface of the copper film, and a negative film with a transparent part formed in the same shape as the conductive circuit to be obtained was applied to the upper surface of the film, and exposed. The photosensitive resist film placed on the lower surface of the transparent portion of the negative film was then cured. Next, the negative film is removed, and the photosensitive resist film is removed in areas that have not been developed and cured, specifically, areas that have not been exposed to light, and etched with mchloride etching solution to remove copper from areas that are unnecessary for conductor circuits. The coating was removed.
た。Ta.
ついで導通回路3のランド部となる部分とその先端部分
を除いた部分に耐めっきレジスト(アサヒ化学研究所製
、商品名CCR506)を塗布して耐めっきレジスト膜
5を形成した後、ランド部となる部分とその先端部分の
銅の被膜上にワット浴で2μmの厚さにニッケルめっき
を施し、さら圧その上面に金めつき〔日本エレクトロブ
レイティングエンジニャーズ(EEJA)製、商品名テ
ンペレックス401〕を施してランド部(図面せず)と
ワイヤーボンディング部4とを形成した。Next, a plating-resistant resist (manufactured by Asahi Chemical Research Institute, trade name: CCR506) is applied to the portion of the conductive circuit 3 excluding the land portion and its tip portion to form a plating-resistant resist film 5. Nickel plating is applied to the copper coating on the part and its tip to a thickness of 2 μm in a Watts bath, and then gold plating is applied to the upper surface of the plated surface under further pressure [manufactured by Electroblating Engineers of Japan (EEJA), trade name: Temperex]. 401] to form a land portion (not shown) and a wire bonding portion 4.
次に第2図に示すように貫通孔2内にすずめつきを9
amの厚さに施した直径が0.46m+で。Next, as shown in FIG.
The diameter applied to the thickness of am is 0.46m+.
方の端部をくぎの顆状に加工した長さが710mの52
合金のネールへラドピン5を挿入し、他の一方の端部(
端子)を下面に露出させた後8n : Pb=60:4
0の半田でネールヘッドピン5を固着し、かつ貫通孔2
内を気密封止した半導体素子搭載用配線板を得た。52 with a length of 710m with one end shaped like a nail condyle.
Insert the rad pin 5 into the alloy nail and press the other end (
8n:Pb=60:4 after exposing the terminal) to the bottom surface
0 solder to fix the nail head pin 5 and through hole 2.
A wiring board for mounting a semiconductor element, the inside of which was hermetically sealed, was obtained.
(発明の効果)
本発明になる半導体素子搭載用配線板は、高密度配線に
優れ、ワイヤーボンディング端子数が多いものでも多層
化する必要がなく、放熱性に優れるなどの効果を奏する
半導体素子搭載用配線板である。(Effects of the Invention) The wiring board for mounting semiconductor elements according to the present invention is excellent in high-density wiring, does not require multilayering even when the number of wire bonding terminals is large, and has excellent heat dissipation properties. This is a wiring board for
第1図は1本発明の実施例における半導体素子搭載用配
線板の製造作業状態を示す一部省略断面図及び第2図は
1本発明の実施例になる半導体素子搭載用配線板である
。
符号の説明
1・・・アルミナセラミック基板
2・・・貫通孔 3・・・導通回路4・・
・ワイヤーボンディング部
5・・・耐めっきレジスト膜
6・・・ネールへラドピンFIG. 1 is a partially omitted cross-sectional view showing the manufacturing process of a wiring board for mounting a semiconductor element according to an embodiment of the present invention, and FIG. 2 shows a wiring board for mounting a semiconductor element according to an embodiment of the present invention. Explanation of symbols 1... Alumina ceramic substrate 2... Through hole 3... Continuity circuit 4...
・Wire bonding part 5... Anti-plating resist film 6... Rad pin to nail
Claims (1)
が搭載される部分を除いた部分の周辺の表面に形成され
たワイヤーボンディング部、ワイヤーボンディング部と
接して形成された導通回路、導通回路の上面の一部に形
成された耐めつきレジスト膜、導通回路及びアルミナセ
ラミック基板を貫通して形成された貫通孔、貫通孔内に
挿入固着されたピンとからなる半導体素子搭載用配線板
。 2、アルミナセラミック基板の任意の個所に貫通孔を形
成した後、該アルミナセラミック基板の表面を化学的に
粗化し、ついでめつき法により金属被膜を形成し、さら
にその上面にレジスト膜を形成し、エッチング法で金属
被膜の必要な部分のみを残して導通回路を形成し、しか
る後導通回路の一部に耐めつきレジスト膜を形成し、耐
めつきレジスト膜を形成していない導通回路の先端部分
にワイヤーボンディング部を形成した後、貫通孔内にピ
ンを挿入して固着することを特徴とする半導体素子搭載
用配線板の製造法。[Scope of Claims] 1. A wire bonding portion formed on the surface of the alumina ceramic substrate around the area excluding the portion where the semiconductor element is mounted, which is approximately in the center, and a conduction circuit formed in contact with the wire bonding portion. A wiring for mounting a semiconductor element, which is made up of a resist film formed on a part of the upper surface of the conductive circuit, a through hole formed through the conductive circuit and the alumina ceramic substrate, and a pin inserted and fixed in the through hole. Board. 2. After forming through-holes at arbitrary locations on the alumina ceramic substrate, the surface of the alumina ceramic substrate is chemically roughened, a metal coating is then formed by a plating method, and a resist film is further formed on the top surface. , a conductive circuit is formed by leaving only the necessary part of the metal film by etching, and then a plating resist film is formed on a part of the conductive circuit, and the conductive circuit without the plating resist film is formed. A method for manufacturing a wiring board for mounting a semiconductor element, which comprises forming a wire bonding part at the tip, and then inserting a pin into a through hole and fixing it.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8005990A JPH03280451A (en) | 1990-03-28 | 1990-03-28 | Semiconductor device mounting wiring board and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8005990A JPH03280451A (en) | 1990-03-28 | 1990-03-28 | Semiconductor device mounting wiring board and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03280451A true JPH03280451A (en) | 1991-12-11 |
Family
ID=13707664
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8005990A Pending JPH03280451A (en) | 1990-03-28 | 1990-03-28 | Semiconductor device mounting wiring board and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03280451A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002299497A (en) * | 2001-03-30 | 2002-10-11 | Kyocera Corp | Bonding structure of ceramic basic material and conductor pin |
-
1990
- 1990-03-28 JP JP8005990A patent/JPH03280451A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002299497A (en) * | 2001-03-30 | 2002-10-11 | Kyocera Corp | Bonding structure of ceramic basic material and conductor pin |
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