JPH03278283A - Image processor - Google Patents

Abstract

PURPOSE:To rapidly search the existing position of an object by forming a compressed image from a binary image, converting the picture element data of an independent picture element in the compressed image to remove noise and scanning the noise-removed compressed image to search the existing position of the object. CONSTITUTION:Picture element data are extracted every other three picture elements in horizontal and vertical directions of a binary image to compress binary picture element data BVi. A noise removing circuit 20 detects and in dependent picture element from the compressed image and the picture element data of the independent picture element is converted so that a black picture element is converted into a white picture element and vice versa. The nose- removed compressed image data BVi are stored in an image memory 19 and then a CPU 22 scans all the compressed image to search the existing position of the object.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an image processing device used to search for the location of an object by processing an input image obtained by imaging the object.

<Prior Art> Conventionally, this type of image processing apparatus generates a binary image 1 as shown in FIG. There is a method that searches for the location of the object by scanning the entire image 1 as shown by the arrow in the figure to detect black pixel portions 2.3 corresponding to the image of the object. The input image contains large and small noise, and this noise appears as, for example, a black pixel portion 4 on the binary image 1. Therefore, during scanning, the area of 2 to 40 black pixel portions is measured and the area of the black pixel portion 4 is measured based on the size of the measured value. Search processing is proceeding while determining whether the black pixel portion is noise or not.

<Problems to be solved by the invention> However, in such a method, it is necessary to scan the entire binary image 1 over the entire image, and each time a black pixel portion is detected, area measurement is performed for noise discrimination. Therefore, there is a problem in that the search process takes a lot of time.

The present invention has been made in view of the above problem, and an object of the present invention is to provide a novel image processing device that can search for the location of an object at high speed.

<Means for Solving the Problems> In the present invention, in order to search for the location of the object by processing an input image obtained by imaging the object, the input image is binarized. means for generating a binary image; means for extracting pixel data at a predetermined pixel position from the binary image to generate a compressed image; and converting pixel data for isolated pixels in the compressed image to remove noise. An image processing device is constituted by means for scanning the compressed image after noise removal and searching for the location of the object.

<Operation> Since the location of the object is searched using the compressed image obtained by removing noise after compression processing, the search range is narrowed,
Furthermore, the time required for noise discrimination is significantly shortened, and the location of the object can be searched for at high speed.

<Embodiment> FIG. 1 shows the overall configuration of an image processing apparatus according to an embodiment of the present invention, and FIG. 2 is a time chart for one horizontal scanning period of an input image.

In the illustrated image processing device, a camera 1° images an object to obtain an input image, and obtains a video signal VD of the input image.
, are given to the binarization circuit 11 and the synchronization separation circuit 12. The binarization circuit 11 binarizes the video signal VD and generates binary image data 8ν.

The synchronization separation circuit 12 separates the video signal VD into a horizontal synchronization signal HD and a vertical synchronization signal VD. Note 2
The value image data BV is shown in FIG. 2 (4), and the horizontal synchronization signal H
D is shown in FIG. 2 (2).

The binary image data BV is output to the CRT display unit 14 via the CRT interface 13 and is also provided to the image memory 16 via the data converter 15. The data converter 15 is for converting serial data into parallel data.

The horizontal and vertical synchronization signals HD, VD separated by the synchronization separation circuit 12 are sent to two timing control units 17.1.
given to 8.

One timing control section 17 controls the binary image data B.
Address data AD for writing V8 into the image memory 16 is generated. The other timing control unit 1 generates address data AD for writing compressed image data BV and ' to be described later into another image memory 19, and also generates an image clock PCK and a write enable signal WE. The image clock PCK is a clock whose one period corresponds to one pixel of the binary image data BV, and its timing is shown in FIG. 2 (1).

Further, the address data ADz is shown in FIG. 2 (5) and (7), and the write enable signal WE is shown in FIG. 2 (6) and (8), respectively.

The write enable signal WE is a signal for generating a compressed image by extracting pixel data at a predetermined pixel position from each pixel data constituting a binary image, and in this embodiment,
By extracting pixel data every three pixels in each of the horizontal and vertical directions, as shown in FIG. A compressed image 5 with an image size of 8/3 in the vertical direction is obtained.

Figure 2 (5) and (6) are the 31st (however, i・O, L2
．． . . ) and the write enable signal WE for the horizontal scanning line. The write enable signal WE is set to a low level every third pixel in order to extract the 0th, 3rd, 6th... pixel data, and the extracted data must be written into the image memory 19 (address data AD2 is also incremented every three pixels.

Figure 2 (8) shows the address data 8D2 and write enable signal WE for horizontal scanning lines other than the 31st, and the write enable signal WE remains at a high level during these horizontal scanning periods. No pixel data is extracted, and address data ADZ for writing into the image memory 19 is not generated.

In the case of this embodiment, the above compression processing is performed when binary image data BV is input to a noise removal circuit 20 (to be described later), so that the noise removal circuit 20 outputs noise-removed compressed image data BV. , ' will be output.

4 and 5 show specific examples of the timing control section 18.

FIG. 4 shows a circuit portion for generating vertical address data AD2(y), which includes a latch circuit 30, a subtraction counter 31, and an address counter 32. The vertical pixel data extraction interval ([3] in this embodiment) is latched in the latch circuit 30, and the value is stored in the subtraction counter 3.
1. The subtraction counter 31 receives the horizontal synchronization signal H
D is counted and subtracted, and when the counted value becomes zero, an output is given to the address counter 32.

Address counter 32 counts this output and outputs the counted value as vertical address data ADz(y). Note that the vertical synchronization signal VD is applied to the subtraction counter 31 and the address counter 32 as a clear signal, respectively.

FIG. 5 shows a circuit portion for generating horizontal address data ADz(x) and write enable signal WE, which includes a latch circuit 33, a subtraction counter 34, and an address counter 3.
5 and an OR circuit 36. The latch circuit 33 has a horizontal pixel data extraction interval (in this embodiment, 3
”) is latched and its value is loaded into the subtraction counter 34. The subtraction counter 34 performs a subtraction operation by counting the image clock PCK, and when the count value becomes zero, provides an output to the address counter 35 and the OR circuit 36. Address counter 35 counts this output and outputs the counted value as horizontal address data ADZ(X). OR circuit 3
6 is the output from the subtraction counter 35 and the image clock PCK
The logical sum of these is output as the write enable signal WE. Note that the horizontal synchronization signal HD is applied to the subtraction counter 34 and the address counter 35 as a clear signal, respectively.

Returning to FIG. 1, the noise removal circuit 20 detects isolated pixels in the compressed image and performs noise removal by converting the pixel data of the isolated pixels. In this embodiment, a compressed image is scanned by setting a mask 6 of 3 pixels vertically by 3 pixels horizontally as shown in FIG. When it does not match each pixel data of h, the central pixel e is determined to be an isolated pixel corresponding to noise, and the black pixel data is converted to white pixel data, and the white pixel data is converted to black pixel data, respectively.

FIG. 6 shows a circuit configuration for extracting pixel data D3 to D of each pixel a%i in the mask 6 while scanning the mask 6, and FIG. 7 shows whether the center pixel e is an isolated pixel or not. 2 shows a circuit configuration for detecting pixel data and converting pixel data according to the detection result.

In Fig. 6, 40.41 is a delay circuit that delays the compressed image data BV, ′ before noise removal by one horizontal scanning line, and 42 to 47 are delay circuits that delay the compressed image data BV, ′ by 3 clocks using the image clock PCK. This circuit is a delay circuit that delays pixel data D3 to D of each pixel a to i in the mask 6 while scanning the mask 6 with respect to the compressed image by inputting the compressed image data BV,'' to this circuit.

is extracted.

Further, in FIG. 7, 50 to 57 are pixel data D of the center pixel e.
8 and surrounding pixels ayd, each pixel data Da-Dd of f-h
, D, -Dk, and all exclusive OR circuits 5
When pixels 0 to 57 are determined to be non-coincident, the AND circuit 58 outputs an isolated pixel detection signal to the exclusive OR circuit 59. The pixel data D8 of the center pixel e is given as another input to this exclusive OR circuit 59, and when the isolated pixel detection signal is input manually, if the pixel data D8 is black pixel data, it is used as the own pixel data, and when it is white pixel data, it is used as the own pixel data. If so, each data is converted to black pixel data.

The compressed image data BV,' from which noise has been removed by the noise removal circuit 21 is converted into parallel data by the data converter 21 and then provided to the image memory 19.

Two image memories 16, 19 are connected to the CPU 22 via a data bus 25. A ROM 23 for storing programs and a RAM 24 for reading and writing various data are connected to a data bus 25 and an address bus 26 connected to the CPU 22, and the CPU 22 reads compressed images stored in the image memory 10 according to the programs. A search process for the location of the object is executed using the image memory 16, and a measurement process such as feature extraction is executed using the binary image stored in the image memory 16.

Note that FIG. 2 (3) is a signal indicating this measurement range.

Next, a series of operations of the image processing apparatus having the above configuration will be explained.

Now, when the object is imaged by the camera 10.

The video signal VD is binarized by the binarization circuit 11, and the second (l! image data BV) is converted into the image memory 1.
6, and the binary image is displayed on the CRT display section 14.

The binary image data BV is manually inputted to the noise removal circuit 20, and when inputting this data, the binary image data BV is extracted by extracting pixel data every third pixel in each of the horizontal and vertical directions of the binary image. BV is compressed. The noise removal circuit 20 detects isolated pixels in this compressed image, and the pixel data of the isolated pixels is converted into data such that a black pixel becomes a white pixel, and a white pixel becomes a black pixel.

Combining such compression processing and noise removal results in
For example, noise with a size of ~33 pixels in each horizontal and vertical direction is either removed by the compression process, or remains as a single pixel-sized noise, and the next noise removal process removes the noise as an isolated pixel. will be completely removed.

Compressed image data BV after noise removal, ' is an image] 2 After being stored in the memory 19, the CPU 22 scans the entire surface of this compressed image to search for the location of the object. In this case, each time a black pixel part in the compressed image is detected,
Although area measurement is performed for noise discrimination, the search range is significantly narrowed by the compression process, and since noise smaller than a certain size has already been removed, the search for the target object can be performed at high speed.

In the above embodiment, the binary image is compressed to a size of 179 by extracting pixel data every third pixel, but if the extraction interval is made larger, a higher degree of compression can be obtained.
It can also remove larger noises. It is also possible to change the extraction interval of pixel data in the horizontal direction and the vertical direction, and these may be set arbitrarily depending on the size and type of the object to be searched.

<Effects of the Invention> As described above, the present invention generates a binary image by binarizing an input image obtained by imaging an object, and extracts pixel data at a predetermined pixel position from the binary image. It generates a compressed image, converts the pixel data of isolated pixels in the compressed image to remove noise, and then scans the compressed image after noise removal to search for the location of the object. Therefore, the search range is narrowed and the time for noise discrimination is significantly shortened, resulting in the effect that the location of the object can be searched at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an image processing device according to an embodiment of the present invention, FIG. 2 is a time chart of the circuit shown in FIG. 1, and FIG. 3 is an explanatory diagram showing the concept of image compression processing. , FIGS. 4 and 5 are block diagrams showing specific examples of the timing control section, FIGS. 6 and 7 are block diagrams showing the circuit configuration of the noise removal circuit, and FIG. 8 is a block diagram showing the circuit configuration of the noise removal circuit. FIG. 9 is an explanatory diagram showing the concept, and FIG. 9 is an explanatory diagram showing the target object search process. 10... Camera 11... Binarization circuit 1
2...Synchronization separation circuit 18...Timing control unit 19...Image memory 20...Noise removal circuit 22...CPU

Claims (1)

[Scope of Claims] An image processing device for searching for the location of an object by processing an input image obtained by imaging the object, the device comprising: binarizing the input image to generate a binary value; means for generating an image; means for extracting pixel data at a predetermined pixel position from the binary image to generate a compressed image; and means for converting pixel data for isolated pixels in the compressed image to remove noise. and means for scanning the compressed image after noise removal to search for the location of an object.